Application of transistor device with storage function

Abstract

The invention relates to application of a transistor device with a storage function, and belongs to the technical field of semiconductor devices. In order to solve the problems of poor reliability, low integration level and the like caused by lack of a proper charge trap medium in the existing two-dimensional charge trap memory, the invention proposes that two-dimensional lead iodide (PbI2) is adopted as a charge trap layer, and efficient charge trapping is realized by utilizing the natural iodine vacancy defect of the two-dimensional lead iodide (PbI2). According to the device, a two-dimensional semiconductor material (such as WSe2) and PbI2 are integrated through a Van der Waals heterostructure to form a grid-control storage unit. The device has the advantages of large storage window, high switch ratio, high writing speed, multi-level storage capability, high durability and long data retention time. The invention provides an innovative solution for the nonvolatile memory with high integration level and low power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a transistor device with a storage function and a preparation method thereof. Aiming at the problems of insufficient reliability of charge trap media and low integration in existing two-dimensional charge trap memories, the present invention proposes to use two-dimensional lead iodide (PbI2) as the charge trap layer, realize efficient charge capture through its natural iodine vacancy defects, and combine two-dimensional semiconductor materials (such as WSe2) to construct a van der Waals heterostructure to form a gate-controlled storage unit. The device realizes non-volatile multi-level storage and simulates the function of biological synapses by electrically regulating the channel conductance state, and has characteristics such as a large storage window, a high on-off ratio, a fast writing speed, and a long data retention time, providing an innovative solution for the fields of high-integration and low-power non-volatile memories and neuromorphic computing. Background Art

[0002] With the rapid development of semiconductor device technology, the demand for non-volatile memories in the fields of the Internet of Things, artificial intelligence, and wearable electronics is increasing day by day. Traditional charge trap memories (such as flash memories) rely on three-dimensional bulk materials (such as SiO2, HfO2, etc.) as charge capture media, but their integration in two-dimensional material systems faces significant challenges: on the one hand, the charge capture efficiency of traditional media is low and there are many interface defects, resulting in a narrow storage window (usually less than 50 V) and a low on-off ratio (about 10^1–10^2), making it difficult to support multi-level storage functions; on the other hand, the interface compatibility between three-dimensional media and two-dimensional semiconductor materials is poor, which easily introduces interface state defects and reduces the stability and durability of the device (usually the cycle life is less than 10^3 times). In addition, the preparation process of the charge trap layer in the prior art is complex and difficult to be compatible with the van der Waals integration of two-dimensional materials, restricting the high-density integration and large-scale production of the device.

[0003] In recent years, two-dimensional materials (such as transition metal chalcogenides) have been regarded as ideal candidate materials for next-generation non-volatile memories due to their atomic-level thickness, excellent electrical properties, and flexible potential. However, existing two-dimensional semiconductor-based memories mostly rely on external floating gates or ionic liquids for regulation, and have problems such as high power consumption, slow response speed (millisecond level), and short data retention time (usually less than 10^3 seconds). In addition, to realize multi-level storage and neuromorphic simulation functions, complex device structures or external circuits need to be introduced, further increasing the process complexity and device size, and it is difficult to meet the design requirements of high-integration and low-power chips.

[0004] To address the above issues, there is an urgent need to develop a new type of charge trap dielectric that can form an efficient interface with two-dimensional semiconductor materials and achieve high-density charge trapping and dynamic regulation. As a two-dimensional ionic semiconductor, lead iodide (PbI2) exhibits excellent charge trapping potential due to its naturally occurring iodine vacancy defects and low formation energy characteristics. However, the defect engineering properties of PbI2 have not been fully utilized in existing research, and the charge transport mechanism at the heterojunction interface between PbI2 and two-dimensional semiconductors (such as WSe2) is not clear, resulting in device performance (such as storage window and on-off ratio) far from reaching the theoretical limit. In addition, traditional preparation processes (such as chemical vapor deposition) are difficult to precisely control the thickness and uniformity of the PbI2 film, restricting the consistency and reliability of the device.

[0005] Therefore, developing a high-performance memory transistor based on the PbI2 / WSe2 heterostructure, which can achieve a large storage window, high on-off ratio, fast response, and long-term stability through precise regulation of interface charge trapping and release, has become the key path to break through the existing technical bottlenecks. Summary of the Invention

[0006] Technical problems to be solved by the present invention: The application of a transistor device with a storage function disclosed by the present invention has good rectifying characteristics (rectification ratio) and storage characteristics (on-off ratio). The device has a large storage window, high on-off ratio, fast writing speed, multi-level storage ability, high durability, and long data retention time. When the gate voltage of the transistor device with a storage function varies between -80V and +80V, it can provide a storage window greater than 100V, supporting stable switching of the device between multiple conductance states; the on-off ratio reaches 10 3 or more under programming / erasing pulses of ±40 V, and the attenuation is less than 5% after 10 4 cycles, and the data retention exceeds 10 4 seconds, supporting multi-level storage and synaptic plasticity simulation functions.

[0007] To solve the technical problems of the present invention, the technical solution proposed is: The device includes a source-drain electrode, a channel layer, a functional layer, a dielectric layer, and a gate electrode arranged in sequence from top to bottom, where:

[0008] (1) The source-drain electrode is Au;

[0009] (2) The channel layer is two-dimensional WSe2;

[0010] (3) The functional layer is two-dimensional PbI2;

[0011] (4) The dielectric layer is HfO2;

[0012] (5) The gate electrode is Si;

[0013] When the gate voltage of the described transistor device with storage function varies between -80 V and +80 V, it can provide a storage window greater than 100 V, supporting stable switching of the device between multiple conductance states; the on / off ratio reaches 10 3 or more under programming / erasing pulses of ±40 V, and after 10 4 cycles, the attenuation is <5%, and the data retention exceeds 10 4 seconds, supporting multi-level storage and simulation of synaptic plasticity.

[0014] Preferably, when the gate voltage Vg is swept clockwise between -150 and +150 V at a drain-source voltage of Vds = 0.1 V; the device shows a large hysteresis window consistent with the polarity of the 2D semiconductor channel; such a large hysteresis window is a convincing evidence of the key charge trapping and release events involved in the electrical transport process in the 2D semiconductor channel;

[0015] The described transistor device with storage function has typical switching behavior, where the positive pulse applied to the gate drives the WSe2 channel to the off state, and then it returns to the on state when a negative voltage is applied, thus achieving effective modulation of the multi-level storage system; the switching period can be stably repeated under a ±60 V pulse sequence, with a full width at half maximum (FWHM) of 100 ms;

[0016] The described transistor device with storage function has excellent storage stability. The device monitored the on and off states for more than 1.3×10 4 s at a constant drain-source bias of 0.1 V, programmed by applying a gate pulse (+90 V, 100 ms), and a reverse gate pulse (-90 V, 100 ms) was used for the on-state setting process; during the entire monitoring process, the off-current first increased continuously and finally tended to be stable.

[0017] A transistor device with storage function adopts a three-terminal transistor structure, mainly composed of a two-dimensional PbI2 / WSe2 heterostructure, a gate dielectric, and an upper Au electrode. The two-dimensional PbI2 / WSe2 heterostructure is the core part. Using two-dimensional PbI2 as the charge trapping layer, the conductance state of the two-dimensional WSe2 channel is regulated by controlling the gate voltage, thereby achieving the effects of non-volatile multi-level storage and simulating biological synaptic functions. This structural design can give full play to the advantages of the two materials, PbI2 and WSe2, and lay a foundation for realizing the storage function.

[0018] For the described transistor device with storage function, a large number of iodine vacancies are naturally formed in the two-dimensional PbI2 functional layer due to its low formation energy. These iodine vacancies act as charge trapping centers. When applying positive and negative gate voltage pulses, they respectively capture or release electrons from the WSe2 channel, thereby realizing reversible regulation of the device conductance and endowing the device with non-volatile, multi-level storage, and artificial synaptic characteristics.

[0019] The preparation method of the described transistor device with storage function includes the following steps:

[0020] (1) Cleaning the HfO2 / Si substrate: Ultrasonic clean the HfO2 / Si substrate in acetone, isopropyl alcohol, and absolute ethanol for 10 minutes each in an ultrasonic cleaner, and then dry it with high-purity nitrogen for standby;

[0021] (2) Preparing the photoactivated ion layer: Directly grow two-dimensional PbI2 nanosheets on the surface of a clean HfO2 / Si substrate by the solution method;

[0022] (3) Preparing the WSe2 / PbI2 heterojunction: Transfer two-dimensional WSe2 nanosheets to the surface of two-dimensional PbI2 nanosheets through the van der Waals integration process, and keep the process carried out in a nitrogen atmosphere to ensure that the interfaces of the two layers of materials are clean and in close contact;

[0023] (4) Preparing the source and drain electrodes: Design electrode patterns with reasonable structures and sizes on the surface of the WSe2 / PbI2 heterojunction through photolithography or EBL methods in combination with Auto CVD software, and deposit the metal electrode Au on the surface of the heterojunction through the thermal evaporation coating process.

[0024] Preferably, the specific parameters include: 1 - 4 layers of WSe2, with a thickness of 0.7 - 3 nm, a PbI2 thickness of 1 - 5 nm, an Au thickness of 60 - 100 nm, and a channel width of 200 nm - 5 μm.

[0025] Preferably, the preparation steps of the two-dimensional PbI2 nanosheets are as follows:

[0026] (1) Take 10 mg of yellow granular PbI2 raw material and dissolve it in 10 ml of ultrapure water, and stir on a magnetic stirrer at 90 °C for more than 4 h to fully dissolve the PbI2 particles;

[0027] (2) Drop the PbI2 solution onto the surface of the substrate, and keep heating at 40 °C on a hot plate until the water completely evaporates. Regularly shaped two-dimensional PbI2 nanosheets can be seen on the substrate.

[0028] Preferably, the WSe2 layer can be prepared by two methods: mechanical exfoliation method or chemical vapor deposition method.

[0029] Preferably, the preparation steps of the WSe2 / PbI2 heterojunction are as follows:

[0030] (1) Preparation of WSe2: Directly exfoliate the mechanically exfoliated WSe2 onto PDMS to obtain WSe2 / PDMS; or transfer the WSe2 prepared by chemical vapor deposition through a wet transfer technique, and extract the WSe2 on the surface of the aqueous solution by PDMS during the transfer process to obtain WSe2 / PDMS;

[0031] (2) Transfer of WSe2: Under the microscope field of view, align the target WSe2 with the target PbI2 and keep it in contact at 80~90 °C for 2~3 minutes;

[0032] (3) Obtain the WSe2 / PbI2 heterojunction: Lift the thermal release tape to make the WSe2 fall on the PbI2 film to complete the preparation of the heterojunction.

[0033] Preferably, the steps for the surface Au electrode are as follows:

[0034] (1) Spin-coat photoresists PMMA-A4 and PMMA-A5 on the surface of the substrate with the WSe2 / PbI2 heterojunction in sequence, and bake them on a hot plate at 180 °C for 90 s respectively;

[0035] (2) Find the surrounding area of the sample in the scanning electron microscope and engrave alignment marks, develop the exposed alignment marks, take pictures with a microscope and record, and locate the sample and the engraved pattern;

[0036] (3) Perform alignment of the marks and exposure of the sample;

[0037] (4) After development, blow dry with a nitrogen gun and deposit the Au electrode by thermal evaporation.

[0038] Application of the transistor device with storage function.

[0039] Preferably, when the gate voltage of the transistor device with storage function varies between -80V and +80V, it can provide a storage window greater than 100V, supporting stable switching of the device between multiple conductance states.

[0040] Preferably, as the gate voltage of the transistor device with storage function increases, the storage window increases linearly. At the same time, the linear relationship between the increase in the storage window and the increase in the captured charge amount indicates that the charge capture ability of the PbI2 functional layer is enhanced with the expansion of the gate voltage range, so that the device can support a larger range of conductance changes, further supporting the multi-level storage characteristics of the device.

[0041] Preferably, the transistor device with storage function has stable switching behavior under periodic gate voltage pulses, can maintain stable switching performance under continuous gate voltage pulses, and has high stability when reused. The device can maintain good durability under multiple storage operations.

[0042] Preferably, for the durability test of the transistor device with storage function under programming and erasing pulses (±40 V), the device can still maintain good storage performance after more than 10,000 cycles, demonstrating the durability and stability of the device during long-term use.

[0043] Preferably, when the holding time of the transistor device with storage function in the switching state exceeds 10,000 seconds, only a slight change occurs in the current in the on state. The device has good storage charge retention ability, that is, without an external power supply, the device can maintain its stored state for a long time.

[0044] Beneficial effects:

[0045] A transistor device with storage function, its preparation method and application provided by the present invention aim at the problems of poor reliability and low integration in existing two-dimensional charge trap memories due to the lack of a suitable charge trap medium. The present invention proposes to use two-dimensional lead iodide (PbI2) as the charge trap layer and utilize its naturally occurring iodine vacancy defects to achieve efficient charge capture. The device is integrated by a two-dimensional semiconductor material (such as WSe2) and PbI2 through a van der Waals heterostructure to form a gate-controlled storage unit. Its preparation method includes preparing a PbI2 thin film by a solution method or a thermal evaporation method, combining a two-dimensional semiconductor material by mechanical exfoliation or chemical vapor deposition, constructing a heterostructure through a dry transfer technique, and fabricating electrodes using electron beam lithography and metal deposition processes. It has the following significant advantages:

[0046] 1. Efficient charge capture and ultra-large storage window Through the precise utilization of naturally occurring iodine vacancy defects in the two-dimensional PbI2 functional layer, efficient charge capture and release are achieved. When the gate voltage (Vg) scanning range of the device is ±80 V, the storage window exceeds 100 V (as Figure 2 shown), far exceeding that of traditional two-dimensional charge trap memories (usually <50 V), providing sufficient dynamic range for multi-level storage and synaptic weight regulation.

[0047] 2. High on-off ratio and fast response characteristics Under programming (+40 V) and erasing (-40 V) pulses, the on-off ratio of the device reaches more than 10^3 (as Figure 5 shown), and the writing speed is increased to the microsecond level (100 μs), significantly superior to existing two-dimensional memories based on ionic liquids or floating gate structures (on-off ratio about 10^1–10^2, response speed millisecond level).

[0048] 3. Long data retention and high durability Without an external power supply, the charge retention time of the device exceeds 10^4 seconds (about 2.8 hours), and after 10^4 programming / erasing cycles, the on / off ratio decay is less than 5% (as shown in Figure 5 , Figure 6 ), demonstrating excellent non-volatile storage stability and meeting the reliability requirements of industrial-grade storage devices.

[0049] 4. Integration of multi-level storage and synaptic simulation functions By adjusting the amplitude or number of gate voltage pulses, the device conductance can be switched between multiple discrete states, supporting multi-bit storage (such as 4-level states, as shown in Figure 3 ). At the same time, under continuous pulse stimulation, the device exhibits characteristics of paired-pulse facilitation (PPF), paired-pulse depression (PPD), and the conversion from short-term memory (STM) to long-term memory (LTM) (as shown in Figure 7 , Figure 8 ), which can accurately simulate the plasticity behavior of biological synapses and provide a hardware foundation for neuromorphic computing.

[0050] 5. Process compatibility and high integration potential The PbI2 thin film is prepared by solution method or low-temperature thermal evaporation method, with a process temperature below 200 °C, compatible with CMOS technology, and avoiding interface damage through van der Waals heterointegration technology. The device channel width can be reduced to 200 nm (as shown in the Figure 7 structure diagram), and the single-layer integration density reaches 10^8 devices / cm 2 , laying a foundation for the realization of three-dimensional stacking and high-density storage arrays.

[0051] 6. Low power consumption and wide voltage regulation range The device operating voltage is as low as ±40 V (traditional floating-gate devices require >100 V), and the storage window linearly expands with the gate voltage range (ΔVth ≈ 120 V when ΔVg = 80 V), supporting conductance regulation in a wide dynamic range (as shown in Figure 2 ), suitable for low-power edge computing and adaptive neural network applications.

[0052] In summary, through material innovation and structural optimization, the present invention breaks through the bottleneck of traditional two-dimensional memories in performance and function integration, and has high reliability, versatility, and process scalability, providing a new solution for the development of next-generation non-volatile memories and neuromorphic chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The present invention will be further described below with reference to the accompanying drawings.

[0054] Figure 1 is the transfer curve of the device of the present invention when sweeping back and forth from -100 to 100 v at Vds = 0.1 v.

[0055] Figure 2 The memory window (left axis) extracted from the device of the present invention and the calculated trapped charge amount (right axis) as a function of Vg.max (inset: optical micrograph of a typical device).

[0056] Figure 3 Under the programming / erasing pulses with a half-height width of 100 ms at +60 / -60 V, the MoS2 channel of the device of the present invention can be switched between off and on.

[0057] Figure 4 The steady-state switching behavior of the device of the present invention under a series of periodic gate pulses (±60 V, 100 ms, time interval of 1.2 s).

[0058] Figure 5 The endurance of the device of the present invention at Vds = 0.1 V during the erasing and programming pulse cycles (Vg = ±40 V).

[0059] Figure 6 The read currents of the device of the present invention in the on and off states at Vds = 0.1 V and Vg = 0 V, respectively.

[0060] Figure 7 The device structure diagram of the present invention.

[0061] Figure 8 The transfer curve of the comparative device of the present invention when sweeping back and forth from -60 to 60 V at Vds = 0.1 V. Detailed implementation manners

[0062] Example 1

[0063] A transistor device with a storage function proposed in this example, as shown in Figure 7, from top to bottom are Au source and drain electrodes, WSe2 channel layer, PbI2 functional layer, HfO2 dielectric layer, and Si gate electrode. By precisely utilizing the natural iodine vacancy defects in the two-dimensional PbI2 functional layer and combining with the van der Waals heterointegration technology, efficient charge trapping and interface non-damaging integration are achieved. The specific parameters include: 1 - 4 layers (0.7 - 3 nm) of WSe2, 1 - 5 nm of PbI2 thickness, 60 - 100 nm of Au thickness, and a channel width of 200 nm - 5 μm. The interface between PbI2 and WSe2 is flat and has no obvious defects, ensuring the long-term stability and storage performance of the device.

[0064] The specific steps are as follows:

[0065] Step 1) Clean the HfO2 / Si substrate (Suzhou Jingsi Electronics Technology) in an ultrasonic machine with acetone, isopropyl alcohol, and absolute ethanol for 10 minutes each in sequence, and then dry it with high-purity nitrogen for standby;

[0066] Step 2) Dissolve 10 mg of PbI2 raw material (yellow granular) in 10 ml of ultrapure water, and stir on a magnetic stirring table at 90 °C for more than 4 h to fully dissolve the PbI2 particles;

[0067] Step 3) Drop the PbI2 solution onto the surface of the cleaned HfO2 / Si substrate in Step 1, and heat it on a hot plate at 40 °C until the water completely evaporates, forming regular two-dimensional PbI2 nanosheets on the substrate;

[0068] Step 4) Prepare the WSe2 layer. Directly exfoliate the mechanically exfoliated WSe2 (the WSe2 crystal is provided by Shanghai Angwei Technology) onto PDMS to obtain WSe2 / PDMS;

[0069] Step 5) Through the van der Waals integration process, under the microscope field of view, align the target WSe2 obtained in Step 4 with the target PbI2 prepared in Step 3, keep it in contact at 80 - 90 °C for 2 - 3 minutes, lift the thermal release tape to make WSe2 fall on the PbI2 film, and complete the preparation of the heterojunction. The process is carried out in a nitrogen atmosphere to ensure the clean and close contact of the interfaces of the two layers of materials.

[0070] Step 6) Spin-coat photoresists PMMA - A4 and PMMA - A5 on the surface of the substrate with the WSe2 / PbI2 heterojunction in sequence, and bake them on a hot plate at 180 °C for 90 s respectively;

[0071] Step 7) Find the surrounding area of the sample in the scanning electron microscope and engrave alignment marks. Develop the exposed alignment marks, and take pictures with a microscope to record and locate the sample and the engraved pattern;

[0072] Step 8) Perform the alignment of the marks and the exposure of the sample;

[0073] Step 9) After development, dry it with a nitrogen gun. Through the EBL method, combined with the Auto CVD software, design electrode patterns with reasonable structures and sizes on the surface of the WSe2 / PbI2 heterojunction, and deposit metal electrodes (Au) on the surface of the heterojunction through the thermal evaporation coating process;

[0074] To check the gate modulation, measure the transfer curve (Ids-Vg) of the WSe2 / PbI2 device as Figure 1As shown. When the gate voltage Vg is scanned between -150 and +150 V at Vds = 0.1 V, the device shows a large hysteresis window consistent with the polarity of the 2D semiconductor channel. Thanks to the efficient charge trapping ability of iodine vacancy defects in the PbI2 layer, the storage window ΔV linearly increases to 120 V within the gate voltage range of ±80 V ( Figure 2 ), far exceeding that of traditional two-dimensional charge trap memories (usually <50 V), providing sufficient dynamic range for multi-level storage and synaptic weight regulation.

[0075] To demonstrate the switching ability of our storage device, we define the low-resistance state channel as the "on state" and the high-resistance state as the "off state". Figure 3 Illustrates the typical switching behavior of the storage device, where a positive pulse applied to the gate drives the wse2 channel to the off state and then returns to the on state when a negative voltage is applied, thus achieving effective modulation of the multi-level storage system with a switching ratio of 10 3 or more, and the writing speed is increased to the microsecond level (100 μs), significantly better than that of ionic liquid or floating gate structure devices. By adjusting the amplitude or number of gate voltage pulses, the device conductance can be switched between multiple discrete states, supporting multi-bit storage.

[0076] In addition, under the ±60 V pulse sequence (FWHM = 100 ms), the switching behavior of the device is stable and repeatable ( Figure 4 ). After 10 4 programming / erasing cycles, the switching ratio decays <5%; at a drain-source bias of 0.1 V, the data retention time >1.3×10 4 s ( Figure 5 , 6 ), meeting the reliability requirements of industrial-grade non-volatile memories.

[0077] We conducted a durability test and observed Figure 5 reproducible switching of more than 104 cycles. Stable and distinguishable on and off states are crucial for non-volatile data storage. To evaluate the stability of the device, we monitored the on and off states at a constant drain-source bias of 0.1 V for more than 1.3×10 4 s, as shown in Figure 6 . The off state is programmed by applying a gate pulse (+90 V, 100 ms), while for the on state setting process, a reverse gate pulse (-90 V, 100 ms) is used. During the entire monitoring process, the off-current first increases continuously and finally stabilizes. This is related to ionic defects, which first accumulate at the channel interface to deplete carriers, then slowly relax into the PbI2 layer and stabilize at the interface, and finally distribute at the interface.

[0078] In the gate voltage range of ±80 V, the storage window reaches 120 V; the on / off ratio reaches 10 3 or more under programming / erasing pulses (±40 V); the on / off ratio attenuation is less than 5% after 10,000 cycles; the data retention time exceeds 10,000 seconds; it supports multi-level storage and synaptic plasticity simulation functions.

[0079] Example 2

[0080] A transistor device with a storage function proposed in this example has the same structure as that in Example 1. From top to bottom, it is an Au source-drain electrode, a WSe2 channel layer, a PbI2 functional layer, an HfO2 dielectric layer, and an Si gate electrode. The specific parameters include: 1 - 4 layers (0.7 - 3 nm) of WSe2, a PbI2 thickness of 1 - 5 nm, an Au thickness of 60 - 100 nm, and a channel width of 200 nm - 5 μm. The difference between this example and Example 1 lies in the preparation method of the WSe2 layer. The specific steps are as follows:

[0081] Step 1) Clean the HfO2 / Si substrate: Use acetone, isopropyl alcohol, and absolute ethanol in sequence to ultrasonically clean the HfO2 / Si substrate (Suzhou Jingxi Electronic Technology) in an ultrasonic machine for 10 minutes each, and then dry it with high-purity nitrogen for standby.

[0082] Step 2) Prepare the two-dimensional PbI2 functional layer: Take 10 mg of PbI2 raw material (yellow granular) and dissolve it in 10 ml of ultrapure water. Stir on a magnetic stirrer at 90 °C for more than 4 hours to fully dissolve the PbI2 particles; drop the PbI2 solution onto the surface of the HfO2 / Si substrate cleaned in Step 1, and heat it on a hot plate at 40 °C until the water evaporates completely to form regular two-dimensional PbI2 nanosheets.

[0083] Step 3) Prepare the WSe2 layer (wet transfer technology): Transfer the WSe2 prepared by chemical vapor deposition through wet transfer technology. During the transfer process, extract the WSe2 on the surface of the aqueous solution through PDMS to obtain WSe2 / PDMS. Align the WSe2 / PDMS with the PbI2 thin film prepared in Step 2 under a microscope, slowly lower the PDMS until it touches the interface, and hot-press it at 80 - 90 °C for 2 - 3 minutes to achieve the hetero-integration of WSe2 and PbI2 using van der Waals forces; slowly peel off the PDMS to complete the transfer of WSe2 to the PbI2 thin film, ensuring a flat interface and no residual contaminants.

[0084] Step 4) Fabricate source and drain electrodes: Spin-coat photoresists PMMA-A4 and PMMA-A5 successively on the surface of the WSe2 / PbI2 heterojunction, and bake them on a hot plate at 180 °C for 90 seconds respectively; Define the electrode pattern by electron beam lithography (EBL) technology, and deposit an Au electrode with a thickness of 60-100 nm using thermal evaporation process to ensure an ohmic contact between the electrode and the channel layer.

[0085] Step 5) Performance test: The storage characteristics of the device are the same as those in Example 1. Specifically, the WSe2 layer prepared by wet transfer technology is combined with the PbI2 functional layer formed by solution method (process temperature < 200 °C), which has both CMOS compatibility and high integration density (10 8 devices / cm² for monolayer). The storage window exceeds 100 V within the gate voltage range of ±80 V; The on / off ratio reaches 10 3 or more under programming / erasing pulses (±40 V). After 10 4 cycles, the attenuation is less than 5%, and the data retention exceeds 10 4 seconds, supporting multi-level storage and synaptic plasticity simulation.

[0086] Comparative Example 1

[0087] This comparative example is basically the same as Example 2, and the difference lies in: Step 2): Directly fabricate the WSe2 layer on the cleaned HfO2 / Si substrate, omitting the preparation of PbI2 nanosheets.

[0088] We fabricated field-effect transistors of pure MoS2 and tested them under similar experimental conditions for comparison. Figure 8 It shows that: The device shows ohmic contact in the output curve. Due to the lack of charge trapping effect of the PbI2 functional layer, the hysteresis window of the device is negligible. Therefore, PbI2 is confirmed to be a trapping material with excellent charge storage ability, verifying the core value of PbI2 as an efficient charge trap material.

[0089] The heterostructure constructed by PbI2 and WSe2 in the present invention significantly improves the storage window and on / off ratio of the device through the efficient charge trapping and release mechanism of interfacial iodine vacancy defects. Compared with the problems of low efficiency of charge trapping media and many interfacial defects in existing two-dimensional charge trap memories, the heterojunction structure of the present invention realizes reversible regulation of the conductance state and multi-level non-volatile storage ability through the synergistic effect of the two-dimensional PbI2 functional layer and the WSe2 channel. The device has a storage window exceeding 100 V within the gate voltage range of ±80 V, an on / off ratio reaching 10³ or more, and the performance attenuation is less than 5% after 10,000 programming / erasing cycles. At the same time, it supports a microsecond-level writing speed and a data retention time of up to 10,000 seconds, providing an innovative solution for high-integration, low-power non-volatile memories and neuromorphic computing.

[0090] The present invention is not limited to the specific technical solutions described in the above embodiments, and all technical solutions formed by equivalent substitution are within the scope of protection required by the present invention.

Claims

1. Application of a transistor device with storage function, characterized in that, The device includes a source-drain electrode, a channel layer, a functional layer, a dielectric layer, and a gate electrode arranged in sequence from top to bottom, where: (1) The source-drain electrode is Au; (2) The channel layer is two-dimensional WSe2; (3) The functional layer is two-dimensional PbI2; (4) The dielectric layer is HfO2; (5) The gate electrode is Si; When the gate voltage of the described transistor device with storage function varies between -80V and +80V, it can provide a storage window greater than 100V, supporting stable switching of the device between multiple conductance states; the on / off ratio reaches 10 3 or more under programming / erasing pulses of ±40 V, and after 10 4 cycles, the attenuation is <5%, and the data retention exceeds 10 4 seconds, supporting multi-level storage and synaptic plasticity simulation functions.

2. The application of the transistor device with storage function according to claim 1, characterized in that when the gate voltage Vg is swept clockwise between -150 and +150 V at a drain-source voltage of Vds = 0.1 V; the device shows a large hysteresis window consistent with the polarity of the 2D semiconductor channel; such a large hysteresis window is a convincing evidence of the key charge capture and release events involved in the electrical transport process in the 2D semiconductor channel; The transistor device with storage function has typical switching behavior, where a positive pulse applied to the gate drives the wse2 channel to the off state, and then returns to the on state when a negative voltage is applied, thus realizing effective modulation of the multi-level storage system; the switching period can be stably repeated under a ±60 V pulse sequence, with a full width at half maximum FWHM of 100 ms; The transistor device with storage function has excellent storage stability. The device monitored the on and off states for more than 1.3×10 4 s under a constant drain-source bias of 0.1 V. Programming was performed by applying a gate pulse of +90 V for 100 ms, while a reverse gate pulse of -90 V for 100 ms was used for the on-state setting process; during the entire monitoring process, the off-current first increased continuously and finally tended to be stable.

3. The application of the transistor device with storage function according to claim 1, characterized in that The device can achieve reversible capture and release of charges through the PbI2 functional layer as a charge capture center under the action of an electric field, thereby generating an obvious change in conductivity in the two-dimensional WSe2 channel and endowing the device with multi-level non-volatile storage ability; As the gate voltage increases, the storage window increases linearly, and the linear relationship between the increase in the storage window and the increase in the captured charge amount indicates that the charge capture ability of the PbI2 functional layer is enhanced with the expansion of the gate voltage range, so that the device can support a larger range of conductivity changes, further supporting the multi-level storage characteristics of the device; The storage characteristics of the device include: being able to switch between multiple levels, thus supporting multi-bit storage; when different gate voltage pulses are applied, reversible regulation of conductivity can be achieved, and it has a high switching ratio; The device has stable switching behavior under the action of periodic gate voltage pulses. The device can maintain stable switching performance under continuous gate voltage pulses and has high stability when reused. The device can maintain good durability under multiple storage operations.

4. The application of the transistor device with storage function according to claim 1, characterized in that The heterostructure constructed by PbI2 and WSe2 significantly improves the storage window and on / off ratio of the device through the efficient charge capture and release mechanism of interfacial iodine vacancy defects. Through the synergistic effect of the two-dimensional PbI2 functional layer and the WSe2 channel, the reversible regulation of the conductance state and the multi-level non-volatile storage ability are achieved. The storage window of this device exceeds 100 V within the gate voltage range of ±80 V, the on / off ratio reaches more than 10³, and the performance degradation is less than 5% after 10,000 programming / erasing cycles. At the same time, it supports a microsecond-level writing speed and a data retention time of up to 10,000 seconds, and is applied to high-integration, low-power non-volatile memories and neuromorphic computing.

5. The application of the transistor device with storage function according to claim 1, characterized in that The preparation method of the transistor device described above includes the following steps: (1) Cleaning the HfO2 / Si substrate: The HfO2 / Si substrate is ultrasonically cleaned successively with acetone, isopropyl alcohol, and absolute ethanol for 10 minutes each step; after cleaning, it is dried with high-purity nitrogen and prepared for use. (2) Preparing the two-dimensional PbI2 functional layer: Dissolve 10 mg of PbI2 powder in 10 ml of ultrapure water and stir for 4 hours under magnetic stirring at 90 °C; drop the PbI2 solution onto the surface of the clean HfO2 / Si substrate and heat it on a hot plate at 40 °C until the water volatilizes completely to form regular two-dimensional PbI2 nanosheets. (3) Preparing the WSe2 / PbI2 heterojunction: Two-dimensional WSe2 is obtained through a wet transfer technique and then transferred onto the surface of the PbI2 thin film; in a nitrogen atmosphere, WSe2 and PbI2 nanosheets are combined through van der Waals forces to ensure a tight and clean interface between the two. (4) Preparing the source and drain electrodes: Spin-coat photoresist on the surface of the WSe2 / PbI2 heterojunction, and after exposure and development, deposit Au source and drain electrodes on the surface using a thermal evaporation process with a thickness of 60 - 100 nm to ensure good contact between the electrodes and the device. The thickness of WSe2 is 1 - 4 layers with a thickness of 0.7 - 3 nm, the thickness of PbI2 is 1 - 5 nm, the thickness of Au is 60 - 100 nm, the channel width is 200 nm - 5 mm, and the interface between PbI2 and WSe2 is flat and has no obvious defects, ensuring the long-term stability and storage performance of the device.

6. The application of the transistor device with a storage function according to claim 1, wherein, The growth process of the PbI2 layer can adopt a solution method or a low-temperature thermal evaporation method, and this method can ensure the uniformity of PbI2 and be compatible with the CMOS process to achieve large-scale integration and mass production.

7. The application of the transistor device with a storage function according to claim 1, characterized in that, The two-dimensional PbI2 functional layer uses naturally formed iodine vacancies as charge capture centers, and these iodine vacancies provide effective sites for storing charges, thereby realizing efficient charge capture and release.

8. The application of the transistor device with a storage function according to claim 1, characterized in that, The device has a non-volatile storage function. After applying the programming and erasing voltages, the device can maintain the stored charge state for more than 10,000 cycles, and the charge retention time exceeds 10,000 seconds.

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