Trench type semiconductor element

Abstract

The invention discloses a trench type semiconductor element, which comprises a substrate, a plurality of first conductor electrodes, a plurality of second conductor electrodes, a plurality of heavily doped regions and a plurality of source contact windows, the substrate is provided with a plurality of grooves, the first conductor electrodes are arranged at the bottoms of the grooves, and the second conductor electrodes are arranged in the grooves above the first conductor electrodes. The heavily doped region is arranged on the surface of the substrate between the grooves. The source contact windows are respectively connected to the heavily doped region and the first portions of the plurality of second conductor electrodes, so that the first portions are equipotential with the heavily doped region.

Description

Technical Field

[0001] The present invention relates to a trench-type semiconductor device, and more particularly to a trench-type semiconductor device for improving the figure of merit (FOM). Background Art

[0002] The figure of merit (FOM) of a transistor device is determined by the product of the on-resistance (Ron) and the gate-to-drain capacitance (Qgd). At present, in order to improve the energy conversion efficiency of the transistor device and suppress power loss, it is necessary to reduce the figure of merit (FOM) of the transistor device. Therefore, how to effectively reduce the figure of merit of the transistor device is the current continuous effort goal. Summary of the Invention

[0003] The present invention provides a trench-type semiconductor device, which can improve the figure of merit (FOM) by reducing Qgd without changing the manufacturing process or device design.

[0004] The trench-type semiconductor device of the present invention includes a substrate, a plurality of first conductor electrodes, a plurality of second conductor electrodes, a plurality of heavily doped regions, and a plurality of source contact windows. The substrate has a plurality of trenches, the first conductor electrodes are disposed at the bottoms of the respective trenches, and the second conductor electrodes are disposed in the respective trenches above the first conductor electrodes. The heavily doped regions are disposed on the surface of the substrate between the trenches. The source contact windows are respectively connected to the heavily doped regions and a first portion of the plurality of second conductor electrodes, so that the first portion is at the same potential as the heavily doped regions.

[0005] In an embodiment of the present invention, a second portion of the plurality of second conductor electrodes is electrically connected to the gate potential.

[0006] In an embodiment of the present invention, the ratio of the first portion to the second portion is from 1 / 99 to 99 / 1.

[0007] In an embodiment of the present invention, the ratio of the first portion to the second portion is from 1 / 2 to 2 / 1.

[0008] In an embodiment of the present invention, one end of each of the plurality of second conductor electrodes has an extension portion, and the trench-type semiconductor device may further include a gate bus and a plurality of gate contact windows. The gate bus is disposed above the extension portion, and the gate contact windows are respectively connected to the gate bus and the extension portions of the second portion of the plurality of second conductor electrodes.

[0009] In an embodiment of the present invention, the extending direction of the gate bus is perpendicular to the extending direction of the extension portion.

[0010] In one embodiment of the present invention, the trench-type semiconductor element may further include a source busbar, which is disposed on the source contact window and connected to the source contact window.

[0011] In one embodiment of the present invention, the trench-type semiconductor element may further include an inter-gate dielectric layer, which is disposed between the first conductor electrode and the second conductor electrode.

[0012] In one embodiment of the present invention, the trench-type semiconductor element may further include a gate dielectric layer, which is disposed between the second conductor electrode and the heavily doped region.

[0013] In one embodiment of the present invention, the trench-type semiconductor element may further include a bottom oxide layer, which is disposed between the first conductor electrode and the substrate.

[0014] In one embodiment of the present invention, the trench-type semiconductor element may further include a plurality of well regions, which are disposed between the trenches and surround the heavily doped region, and the conductivity type of the well region is different from that of the heavily doped region.

[0015] Based on the above, through layout design, the present invention can reduce the gate-to-drain capacitance (Qgd), and thus improve the figure of merit of the trench-type semiconductor element, without changing the original manufacturing process or element design.

[0016] To make the above features and advantages of the present invention more obvious and understandable, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings. Brief Description of the Drawings

[0017] Figure 1 is an exemplary layout diagram of a trench-type semiconductor element according to an embodiment of the present invention;

[0018] Figure 2 is a cross-sectional schematic diagram of a trench-type semiconductor element according to an embodiment of the present invention;

[0019] Figure 3 is Figure 2 a schematic diagram of the circuit in the trench-type semiconductor element.

[0020] Symbol Description

[0021] 100: Substrate

[0022] 102: First Conductor Electrode

[0023] 104: Second Part

[0024] 104’: First Part

[0025] 104a: Extension

[0026] 106: Heavily Doped Region

[0027] 108: Drain

[0028] 110a, 110b: Source contact window

[0029] 112: Gate bus bar

[0030] 114: Gate contact window

[0031] 116: Source bus bar

[0032] 118: Gate dielectric layer

[0033] 120: Bottom oxide layer

[0034] 122: Well region

[0035] 300: Region

[0036] ILD: Interlayer dielectric layer

[0037] IPO: Inter-poly oxide layer

[0038] R_EPI: Epitaxial resistance

[0039] Rchannel: Channel resistance

[0040] T: Trench Detailed implementation manners

[0041] The following description provides multiple embodiments for implementing different features of the present invention. Moreover, these embodiments are merely exemplary and are not intended to limit the scope and application of the present invention. Also, for clarity, the relative dimensions (e.g., length, thickness, spacing, etc.) and relative positions of regions or structural components may be reduced or enlarged. Additionally, like or identical element symbols are used in different figures to represent like or identical components or features.

[0042] Figure 1 is an exemplary layout diagram of a trench-type semiconductor device according to an embodiment of the present invention, and thus only shows some components. Figure 2 is Figure 1 a schematic cross-sectional view of the trench-type semiconductor device along the line II-II', where more complete components are shown.

[0043] Please refer to Figure 1 and Figure 2, the trench-type semiconductor device of this embodiment includes a substrate 100, a plurality of first conductor electrodes 102, a plurality of second conductor electrodes (including a first part 104' and a second part 104), a plurality of heavily doped regions 106, and a plurality of source contact windows 110a and 110b. The substrate 100 has a plurality of trenches T, where the substrate 100 may include a semiconductor material and an epitaxial layer formed thereon. The first conductor electrodes 102 are disposed at the bottoms of the respective trenches T, and the second conductor electrodes (including the first part 104' and the second part 104) are disposed in the respective trenches T above the first conductor electrodes 102, where the first conductor electrodes 102 and the second conductor electrodes (the first part 104' and the second part 104) are, for example, polysilicon structures. The heavily doped regions 106 are disposed on the surface of the substrate 100 between the trenches T, and the heavily doped regions 106 serve as the sources of the trench-type semiconductor device. As for the drain 108 of the trench-type semiconductor device, it is usually provided at the bottom of the substrate 100. In this embodiment, the source contact windows 110a and 110b are formed in the inner dielectric layer ILD, and the source contact window 110a is connected to the heavily doped region 106, and the source contact window 110b is connected to the first part 104' of the second conductor electrode, making the first part 104' and the heavily doped region 106 at the same potential. As for the first conductor electrode 102, it can be electrically connected to the heavily doped region 106 through other lines (not shown).

[0044] Please continue to refer to Figure 1 , this embodiment has 6 second conductor electrodes, among which 3 (the first part 104') are at the same potential as the heavily doped region 106 through the source contact window 110b, so the ratio of the first part 104' to the second part 104 is 1 / 1. However, the present invention is not limited thereto. In one embodiment, the ratio of the first part 104' to the second part 104 is from 1 / 99 to 99 / 1. In another embodiment, the ratio of the above-mentioned first part to the second part is from 1 / 2 to 2 / 1.

[0045] As for the second part 104 of the second conductor electrode, it is electrically connected to the gate potential. For example, in Figure 1 , one end of each of the second conductor electrodes has an extension 104a, and the trench-type semiconductor device may further include a gate bus 112 and a plurality of gate contact windows 114, where the gate bus 112 is disposed above the extension 104a, and the gate contact windows 114 are respectively connected to the gate bus 112 and the extension 104a of the second part 104 of the second conductor electrode. In one embodiment, the extending direction of the gate bus 112 is perpendicular to the extending direction of the extension 104a.

[0046] Please refer to again Figure 1 and Figure 2, the trench-type semiconductor device may further include a source bus bar 116 disposed on the source contact windows 110a and 110b and connected to the source contact windows 110a and 110b. The trench-type semiconductor device in this embodiment may further include a gate inter-dielectric layer, such as an inter-poly oxide (IPO), disposed between the first conductor electrode 102 and the second conductor electrode (including the first part 104' and the second part 104). The trench-type semiconductor device in this embodiment may further include a gate dielectric layer 118, such as a gate oxide layer, disposed between the second conductor electrode (including the first part 104' and the second part 104) and the heavily doped region 106. The trench-type semiconductor device in this embodiment may further include a bottom oxide layer 120 disposed between the first conductor electrode 102 and the substrate 100, and the bottom oxide layer 120 has a relatively thick thickness to withstand a high breakdown voltage. The trench-type semiconductor device in this embodiment may further include a plurality of well regions 122 disposed between the trenches T and surrounding the heavily doped region 106, and the conductivity type of the well region 122 is different from that of the heavily doped region 106. In one embodiment, the well region 122 is a P-type well and the heavily doped region 106 is an N+ region; in another embodiment, the well region 122 is an N-type well and the heavily doped region 106 is a P+ region.

[0047] Regarding the improved characteristics of the trench-type semiconductor device of the present invention, it will be described with Figure 3 as an example. Figure 3 is a schematic diagram of the circuit in the trench-type semiconductor device showing Figure 2 .

[0048] In Figure 3 , when current passes through the trench-type semiconductor device, since the first part 104' and the heavily doped region 106 are at the same potential, the on-resistance Rsdon is composed of the epitaxial resistance R_EPI and the single-sided channel resistance R_channel; in other words, compared with the conventional structure (both the first part 104' and the second part 104 are electrically connected to the gate potential), the channel resistance R_channel becomes twice. However, since the path from the gate to the drain becomes fewer, the region 300 of the gate-to-drain capacitance (Qgd) also decreases, so the figure of merit (FOM) is improved. Moreover, the size design and manufacturing process of the entire device do not need to be changed, and only the source contact window 110b connected to the first part 104' needs to be formed while forming the source contact window 110a.

[0049] Taking a general high-voltage (120V) component as an example, if the epitaxial resistance R_EPI accounts for about 85% of the on-resistance Rsdon, the channel resistance R_channel accounts for about 15% of the on-resistance Rsdon, and the area of the gate-to-drain capacitance (Qgd) is the proportion (100%) of the entire second conductor electrode, then the FOM (= Qgd × Rsdon) is 100%. In contrast, the ratio of the first part 104' to the second part 104 in this embodiment is 1 / 1, so the area 300 of the gate-to-drain capacitance (Qgd) is only half (50%), and the channel resistance R_channel becomes twice (30%). Therefore, the FOM is calculated as 50% × (85% + 15% × 2) = 57.5%. Thus, the design of the present invention can significantly reduce the FOM and achieve obvious improvement (the improvement degree is about 40%).

[0050] In the experiment of a trench-type semiconductor component with a voltage of 200V, if only the ratio of the first part to the second part in the second conductor electrode is changed and the designs of the other components remain unchanged, the results in Table 1 below can be obtained through experimental measurement.

[0051] Table 1

[0052] Ratio of the first part to the second part 2:1 1:1 1:2 Qgd [nC] 35％ 50％ 70％ <![CDATA[Rdson[mohm-mm 2 > 130％ 113％ 106％ FOM 45％ 56.5％ 74.2％

[0053] The "%" in Table 1 refers to the percentage based on the value 100% of a general component (where the second conductor electrode is fully connected to the gate potential) as the comparison benchmark.

[0054] It can be obtained from Table 1 that adjusting the proportion of the first part 104' with the same potential as the heavily doped region 106 can achieve the effect of improving the FOM. Moreover, the present invention can not only be used for high-voltage components but also be applied to medium-voltage or low-voltage components to improve the FOM of these components.

[0055] Although the present invention is disclosed in combination with the above embodiments, it is not intended to limit the present invention. Any person of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A trench-type semiconductor device, comprising: a substrate having a plurality of trenches; a plurality of first conductor electrodes disposed at bottoms of respective trenches; a plurality of second conductor electrodes disposed in respective trenches above the plurality of first conductor electrodes; a plurality of heavily doped regions disposed on a surface of the substrate between the plurality of trenches; and a plurality of source contact windows respectively connected to the plurality of heavily doped regions and a first portion of the plurality of second conductor electrodes to make the first portion equipotential with the plurality of heavily doped regions.

2. The trench-type semiconductor device according to claim 1, wherein a second portion of the plurality of second conductor electrodes is electrically connected to a gate potential.

3. The trench-type semiconductor device according to claim 2, wherein a ratio of the first portion to the second portion is from 1 / 99 to 99 / 1.

4. The trench-type semiconductor device according to claim 2, wherein a ratio of the first portion to the second portion is from 1 / 2 to 2 / 1.

5. The trench-type semiconductor device according to claim 2, wherein one end of each of the second conductor electrodes has an extension portion, and the trench-type semiconductor device further comprises: a gate bus disposed above the extension portion; and a plurality of gate contact windows respectively connecting the gate bus and the extension portion of the second portion of the plurality of second conductor electrodes.

6. The trench-type semiconductor device according to claim 5, wherein an extending direction of the gate bus is perpendicular to an extending direction of the extension portion.

7. The trench-type semiconductor device according to claim 1, further comprising a source bus disposed on and connected to the plurality of source contact windows.

8. The trench-type semiconductor device according to claim 1, further comprising a gate inter-dielectric layer disposed between the plurality of first conductor electrodes and the plurality of second conductor electrodes.

9. The trench-type semiconductor device according to claim 1, further comprising a gate dielectric layer disposed between the plurality of second conductor electrodes and the plurality of heavily doped regions.

10. The trench-type semiconductor device according to claim 1, further comprising a bottom oxide layer disposed between the plurality of first conductor electrodes and the substrate.

11. The trench-type semiconductor device according to claim 1, further comprising a plurality of well regions disposed between the plurality of trenches and surrounding the plurality of heavily doped regions, and a conductivity type of the plurality of well regions is different from a conductivity type of the plurality of heavily doped regions.

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