Buried gate diamond field effect transistor and preparation method thereof

Abstract

The invention provides a buried-gate diamond field effect transistor and a preparation method, the buried-gate diamond field effect transistor comprises a diamond substrate, a multilayer diamond epitaxial layer, a drain electrode and a source electrode, and the drain electrode is arranged at the bottom of the diamond substrate; the plurality of diamond epitaxial layers are arranged at the top of the diamond substrate, the plurality of diamond epitaxial layers are stacked from bottom to top, a groove is formed in the diamond epitaxial layer connected with the diamond substrate, and a grid electrode is arranged in the groove; and the source electrode is arranged at the top of the uppermost diamond epitaxial layer. The vertical structure transistor is formed through the vertical stacking arrangement of the diamond substrate and the multiple epitaxial layers, and the buried gate design is combined, so that the voltage endurance capability and the power density of the transistor are remarkably improved, higher breakdown and power are further obtained, and meanwhile, the inherent high thermal conductivity characteristic of diamond is kept.

Description

Technical Field

[0001] The present invention belongs to the technical field of transistors, and more specifically, relates to a buried-gate diamond field effect transistor. The present invention also relates to a method for preparing the buried-gate diamond field effect transistor. Background Art

[0002] Field effect transistor is a semiconductor device that uses electric field effect to control current and is a voltage-controlled device. With its high input impedance, low power consumption and excellent switching characteristics, field effect transistor has become a core component of modern electronic circuits.

[0003] Currently, the main materials used to make field-effect transistors are silicon and silicon carbide, but their performance has been developed to a level close to the theoretical limit of the material.

[0004] However, as power electronic systems develop towards high frequency, high power and low loss, the requirements for power semiconductor transistors are getting higher and higher. Currently, buried gate transistors made of silicon carbide and silicon materials are difficult to achieve higher breakdown and power due to the limitations of material properties. Summary of the invention

[0005] The object of the present invention is to provide a buried-gate diamond field effect transistor to obtain higher breakdown and power.

[0006] To achieve the above-mentioned purpose, the technical solution adopted by the present invention is: to provide a buried-gate diamond field-effect transistor, comprising a diamond substrate, a multi-layer diamond epitaxial layer, a drain electrode and a source electrode, wherein the drain electrode is arranged at the bottom of the diamond substrate; the multi-layer diamond epitaxial layer is arranged at the top of the diamond substrate, and the multiple diamond epitaxial layers are stacked from bottom to top, and a groove is opened on the diamond epitaxial layer connected to the diamond substrate, and a gate is arranged in the groove; the source electrode is arranged on the top of the uppermost diamond epitaxial layer.

[0007] In a possible implementation, the diamond substrate is a heavily doped p-type diamond substrate, and the diamond epitaxial layer includes a first lightly doped p-type diamond layer, a second lightly doped p-type diamond layer, and a heavily doped p-type diamond layer arranged in sequence from bottom to top.

[0008] In a possible implementation manner, a first dielectric layer is provided between the gate and the trench, and a second dielectric layer is provided between the gate and the upper lightly doped p-type diamond layer.

[0009] The beneficial effects of the buried-gate diamond field-effect transistor provided by the present invention are as follows: Compared with the prior art, the present invention forms a vertical-structure transistor through the vertical stacked arrangement of a diamond substrate and multiple epitaxial layers, and combines the buried-gate design, significantly improving the breakdown voltage and power density of the transistor, thereby obtaining higher breakdown and power, while maintaining the inherent high thermal conductivity of diamond.

[0010] The present invention also relates to a method for manufacturing a buried-gate diamond field-effect transistor for manufacturing the aforementioned buried-gate diamond field-effect transistor, including: S1. Epitaxially grow a first lightly doped P-type diamond layer on a heavily doped p-type diamond substrate by microwave plasma chemical vapor deposition; S2. Photolithographically pattern a trench window on the first lightly doped P-type diamond layer, etch the trench, and remove the photoresist; S3. Deposit a first dielectric layer in the trench and remove the dielectric outside the trench; S4. Photolithographically pattern a gate window on the first dielectric layer, deposit gate metal, and use a lift-off process to form a gate electrode from the gate metal; S5. Deposit a dielectric layer on top of the gate electrode and remove the dielectric outside the trench; S6. Epitaxially grow a second lightly doped P-type diamond layer on top of the first lightly doped P-type diamond layer by microwave plasma chemical vapor deposition; S7. Epitaxially grow a heavily doped p-type diamond layer on top of the second lightly doped P-type diamond layer by microwave plasma chemical vapor deposition; S8. Deposit source metal and drain metal on the top of the heavily doped p-type diamond layer and the bottom of the heavily doped p-type diamond substrate respectively, and the source metal and drain metal are annealed at high temperature to form a source electrode and a drain electrode. In a possible implementation, in steps S1, S6, and S7, boron elements are doped in the doped p-type diamond substrate, the first lightly doped diamond layer, the second lightly doped diamond layer, and the heavily doped diamond layer. Among them, the doping concentration of boron elements in the heavily doped diamond substrate and the heavily doped diamond layer is 10 18 to 10 22 cm -3 , the doping concentration of boron elements in the first lightly doped diamond layer and the second lightly doped diamond layer is 10 12 to 10 19 cm -3 , the thickness is 10 nanometers to 10 millimeters, and the doping thickness of boron elements in the heavily doped p-type diamond layer is 10 nanometers to 10 millimeters.

[0011] In a possible implementation, in step S2, the trench depth is 0 to 100 micrometers.

[0012] In a possible implementation, in step S3, any one of plasma enhanced chemical vapor deposition, atomic layer deposition, evaporation, or magnetron sputtering can be used to deposit the first dielectric layer. The thickness of the first dielectric layer is less than the depth and width of the trench. The first dielectric layer includes one or more of aluminum oxide, aluminum nitride, silicon dioxide, silicon nitride, or hafnium dioxide, and any one of wet etching, dry etching, or polishing processes can be used for dielectric removal.

[0013] In a possible implementation, in step S4, the gate metal includes any one or more of titanium, aluminum, platinum, gold, nickel, tungsten, or palladium.

[0014] In a possible implementation, in step S5, any one of plasma enhanced chemical vapor deposition, atomic layer deposition, evaporation, or magnetron sputtering can be used to deposit the second dielectric layer. The first dielectric layer includes one or more of aluminum oxide, aluminum nitride, silicon dioxide, silicon nitride, or hafnium dioxide, and any one of wet etching, dry etching, or polishing processes can be used for dielectric removal.

[0015] In a possible implementation, the source metal and the drain metal include any one or more of titanium, aluminum, platinum, gold, nickel, tungsten, or palladium.

[0016] The beneficial effect of the method for manufacturing a buried gate diamond field effect transistor provided by the present invention is that: compared with the prior art, through the vertical integration of multi-layer epitaxy and buried gate processes, and by combining the intrinsic advantages of high thermal conductivity and high breakdown field strength of diamond materials, the present invention realizes the high breakdown voltage and low loss characteristics of the transistor, while ensuring the controllability and repeatability of the process flow. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 It is a schematic structural diagram of the first lightly doped P-type diamond layer after step S1 is completed provided by the embodiment of the present invention; Figure 2 It is a schematic structural diagram of the trench after step S2 is completed provided by the embodiment of the present invention; Figure 3 It is a schematic structural diagram of the first dielectric layer after step S3 is completed provided by the embodiment of the present invention; Figure 4Schematic diagram of the gate after step S4 in the embodiments of the present invention; Figure 5 Schematic diagram of the second dielectric layer after step S5 in the embodiments of the present invention; Figure 6 Schematic diagram of the second lightly doped P-type diamond layer after step S6 in the embodiments of the present invention; Figure 7 Schematic diagram of the heavily doped p-type diamond layer after step S7 in the embodiments of the present invention; Figure 8 Schematic diagram of the buried-gate diamond field-effect transistor after step S8 in the embodiments of the present invention.

[0019] Among them, the reference numerals in the figure are as follows: 1, diamond substrate; 2, drain electrode; 3, diamond epitaxial layer; 4, source electrode; 301, first lightly doped P-type diamond layer; 302, second lightly doped p-type diamond layer; 303, heavily doped p-type diamond layer; 304, gate; 305, first dielectric layer; 306, second dielectric layer; 307, trench; 308, gate window. Detailed implementation manners

[0020] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0021] It should be further noted that the drawings and embodiments of the present invention mainly describe and illustrate the concept of the present invention. On the basis of this concept, the specific forms and settings of some connection relationships, positional relationships, power mechanisms, power supply systems, hydraulic systems and control systems may not be completely described. However, on the premise that those skilled in the art understand the concept of the present invention, those skilled in the art can implement the above specific forms and settings in a well-known manner.

[0022] When an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0023] The orientation or positional relationship indicated by terms such as "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation on the present invention.

[0024] The terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more, and "several" means one or more, unless otherwise specifically defined.

[0025] The buried-gate diamond field-effect transistor provided by the present invention will now be described.

[0026] Embodiment 1 As Figure 8 shown, the buried-gate diamond field-effect transistor includes a diamond substrate 1, a multi-layer diamond epitaxial layer 3, a drain electrode 2, and a source electrode 4. The drain electrode 2 is provided at the bottom of the diamond substrate 1; the multi-layer diamond epitaxial layer 3 is provided on the top of the diamond substrate 1, and the multi-layer diamond epitaxial layer 3 is stacked from bottom to top and is connected to the diamond substrate 1. A trench 307 is formed in the diamond epitaxial layer 3, and a gate electrode 304 is provided in the trench 307; the source electrode 4 is provided on the top of the uppermost diamond epitaxial layer 3.

[0027] The beneficial effects of the buried-gate diamond field-effect transistor provided in this embodiment are as follows: Compared with the prior art, the buried-gate diamond field-effect transistor provided in this embodiment forms a vertical structure transistor through the vertical stacking arrangement of the diamond substrate 1 and the multi-layer epitaxial layer. Combining the design of the buried gate 304 significantly improves the breakdown voltage resistance and power density of the transistor, thereby obtaining higher breakdown and power, while maintaining the inherent high thermal conductivity of diamond.

[0028] In this embodiment, the diamond substrate 1 is a heavily doped p-type diamond substrate 1, and the diamond epitaxial layer 3 includes a first lightly doped P-type diamond layer 301, a second lightly doped p-type diamond layer 302, and a heavily doped p-type diamond layer 303 arranged in sequence from bottom to top. The gradient doping structure realizes the precise control of carriers. The first lightly doped P-type diamond layer 301 and the second lightly doped p-type diamond layer 302 effectively expand the depletion region width to increase the breakdown voltage, while the topmost heavily doped p-type diamond layer 303 reduces the contact resistance and optimizes the conduction characteristics.

[0029] Finally, a first dielectric layer 305 is provided between the gate 304 and the trench 307, and a second dielectric layer 306 is provided between the gate 304 and the upper lightly doped p-type diamond layer. The double dielectric layer structure forms a composite insulation system, which not only suppresses the leakage current of the gate 304 but also enhances the interface stability. At the same time, the threshold voltage can be adjusted by selecting the dielectric material, improving the reliability of the transistor.

[0030] Embodiment 2 Combined with Figures 1 to 8 As shown, the present invention also relates to a method for manufacturing a buried-gate diamond field-effect transistor for manufacturing the aforementioned buried-gate diamond field-effect transistor, including: S1. Epitaxially grow a first lightly doped P-type diamond layer 301 on the heavily doped p-type diamond substrate 1 by microwave plasma chemical vapor deposition; S2. Lithographically pattern the trench 307 window on the first lightly doped P-type diamond layer 301, etch the trench 307, and remove the photoresist; S3. Deposit a first dielectric layer 305 in the trench 307 and remove the dielectric outside the trench 307; S4. Lithographically pattern the gate window 308 on the first dielectric layer 305, deposit the gate metal, and use the lift-off process to form the gate 304 with the gate metal; S5. Deposit a dielectric layer on the top of the gate 304 and remove the dielectric outside the trench 307; S6. Epitaxially grow a second lightly doped P-type diamond layer on the top of the first lightly doped P-type diamond layer 301 by microwave plasma chemical vapor deposition; S7. Epitaxially grow a heavily doped p-type diamond layer 303 on the top of the second lightly doped P-type diamond layer by microwave plasma chemical vapor deposition; S8. Deposit source metal and drain metal on the top of the heavily doped p-type diamond layer 303 and the bottom of the heavily doped p-type diamond substrate 1 respectively, and the source metal and drain metal are annealed at high temperature to form the source electrode 4 and the drain electrode 2.

[0031] The beneficial effects of the method for manufacturing a buried-gate diamond field-effect transistor provided by the present invention are as follows: Compared with the prior art, through the vertical integration of multi-layer epitaxy and buried-gate processes, combined with the intrinsic advantages of high thermal conductivity and high breakdown field strength of diamond materials, the present invention realizes the high breakdown voltage and low loss characteristics of the transistor, while ensuring the controllability and repeatability of the process flow.

[0032] In this embodiment, in steps S1, S6, and S7, boron elements are doped in the doped p-type diamond substrate 1, the first lightly doped diamond layer, the second lightly doped diamond layer, and the heavily doped diamond layer. Among them, the doping concentration of boron elements in the heavily doped diamond substrate 1 and the heavily doped diamond layer is 10^18 to 10^22 cm^-3, and the doping concentration of boron elements in the first lightly doped diamond layer and the second lightly doped diamond layer is 10^12 to 10^19 cm^-3, with a thickness of 10 nanometers to 10 millimeters. The doping thickness of boron elements in the heavily doped p-type diamond layer 303 is 10 nanometers to 10 millimeters. The gradient boron doping design, by precisely regulating the carrier concentration, takes into account both the improvement of the breakdown voltage and the optimization of the ohmic contact, and at the same time, the wide thickness range adapts to the requirements of different power scenarios.

[0033] In addition, in step S2, the depth of the trench 307 is 0 to 100 micrometers. The flexible trench 307 depth design can optimize the electric field distribution, avoid local electric field concentration, enhance the breakdown voltage of the transistor, and at the same time provide a shorter carrier transmission path for high-frequency applications.

[0034] In this embodiment, in step S3, the first dielectric layer 305 can be deposited using any one of plasma-enhanced chemical vapor deposition, atomic layer deposition, evaporation, or magnetron sputtering. The thickness of the first dielectric layer 305 is less than the depth and width of the trench 307. The first dielectric layer 305 includes one or more of aluminum oxide, aluminum nitride, silicon dioxide, silicon nitride, or hafnium dioxide, and any one of wet etching, dry etching, or polishing processes can be used for dielectric removal. The process compatibility and the combination of high-insulation dielectric materials ensure the denseness of the dielectric layer and the interface quality, suppress the gate 304 leakage current, and improve the breakdown voltage stability.

[0035] Preferably, in step S4, the gate metal includes any one or more of titanium, aluminum, platinum, gold, nickel, tungsten, and palladium. Using high work function metals to optimize the barrier characteristics of the gate 304 and reduce the contact resistance, while the selection of multiple metals adapts to the energy band matching requirements of different dielectric interfaces.

[0036] As Figure 5 shown, in step S5, the second dielectric layer 306 can be deposited using any one of plasma-enhanced chemical vapor deposition, atomic layer deposition, evaporation, or magnetron sputtering. The first dielectric layer 305 includes one or more of aluminum oxide, aluminum nitride, silicon dioxide, silicon nitride, or hafnium dioxide, and any one of wet etching, dry etching, or polishing processes can be used for dielectric removal. The double dielectric layer forms a composite insulation barrier, further enhancing the isolation effect between the gate 304 and the channel, and at the same time reducing the interface stress through material matching and improving the long-term reliability.

[0037] Finally, the source metal and the drain metal include any one or more of titanium, aluminum, platinum, gold, nickel, tungsten, and palladium. The ohmic contact design between the high thermal stability metal and diamond reduces the electrode resistance and withstands the thermal stress under high-power conditions, ensuring the efficient conduction and heat dissipation capabilities of the transistor.

[0038] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A buried-gate diamond field-effect transistor, characterized in that Comprising: A diamond substrate (1); A drain electrode (2) disposed at the bottom of the diamond substrate (1); A multi-layer diamond epitaxial layer (3) disposed on the top of the diamond substrate (1), and a plurality of the diamond epitaxial layers (3) are stacked and arranged from bottom to top. A trench (307) is formed in the diamond epitaxial layer (3) connected to the diamond substrate (1), and a gate (304) is disposed in the trench (307); A source electrode (4) disposed on the top of the uppermost diamond epitaxial layer (3).

2. The buried-gate diamond field-effect transistor according to claim 1, wherein: The diamond substrate (1) is a heavily doped p-type diamond substrate (1), and the diamond epitaxial layer (3) includes a first lightly doped P-type diamond layer (301), a second lightly doped p-type diamond layer (302), and a heavily doped p-type diamond layer (303) arranged in sequence from bottom to top.

3. The buried-gate diamond field-effect transistor according to claim 2, wherein: A first dielectric layer (305) is disposed between the gate (304) and the trench (307), and a second dielectric layer (306) is disposed between the gate (304) and the upper lightly doped p-type diamond layer.

4. A method for fabricating a buried-gate diamond field-effect transistor for fabricating the buried-gate diamond field-effect transistor as described in claim 3, characterized in that, Comprising: S1. Epitaxially grow a first lightly doped P-type diamond layer (301) on a heavily doped p-type diamond substrate (1) by microwave plasma chemical vapor deposition; S2. Photolithograph a window of the trench (307) on the first lightly doped P-type diamond layer (301), etch the trench (307), and remove the photoresist; S3. Deposit a first dielectric layer (305) in the trench (307), and remove the dielectric outside the trench (307); S4. Photolithograph a gate window (308) on the first dielectric layer (305), deposit gate metal, and use a lift-off process to form the gate (304) from the gate metal; S5. Deposit a dielectric layer on the top of the gate (304), and remove the dielectric outside the trench (307); S6. Epitaxially grow a second lightly doped P-type diamond layer on the top of the first lightly doped P-type diamond layer (301) by microwave plasma chemical vapor deposition; S7. Epitaxially grow a heavily doped p-type diamond layer (303) on the top of the second lightly doped P-type diamond layer by microwave plasma chemical vapor deposition; S8. Deposit source metal and drain metal on the top of the heavily doped p-type diamond layer (303) and the bottom of the heavily doped p-type diamond substrate (1) respectively, and the source metal and the drain metal are subjected to high-temperature annealing to form a source electrode (4) and a drain electrode (2).

5. The method for manufacturing a buried-gate diamond field-effect transistor according to claim 4, wherein: In steps S1, S6, and S7, boron elements are doped in the doped p-type diamond substrate (1), the first lightly doped diamond layer, the second lightly doped diamond layer, and the heavily doped diamond layer. Among them, the boron element doping concentration in the heavily doped diamond substrate (1) and the heavily doped diamond layer is 10^18 to 10^22 cm^-3, the boron element doping concentration in the first lightly doped diamond layer and the second lightly doped diamond layer is 10^12 to 10^19 cm^-3, the thickness is 10 nanometers to 10 millimeters, and the doping thickness of boron elements in the heavily doped p-type diamond layer (303) is 10 nanometers to 10 millimeters.

6. The method for manufacturing a buried gate diamond field effect transistor according to claim 4, characterized in that: In step S2, the depth of the trench (307) is 0 to 100 micrometers.

7. The method for manufacturing a buried gate diamond field effect transistor according to claim 4, characterized in that: In step S3, the first dielectric layer (305) can be deposited using any one of plasma enhanced chemical vapor deposition, atomic layer deposition, evaporation, or magnetron sputtering. The thickness of the first dielectric layer (305) is less than the depth and width of the trench (307). The first dielectric layer (305) includes one or more of aluminum oxide, aluminum nitride, silicon dioxide, silicon nitride, or hafnium dioxide, and any one of wet etching, dry etching, or polishing processes can be used when removing the dielectric.

8. The method for manufacturing a buried gate diamond field effect transistor according to claim 4, characterized in that: In step S4, the gate metal includes any one or more of titanium, aluminum, platinum, gold, nickel, tungsten, and palladium.

9. The method for manufacturing a buried gate diamond field effect transistor according to claim 4, characterized in that: In step S5, the second dielectric layer (306) can be deposited using any one of plasma enhanced chemical vapor deposition, atomic layer deposition, evaporation, or magnetron sputtering. The first dielectric layer (305) includes one or more of aluminum oxide, aluminum nitride, silicon dioxide, silicon nitride, or hafnium dioxide, and any one of wet etching, dry etching, or polishing processes can be used when removing the dielectric.

10. The method for manufacturing a buried gate diamond field effect transistor according to claim 9, characterized in that: The source metal and the drain metal include any one or more of titanium, aluminum, platinum, gold, nickel, tungsten, and palladium.

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