A heterojunction-based silicon carbide trench MOSFET device structure and its preparation process

Abstract

The present invention relates to the field of MOS semiconductor technology and discloses a heterojunction-based silicon carbide trench MOSFET device structure and its preparation process, comprising a plurality of mutually parallel MOS cells, each of which includes a drain, a source, a gate, and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer. A trench is formed on the upper surface of each MOS cell, below the gate, and an N+ layer is deposited within the trench, wherein the N+ layer includes a left N+ layer and a right N+ layer. The present invention effectively disperses the electric field concentration phenomenon at the bottom of the trench by designing a split left N+ layer and a right N+ layer within the trench, combined with a central N-layer or a central P-layer filled in the middle. Furthermore, the right-angled triangle arrangement of the blocking and isolating bubbles further suppresses the electric field peak at the edge of the N drift layer, significantly improving the breakdown voltage and reliability of the device, making it suitable for high-voltage applications.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS semiconductors, and in particular to a heterojunction-based silicon carbide trench MOSFET device structure and a preparation process thereof. Background Art

[0002] Silicon carbide (SiC) MOSFETs have become an ideal choice for high-voltage, high-power devices due to their advantages, including high breakdown field strength, high thermal conductivity, and low conduction losses. However, traditional planar SiC MOSFETs face the "silicon limit" conflict between specific on-resistance (Ron,sp) and breakdown voltage (BV). While the trench structure improves conduction characteristics, it also faces challenges such as poor gate oxide reliability, reduced carrier mobility due to heterojunction interface defects, and electric field concentration at the trench bottom.

[0003] An existing patent discloses a heterojunction-based silicon carbide trench-gate MOSFET and its manufacturing method (publication number CN116130513A). The structure includes a drain electrode, a first conductivity type substrate, a first conductivity type epitaxial layer, a second conductivity type shielding region, a second trench, a first trench, second conductivity type doped polysilicon, a gate dielectric, a gate electrode, a second conductivity type well region, a first conductivity type source region, an isolation dielectric layer, and a source electrode. In the technology disclosed in this patent, the single conductive layer design within the trench limits carrier transport efficiency, while the flat substrate structure easily leads to uneven current distribution, further restricting device performance optimization. Summary of the Invention

[0004] In order to solve existing technical problems, the present invention provides a heterojunction-based silicon carbide trench MOSFET device structure and its preparation process, which solves the problems of electric field concentration, high on-resistance, large switching loss and insufficient structural scalability of existing devices.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a heterojunction-based silicon carbide trench MOSFET device structure includes a plurality of mutually parallel MOS cells, wherein each MOS cell includes a drain, a source, a gate, and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer. A trench is formed on the upper surface of each MOS cell below the gate, and an N+ layer is deposited inside the trench. The N+ layer includes a left N+ layer and a right N+ layer, and a filling dielectric is formed between the left N+ layer and the right N+ layer by ion implantation.

[0006] The cross-sectional profile of the N substrate layer inside a single MOS cell is convex on both sides and concave in the middle. Contact layers are provided on both sides of the N substrate layer in the single MOS cell, and the contact layers are in ohmic contact with the drain.

[0007] Furthermore, the filling medium is a central N-layer, and the contact layer is a P-type contact layer.

[0008] Furthermore, a semicircular groove is formed on the surface of the N-well layer by etching, a metal dielectric layer is deposited in the semicircular groove, and the metal dielectric layer is in direct contact with the source electrode.

[0009] Furthermore, a plurality of blocking spacer bubbles are formed inside a single MOS cell and on the left and right sides of the N drift layer by ion implantation. The plurality of blocking spacer bubbles are arranged in a right triangle, and the hypotenuse of the right triangle is close to the N+ layer.

[0010] Furthermore, the filling medium is a central P-layer, and the contact layer is an N-type contact layer.

[0011] Furthermore, a doped P-layer is formed at the inner bottom of the central N-layer by ion implantation.

[0012] A process for preparing a heterojunction-based silicon carbide trench MOSFET device structure, comprising the following specific steps:

[0013] S1. Growing an N drift layer on the N substrate layer, and sequentially forming a P+ layer, an N well layer, and a P well layer by ion implantation;

[0014] S2, groove etching is performed on the upper surface of the cell, and an N+ layer is deposited on the inner wall of the groove, which is separated into a left N+ layer and a right N+ layer by mask technology;

[0015] S3, forming a central N- layer between the left and right N+ layers by ion implantation, and implanting a doped P- layer at the bottom of the central N- layer;

[0016] S4, implanting a P-type contact layer into the high convex areas on both sides of the N substrate to form an ohmic contact with the drain;

[0017] S5, etching a semicircular groove on the surface of the N-well layer, depositing a metal dielectric layer and making direct contact with the source;

[0018] S6. Grow a gate oxide layer above the trench, deposit polysilicon to form a gate, prepare a drain on the back of the device, prepare a source on the front and connect it to a metal dielectric layer.

[0019] Furthermore, in step S4, barrier spacer bubbles arranged in a right-angled triangle can be injected on the left and right sides of the N drift layer, with the hypotenuse facing the N+ layer.

[0020] The present invention provides a heterojunction-based silicon carbide trench MOSFET device structure and its preparation process. Compared with the existing technology, this method achieves the following effects:

[0021] 1. The present invention effectively disperses the electric field concentration phenomenon at the bottom of the trench through the design of split left N+ layer and right N+ layer in the trench, combined with the central N- layer or central P- layer filled in the middle. In addition, the right-angled triangle arrangement of the barrier bubble further suppresses the electric field peak at the edge of the N drift layer, significantly improving the breakdown voltage and reliability of the device, making it suitable for high-voltage application scenarios.

[0022] 2. The present invention employs a special-shaped structure with high convex sides and a concave center in the N-type substrate layer. P-type or N-type contact layers are provided in the high-convex areas on both sides, forming a low-resistance ohmic contact with the drain. This design shortens the vertical current path, reduces on-resistance, improves conduction efficiency at high currents, and optimizes power transmission performance.

[0023] 3. The present invention etches a semicircular groove on the surface of the N-well layer and deposits a metal dielectric layer, enabling direct contact with the source. This structure increases the source contact area, reduces contact resistance and parasitic capacitance, and optimizes carrier injection efficiency, helping to improve switching speed and dynamic response performance.

[0024] 4. The present invention supports a variety of heterojunction configurations and optional functional layers through the fabrication process, achieving precise doping through ion implantation and masking techniques. This flexibility allows for customized device parameters tailored to different application requirements while maintaining process compatibility and scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Schematic diagram of Example 1 of the present invention;

[0026] Figure 2 This is a schematic diagram of Example 2 of the present invention;

[0027] Figure 3 This is a schematic diagram of Example 3 of the present invention;

[0028] Figure 4 This is a schematic diagram of Example 4 of the present invention;

[0029] Figure 5 This is a schematic diagram of Example 5 of the present invention.

[0030] In the figure: 1. Drain; 2. Source; 3. Gate; 4. P+ layer; 5. N-well layer; 6. P-well layer; 7. N substrate layer; 8. N-drift layer; 9. N+ layer; 10. Centered N-layer; 11. P-type contact layer; 12. Blocking bubble; 13. N-type contact layer; 14. Centered P-layer; 15. Doped P-layer; 21. Metal dielectric layer; 91. Left N+ layer; 92. Right N+ layer. DETAILED DESCRIPTION

[0031] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] like Figure 1-5 As shown, according to one aspect of the present invention, a process for preparing a heterojunction-based silicon carbide trench MOSFET device structure is provided, and the specific steps are:

[0033] Step 1: growing an N drift layer 8 on the N substrate layer 7, and sequentially forming a P+ layer 4, an N well layer 5, and a P well layer 6 by ion implantation;

[0034] Step 2: perform trench etching on the upper surface of the cell and deposit an N+ layer 9 on the inner wall of the trench, which is then separated into a left N+ layer 91 and a right N+ layer 92 by masking technology;

[0035] Step 3: Form a central N- layer 10 between the left and right N+ layers 9 by ion implantation, and implant a doped P- layer 15 at the bottom of the central N- layer 10;

[0036] Step 4: Injection of P-type contact layer 11 is formed in the high convex area on both sides of N substrate 7 to form ohmic contact with drain 1; this step can also inject right-angled triangle-shaped blocking spacer bubbles 12 on the left and right sides of N drift layer 8, with the hypotenuse facing N+ layer 9.

[0037] Step 5: etching a semicircular groove on the surface of the N-well layer 5, depositing a metal dielectric layer 21 in direct contact with the source 2;

[0038] Step 6: Grow a gate oxide layer above the trench, deposit polysilicon to form a gate 3, prepare a drain 1 on the back of the device, prepare a source 2 on the front and connect it to the metal dielectric layer 21

[0039] Example 1

[0040] like Figure 1Figure 1 shows a heterojunction-based silicon carbide trench MOSFET device structure comprising several juxtaposed MOS cells. Each MOS cell comprises a drain 1, a source 2, a gate 3, and a semiconductor epitaxial layer. The semiconductor epitaxial layer comprises an N substrate layer 7, an N drift layer 8, a P+ layer 4, an N well layer 5, and a P well layer 6. A trench is defined on the upper surface of the MOS cell, below the gate 3. An N+ layer 9 is deposited within the trench. The N+ layer 9 comprises a left N+ layer 91 and a right N+ layer 92. A filling dielectric is formed between the left and right N+ layers 91 and 92 via ion implantation. The cross-sectional profile of the N substrate layer 7 within the MOS cell is convex on both sides and concave in the middle. Contact layers are provided on both sides of the N substrate layer 7 within the MOS cell, making ohmic contact with the drain 1. The filling dielectric is a central N- layer 10, and the contact layer is a P-type contact layer 11. The central N- layer 10 is filled in the trench, that is, a lightly doped N- layer is implanted between the left and right N+ layers 9 to form a low-resistance current channel and reduce the channel resistance.

[0041] Separate left and right N+ layers 9 are deposited on the inner walls of the gate trench, with an N- layer 10 implanted in the middle as a filler. The N substrate layer 7 is designed as a special-shaped structure with high convex sides and a low concave center. A P-type contact layer 11 is formed in the raised areas to achieve ohmic contact with the drain. The N+ / N- layered design within the trench enhances carrier mobility and reduces on-resistance. The special-shaped substrate structure combined with the P-type contact layer optimizes the drain current path, improving current density and heat dissipation.

[0042] Example 2

[0043] like Figure 2 As shown, a semicircular groove is formed on the surface of the N-well layer 5 by etching, and a metal dielectric layer 21 is deposited in the semicircular groove, and the metal dielectric layer 21 is in direct contact with the source 2. A semicircular groove is etched on the surface of the N-well layer 5 and a metal dielectric layer 21 is deposited so as to make it in direct contact with the source 2.

[0044] The semicircular groove structure increases the source contact area, the metal dielectric layer reduces the contact resistance, significantly improves the source carrier injection efficiency, and enhances the device's ability to withstand current shocks.

[0045] Example 3

[0046] like Figure 3 As shown, a plurality of blocking spacer bubbles 12 are formed inside a single MOS cell and on the left and right sides of the N-drift layer 8 through ion implantation. The blocking spacer bubbles 12 are arranged in a right triangle, with the hypotenuse of the right triangle arrangement close to the N+ layer 9. The blocking spacer bubbles 12 are implanted in a right triangle arrangement on both sides of the N-drift layer 8, with the hypotenuse facing the trench N+ layer 9.

[0047] The geometric arrangement of the ion bubbles forms a directional electric field barrier, effectively suppressing leakage current and optimizing the voltage resistance characteristics; the beveled edge design accurately blocks the electric field at the edge of the drift region, improving the breakdown voltage stability.

[0048] Example 4

[0049] like Figure 4 As shown, the filling dielectric is a central P-layer 14, and the contact layer is an N-type contact layer 13. The trench filling dielectric is replaced with the central P-layer 14, and the contact layers on both sides of the N substrate 7 are changed to N-type contact layers 13.

[0050] The P-layer filling realizes carrier concentration gradient control and forms a bidirectional carrier acceleration channel combined with the N-type contact layer, which significantly reduces switching losses and is suitable for high-frequency application scenarios.

[0051] Example 5

[0052] like Figure 5 As shown, a doped P-layer 15 is formed at the inner bottom of the central N-layer 10 by ion implantation. The doped P-layer 15 is implanted at the bottom of the central N-layer 10 to form a local PN junction structure.

[0053] The charge compensation effect introduced by the P-layer optimizes the electric field distribution at the bottom of the trench, alleviates the peak electric field problem, improves the long-term reliability and avalanche withstand capability of the device, while maintaining low on-resistance characteristics.

[0054] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A silicon carbide trench MOSFET device structure based on a heterojunction, comprising a plurality of mutually parallel MOS cells, wherein each of the MOS cells comprises a drain (1), a source (2), a gate (3) and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer comprises an N substrate layer (7), an N drift layer (8), a P+ layer (4), an N well layer (5) and a P well layer (6), characterized in that: A groove is provided on the upper surface of a single MOS cell and below the gate (3), an N+ layer (9) is deposited inside the groove, the N+ layer (9) comprising a left N+ layer (91) and a right N+ layer (92), and a filling medium is formed between the left N+ layer (91) and the right N+ layer (92) by ion implantation; The cross-sectional profile of the N substrate layer (7) inside a single MOS cell is in a shape with high convexities on both sides and a low concave in the middle. A contact layer is provided on both sides of the N substrate layer (7) in the single MOS cell, and the contact layer is in ohmic contact with the drain (1); The filling medium is a central P-layer (14), and the contact layer is an N-type contact layer (13).

2. A silicon carbide trench MOSFET device structure based on a heterojunction, comprising a plurality of mutually parallel MOS cells, wherein each of the MOS cells comprises a drain (1), a source (2), a gate (3) and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer comprises an N substrate layer (7), an N drift layer (8), a P+ layer (4), an N well layer (5) and a P well layer (6), characterized in that: A groove is provided on the upper surface of a single MOS cell and below the gate (3), an N+ layer (9) is deposited inside the groove, the N+ layer (9) comprising a left N+ layer (91) and a right N+ layer (92), and a filling medium is formed between the left N+ layer (91) and the right N+ layer (92) by ion implantation; The cross-sectional profile of the N substrate layer (7) inside a single MOS cell is in a shape with high convexities on both sides and a low concave in the middle. A contact layer is provided on both sides of the N substrate layer (7) in the single MOS cell, and the contact layer is in ohmic contact with the drain (1); The filling medium is a central N-layer (10), and the contact layer is a P-type contact layer (11); A doped P-layer (15) is formed at the inner bottom of the central N-layer (10) by ion implantation.

3. The heterojunction-based silicon carbide trench MOSFET device structure according to claim 2, characterized in that: A semicircular groove is formed on the surface of the N-well layer (5) by etching, a metal dielectric layer (21) is deposited in the semicircular groove, and the metal dielectric layer (21) is in direct contact with the source electrode (2).

4. The heterojunction-based silicon carbide trench MOSFET device structure according to claim 2, wherein: A plurality of barrier spacer bubbles (12) are formed inside a single MOS cell and on the left and right sides of the N drift layer (8) by ion implantation. The plurality of barrier spacer bubbles (12) are arranged in a right triangle, and the hypotenuse of the right triangle arrangement is close to the N+ layer (9).

5. A process for preparing a heterojunction-based silicon carbide trench MOSFET device structure, characterized in that: Applied to the heterojunction-based silicon carbide trench MOSFET device structure according to any one of claims 2 to 4, the preparation process of the heterojunction-based silicon carbide trench MOSFET device structure comprises the following specific steps: S1. Growing an N drift layer (8) on an N substrate layer (7), and sequentially forming a P+ layer (4), an N well layer (5), and a P well layer (6) by ion implantation; S2, groove etching is performed on the upper surface of the cell, and an N+ layer (9) is deposited on the inner wall of the groove, which is separated into a left N+ layer (91) and a right N+ layer (92) by mask technology; S3, forming a central N-layer (10) between the left and right N+ layers (9) by ion implantation, and implanting a doped P-layer (15) at the bottom of the central N-layer (10); S4, injecting into the high convex areas on both sides of the N substrate layer (7) to form a P-type contact layer (11), forming an ohmic contact with the drain (1); S5, etching a semicircular groove on the surface of the N-well layer (5), depositing a metal dielectric layer (21) and directly contacting the source electrode (2); S6. A gate oxide layer is grown above the trench, polysilicon is deposited to form a gate (3), a drain (1) is prepared on the back of the device, a source (2) is prepared on the front and connected to a metal dielectric layer (21).

6. The process for preparing a heterojunction-based silicon carbide trench MOSFET device structure according to claim 5, characterized in that: In step S4, barrier spacer bubbles (12) arranged in a right-angled triangle can be injected into the left and right sides of the N drift layer (8), with the hypotenuse facing the N+ layer (9).

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