JFET device

Abstract

The invention discloses a JFET device, and the device comprises a substrate which is provided with a first doped region in a region from the upper surface of the substrate to a preset depth; the epitaxial layer is formed on the substrate, a first polycrystalline silicon layer and a second polycrystalline silicon layer are formed on the epitaxial layer, a first STI structure, a second STI structure and a third STI structure are formed in the epitaxial layer, the first STI structure, the second STI structure and the third STI structure are annular from an overlook view, the second STI structure is located in an area surrounded by the third STI structure, and the third STI structure is located in an area surrounded by the third STI structure. The first STI structure is located in an area surrounded by the second STI structure; a first heavily doped region is formed in the epitaxial layer in a region surrounded by the first STI structure, the first heavily doped region is in contact with the bottoms of the first polycrystalline silicon layer and the second polycrystalline silicon layer respectively, second heavily doped regions are formed in the epitaxial layer on the outer two sides of the first STI structure, third heavily doped regions are formed in the epitaxial layer on the outer two sides of the second STI structure, and the third heavily doped regions are in contact with the bottoms of the first polycrystalline silicon layer and the second polycrystalline silicon layer respectively. And fourth heavily doped regions are formed in the epitaxial layer on the outer two sides of the third STI structure.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor devices and integrated circuits, and particularly to a JFET device. Background Art

[0002] A junction field-effect transistor (JFET) device is a semiconductor device that uses a PN junction (positive negative junction) as the gate of the device to control the conduction and cutoff of the channel. When the device is operating, a negative bias voltage is applied to the gate of the device, and both sides of the PN junction are depleted. When the channel is completely depleted, the device is in the channel pinch-off state and the device is cutoff; otherwise, the device is conducting.

[0003] Reference Figure 1 , which shows a cross-sectional view of a JFET device provided in the related art. Exemplarily, as Figure 1 shown, a buried layer doping region 111 is formed in a substrate 110, an epitaxial layer 120 is formed on the substrate 110, a first shallow trench isolation (STI) structure 131 and a second STI structure 132 that are annular when viewed from above are formed in the epitaxial layer 120, the first STI structure 131 is located in a region surrounded by the second STI structure 132, a first gate 141 and a second gate 142 are formed on the epitaxial layer 120, a first sidewall 1411 is formed on the peripheral side of the first gate 141, a second sidewall 1421 is formed on the peripheral side of the second gate 142, a first heavily doped region 1241 is formed in the epitaxial layer 120 between the first gate 141 and the second gate 142, second heavily doped regions 1251, 1252 are formed in the epitaxial layer 120 outside the first gate 141 and the second gate 142, third heavily doped regions 1242, 1243 are formed in the epitaxial layer 120 outside the first STI structure 131, the second heavily doped regions 1251, 1252 are formed in first well regions 1231, 1232, the first heavily doped region 1421, the second heavily doped regions 1251, 1252, and the well regions 1231, 1232 are formed in a deep well (DW) region 121, and the third heavily doped regions 1242, 1243 are formed in second well regions 1233, 1234.

[0004] When Figure 1When the shown JFET device operates, the first gate 141 and the second gate 142 are electrically connected through the first heavily doped region 1241. A gate voltage is applied, and the second heavily doped regions 1251 and 1252 serve as the source and drain of the device. It is not difficult to see that the JFET device provided in the related art is non-isolated, and the substrate 110 interferes with the device; at the same time, the substrate 110 is at the same potential as the first heavily doped region 1241, the first gate 141, and the second gate 142, and the overall potential is biased. Summary of the Invention

[0005] The present application provides a JFET device, which can solve the problem of poor electrical performance of the JFET device provided in the related art. The device includes:

[0006] A substrate, in which a first doped region is formed in a region from the upper surface of the substrate to a predetermined depth;

[0007] An epitaxial layer, which is formed on the substrate. A first polysilicon layer and a second polysilicon layer are formed on the epitaxial layer. A first STI structure, a second STI structure, and a third STI structure are formed in the epitaxial layer. From a top view, the first STI structure, the second STI structure, and the third STI structure are annular. The second STI structure is located in the region surrounded by the third STI structure, and the first STI structure is located in the region surrounded by the second STI structure;

[0008] A first heavily doped region is formed in the epitaxial layer in the region surrounded by the first STI structure. The first heavily doped region is in contact with the bottoms of the first polysilicon layer and the second polysilicon layer respectively. Second heavily doped regions are formed in the epitaxial layer on the outer two sides of the first STI structure. Third heavily doped regions are formed in the epitaxial layer on the outer two sides of the second STI structure. Fourth heavily doped regions are formed in the epitaxial layer on the outer two sides of the third STI structure;

[0009] The impurities doped in the first heavily doped region and the third heavily doped region have the same conductivity type. The impurities doped in the second heavily doped region and the fourth heavily doped region have the same conductivity type. The impurities doped in the first heavily doped region and the second heavily doped region have different conductivity types. The impurities doped in the first doped region and the first heavily doped region have different conductivity types.

[0010] In some embodiments, a second doped region is formed in the region surrounded by the third STI structure in the epitaxial layer. A third doped region is formed in the region surrounded by the second STI structure in the epitaxial layer. The depth of the third doped region is less than the depth of the second doped region. The impurities doped in the second doped region and the third doped region have different conductivity types. The impurities doped in the second doped region and the first heavily doped region have the same conductivity type.

[0011] In some embodiments, the third heavily doped region is formed in the second doped region, and the second heavily doped region is formed in the third doped region.

[0012] In some embodiments, a fourth doped region is further formed in the third doped region, the second heavily doped region is formed in the fourth doped region, and the conductivity types of the impurities doped in the fourth doped region and the first heavily doped region are different.

[0013] In some embodiments, a fifth doped region is further formed in the epitaxial layer, the fifth doped region is located outside the second doped region, and the conductivity types of the impurities doped in the fifth doped region and the first heavily doped region are different.

[0014] In some embodiments, the fourth heavily doped region is formed in the fifth doped region.

[0015] In some embodiments, when the JFET device operates, the first polysilicon layer, the second polysilicon layer and the first heavily doped region are electrically connected to form the top gate of the device, the two third heavily doped regions are electrically connected to form the back gate of the device, and the two second heavily doped regions are the source and the drain respectively.

[0016] The technical solution of the present application has at least the following advantages:

[0017] By forming the first doped region as a buried layer doped region between the substrate and the epitaxial layer, by forming the first heavily doped region connecting the first polysilicon layer and the second polysilicon layer in the epitaxial layer as the top gate, forming the second heavily doped region in the epitaxial layer as the source and the drain, and forming the third heavily doped region in the epitaxial layer as the back gate, the threshold voltage of the device is controlled by a double gate, the influence of the substrate on the electrical performance is reduced, and the electrical performance of the device is improved. Description of the Drawings

[0018] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 is a cross-sectional view of a JFET device provided in the related art;

[0020] Figure 2 is a cross-sectional view of a JFET device provided in an exemplary embodiment of the present application. Detailed Embodiments

[0021] The technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without making creative efforts shall fall within the scope of protection of the present application.

[0022] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and should not be construed as indicating or implying relative importance.

[0023] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" should be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may also be the internal communication of two elements. It may be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0024] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0025] Reference Figure 2 , which shows a cross-sectional view of a JFET device provided by an exemplary embodiment of the present application. As Figure 2 shown, the device includes:

[0026] A substrate 210, in which a first doped region 211 is formed in a region from its upper surface to a predetermined depth.

[0027] An epitaxial layer 220 is formed on a substrate 210, on which a first polysilicon layer 241 and a second polysilicon layer 242 are formed. A first STI structure 231, a second STI structure 232, and a third STI structure 233 are formed therein. When observed from a top view, the first STI structure 231, the second STI structure 232, and the third STI structure 233 are annular (which may be an elliptical ring, a circular ring, a rectangular ring, a bullet-shaped ring, etc.) and do not contact each other. The second STI structure 232 is located in the area surrounded by the third STI structure 233, and the first STI structure 231 is located in the area surrounded by the second STI structure 232.

[0028] A first heavily doped region 2241 is formed in the epitaxial layer 220 in the area surrounded by the first STI structure 231. The first heavily doped region 2241 is in contact with the bottoms of the first polysilicon layer 241 and the second polysilicon layer 242 respectively. Second heavily doped regions 2251 and 2252 are formed in the epitaxial layer 220 on the outer two sides of the first STI structure 231. Third heavily doped regions 2242 and 2243 are formed in the epitaxial layer 220 on the outer two sides of the second STI structure 232. Fourth heavily doped regions 2253 and 2254 are formed in the epitaxial layer 220 on the outer two sides of the third STI structure 233.

[0029] A second doped region 221 is formed in the area surrounded by the third STI structure 233 in the epitaxial layer 220. A third doped region 222 is formed in the area surrounded by the second STI structure 232 in the epitaxial layer 220. The depth of the third doped region 222 is less than the depth of the second doped region 221. The third heavily doped regions 2242 and 2243 are formed in the second doped region 221, and the second heavily doped regions 2251 and 2252 are formed in the third doped region 222.

[0030] Fourth doped regions 2231 and 2232 are also formed in the third doped region 222, and the second heavily doped regions are formed in the fourth doped regions (the second heavily doped region 2251 is formed in the fourth doped region 2231, and the second heavily doped region 2252 is formed in the fourth doped region 2232); fifth doped regions 2233 and 2234 are also formed in the epitaxial layer 220. The fifth doped regions 2233 and 2234 are located outside the second doped region 221 and do not contact the second doped region 221. The fourth heavily doped regions are formed in the fifth doped regions (the fourth heavily doped region 2253 is formed in the fifth doped region 2233, and the fourth heavily doped region 2254 is formed in the fifth doped region 2234).

[0031] Among them, the substrate 210, the second doping region 211, the first heavily doped region 2241, and the third heavily doped regions 2242 and 2243 are doped with impurities of the same conductivity type. The first doping region 211, the third doping region 222, the second heavily doped regions 2251 and 2252, the fourth doping regions 2231 and 2232, the fourth heavily doped regions 2253 and 2254, and the fifth doping regions 2233 and 2234 are doped with impurities of the same conductivity type. The concentrations of the impurities doped in the first heavily doped region 2241, the second heavily doped regions 2251 and 2252, the third heavily doped regions 2242 and 2243, and the fourth heavily doped regions 2253 and 2254 are greater than those in other doping regions.

[0032] If the impurities doped in the substrate 210, the second doping region 211, the first heavily doped region 2241, and the third heavily doped regions 2242 and 2243 are P (positive) - type impurities, then the impurities doped in the first doping region 211, the third doping region 222, the second heavily doped regions 2251 and 2252, the fourth doping regions 2231 and 2232, the fourth heavily doped regions 2253 and 2254, and the fifth doping regions 2233 and 2234 are N (negative) - type impurities; if the impurities doped in the substrate 210, the second doping region 211, the first heavily doped region 2241, and the third heavily doped regions 2242 and 2243 are N - type impurities, then the impurities doped in the first doping region 211, the third doping region 222, the second heavily doped regions 2251 and 2252, the fourth doping regions 2231 and 2232, the fourth heavily doped regions 2253 and 2254, and the fifth doping regions 2233 and 2234 are P - type impurities.

[0033] When the JFET device operates, the first polysilicon layer 241, the second polysilicon layer 242, and the first heavily doped region 2241 are electrically connected to form the top gate of the device, the two third heavily doped regions 2242 and 2243 are electrically connected to form the back gate of the device, and the two second heavily doped regions 2251 and 2252 are the source and drain respectively; the first doping region 211 is a buried - layer doping region, the second doping region 221 is an under - doping region, the third doping region 222 is a drift region, and the fourth doping regions 2231 and 2232 and the fifth doping regions 2233 and 2234 are well regions.

[0034] In summary, in the embodiments of the present application, by forming a first doped region as a buried doped region between the substrate and the epitaxial layer, forming a first heavily doped region connecting the first polysilicon layer and the second polysilicon layer as the top gate in the epitaxial layer, forming a second heavily doped region as the source and drain in the epitaxial layer, and forming a third heavily doped region as the back gate in the epitaxial layer, the threshold voltage of the device is controlled by a double gate, the influence of the substrate on the electrical performance is reduced, and the electrical performance of the device is improved.

[0035] Obviously, the above embodiments are merely examples for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. The obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims

1. A JFET device, characterized in that, Including: A substrate, in which a first doped region is formed in a region from the upper surface of the substrate to a predetermined depth; An epitaxial layer, which is formed on the substrate. A first polysilicon layer and a second polysilicon layer are formed on the epitaxial layer. A first STI structure, a second STI structure and a third STI structure are formed in the epitaxial layer. From a top view perspective, the first STI structure, the second STI structure and the third STI structure are annular. The second STI structure is located in the region surrounded by the third STI structure, and the first STI structure is located in the region surrounded by the second STI structure; A first heavily doped region is formed in the epitaxial layer in the region surrounded by the first STI structure. The first heavily doped region is in contact with the bottoms of the first polysilicon layer and the second polysilicon layer respectively. A second heavily doped region is formed in the epitaxial layer on the outer two sides of the first STI structure. A third heavily doped region is formed in the epitaxial layer on the outer two sides of the second STI structure. A fourth heavily doped region is formed in the epitaxial layer on the outer two sides of the third STI structure; The conductivity types of the impurities doped in the first heavily doped region and the third heavily doped region are the same. The conductivity types of the impurities doped in the second heavily doped region and the fourth heavily doped region are the same. The conductivity types of the impurities doped in the first heavily doped region and the second heavily doped region are different. The conductivity types of the impurities doped in the first doped region and the first heavily doped region are different.

2. The device according to claim 1, characterized in that A second doped region is formed in the region surrounded by the third STI structure in the epitaxial layer. A third doped region is formed in the region surrounded by the second STI structure in the epitaxial layer. The depth of the third doped region is less than the depth of the second doped region. The conductivity types of the impurities doped in the second doped region and the third doped region are different. The conductivity types of the impurities doped in the second doped region and the first heavily doped region are the same.

3. The device according to claim 2, characterized in that, The third heavily doped region is formed in the second doped region. The second heavily doped region is formed in the third doped region.

4. The device according to claim 3, characterized in that A fourth doped region is further formed in the third doped region. The second heavily doped region is formed in the fourth doped region. The conductivity types of the impurities doped in the fourth doped region and the first heavily doped region are different.

5. The device according to claim 4, wherein A fifth doped region is further formed in the epitaxial layer. The fifth doped region is located outside the second doped region. The conductivity types of the impurities doped in the fifth doped region and the first heavily doped region are different.

6. The device according to claim 5, characterized in that, The fourth heavily doped region is formed in the fifth doped region.

7. The device according to any one of claims 1 to 6, characterized in that, When the JFET device operates, the first polysilicon layer, the second polysilicon layer and the first heavily doped region are electrically connected to form the top gate of the device. The two third heavily doped regions are electrically connected to form the back gate of the device. The two second heavily doped regions are respectively the source and the drain.

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