Semiconductor transistor structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor transistor structure and a manufacturing method thereof, and the semiconductor transistor structure comprises a semiconductor substrate which is provided with an active region and a trench isolation region surrounding the active region; a first interlayer dielectric (ILD) layer covering the semiconductor substrate; the metal gate is embedded in the first ILD layer and covers the active region and the trench isolation region, the metal gate comprises a first part arranged right above the active region and a second part arranged right above the trench isolation region, and the first part is thicker than the second part; a hard mask layer disposed on the second portion; and a gate dielectric layer disposed between the first portion of the metal gate and the active region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to an improved semiconductor transistor structure and a manufacturing method thereof. Background Art

[0002] The height of a metal gate (MG) composed of a complex work function metal (WFM) thin film is crucial for the device and yield performance of fin field-effect transistor (FinFET) technology. The parasitic capacitance between the metal gate and adjacent conductors increases as the height of the metal gate increases, and there is a disproportionate relationship between the channel resistance and the height of the metal gate. Therefore, there is a need in this technical field for a structure and a manufacturing method that can improve the height uniformity of the metal gate. Summary of the Invention

[0003] The main objective of the present invention is to provide an improved semiconductor transistor structure and a manufacturing method thereof to solve the deficiencies or drawbacks of the prior art.

[0004] On the one hand, the present invention provides a semiconductor transistor structure, comprising: a semiconductor substrate having an active region and a trench isolation region surrounding the active region; a first interlayer dielectric (ILD) layer covering the semiconductor substrate; a metal gate embedded in the first ILD layer and covering the active region and the trench isolation region, wherein the metal gate includes a first portion disposed directly above the active region and a second portion disposed directly above the trench isolation region, and wherein the first portion is thicker than the second portion; a hard mask layer disposed on the second portion; and a gate dielectric layer disposed between the first portion of the metal gate and the active region.

[0005] According to an embodiment of the present invention, the hard mask layer comprises a silicon nitride layer.

[0006] According to an embodiment of the present invention, the metal gate comprises a metal filling layer and a work function metal layer.

[0007] According to an embodiment of the present invention, the metal filling layer comprises a tungsten metal layer.

[0008] According to an embodiment of the present invention, the hard mask layer is in direct contact with the metal filling layer.

[0009] According to an embodiment of the present invention, the top surface of the hard mask layer is coplanar with the top surface of the first portion of the metal gate.

[0010] According to an embodiment of the present invention, the semiconductor transistor structure further comprises: a source doping region disposed on a first side of the metal gate; and a drain doping region disposed on a second side opposite to the metal gate.

[0011] According to an embodiment of the present invention, the semiconductor transistor structure further includes: a second interlayer dielectric (ILD) layer covering the first ILD layer, the hard mask layer, and the metal gate; and a contact plug embedded in the second ILD layer and extending into the hard mask layer to make electrical contact with the second portion of the metal gate.

[0012] According to an embodiment of the present invention, the contact plug includes tungsten.

[0013] According to an embodiment of the present invention, the width of the second portion of the metal gate is greater than or equal to 0.07 micrometers.

[0014] On the other hand, a method for forming a semiconductor transistor structure according to the present invention includes: providing a semiconductor substrate having an active region and a trench isolation region surrounding the active region; forming a first interlayer dielectric (ILD) layer covering the semiconductor substrate; forming a metal gate embedded in the first ILD layer and covering the active region and the trench isolation region, wherein the metal gate includes a first portion disposed directly above the active region and a second portion disposed directly above the trench isolation region, and wherein the first portion is thicker than the second portion; forming a hard mask layer on the second portion; and forming a gate dielectric layer between the first portion of the metal gate and the active region.

[0015] According to an embodiment of the present invention, the hard mask layer includes a silicon nitride layer.

[0016] According to an embodiment of the present invention, the metal gate includes a metal fill layer and a work function metal (WFM) layer.

[0017] According to an embodiment of the present invention, the metal fill layer includes a tungsten metal layer.

[0018] According to an embodiment of the present invention, the hard mask layer is in direct contact with the metal fill layer.

[0019] According to an embodiment of the present invention, the top surface of the hard mask layer is coplanar with the top surface of the first portion of the metal gate.

[0020] According to an embodiment of the present invention, the method further includes: forming a source doping region on a first side of the metal gate; and forming a drain doping region on a second side opposite to the first side of the metal gate.

[0021] According to an embodiment of the present invention, the method further includes: forming a second interlayer dielectric (ILD) layer covering the first ILD layer, the hard mask layer, and the metal gate; and forming a contact plug embedded in the second ILD layer and extending into the hard mask layer to make electrical contact with the second portion of the metal gate.

[0022] According to an embodiment of the present invention, the contact plug includes tungsten.

[0023] According to an embodiment of the present invention, the width of the second part of the metal gate is greater than or equal to 0.07 micrometers. Brief Description of the Drawings

[0024] Figure 1 FIG. 1 is a top view of a semiconductor transistor structure illustrated in an embodiment of the present invention;

[0025] Figure 2 FIG. 2 is a schematic cross-sectional view taken along the tangent line I-I' in Figure 1 FIG. 1;

[0026] Figure 3 FIG. 3 is a schematic cross-sectional view taken along the tangent line II-II' in Figure 1 FIG. 1;

[0027] Figure 4 FIG. 4 is a top view of a semiconductor transistor structure illustrated in another embodiment of the present invention;

[0028] Figure 5 FIG. 5 is a schematic cross-sectional view taken along the tangent line III-III' in Figure 4 FIG. 4;

[0029] Figures 6 to 10 FIG. 6 is a schematic diagram of a method for forming a semiconductor transistor structure illustrated in an embodiment of the present invention.

[0030] Symbol Description

[0031] 1, 2 Semiconductor transistor structures

[0032] 100 Semiconductor substrate

[0033] 101 Active region

[0034] 102 Trench isolation region

[0035] 104 Source doping region

[0036] 106 Drain doping region

[0037] 108 Protection seal ring region

[0038] 120 Self-aligned contact (SAC) hard mask layer

[0039] 210 First interlayer dielectric (ILD) layer

[0040] 220 Second interlayer dielectric (ILD) layer

[0041] CT Contact plug

[0042] D1 First direction

[0043] D2 Second direction

[0044] GOX gate dielectric layer

[0045] MG metal gate

[0046] MG-1 first part

[0047] MG-2 second part

[0048] ML metal fill layer

[0049] MW work function metal layer

[0050] PR photoresist pattern

[0051] PO opening

[0052] R recessed area

[0053] SP spacer wall

[0054] S1, S2 top surface

[0055] t1, t2 thickness

[0056] w width Detailed implementation manners

[0057] In the following, details will be described with reference to the accompanying drawings, the content of which also constitutes a part of the detailed description of the specification and is shown in a specific example manner for implementing the embodiment. The following embodiments have described sufficient details for those of ordinary skill in the art to implement accordingly.

[0058] Of course, other embodiments may also be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be regarded as a limitation. Instead, the embodiments included therein will be defined by the appended claims.

[0059] Please refer to Figures 1 to 3 , wherein Figure 1 is a top view of a semiconductor transistor structure shown according to an embodiment of the present invention, Figure 2 is a schematic cross-sectional view taken along the tangent line I-I' in Figure 1 , Figure 3 is a schematic cross-sectional view taken along the tangent line II-II' in Figure 1 . As shown in Figures 1 to 3As shown, the semiconductor transistor structure 1 includes a semiconductor substrate 100 having an active region 101 and a trench isolation region 102 surrounding the active region 101. According to an embodiment of the present invention, for example, the semiconductor transistor structure 1 can be a medium-voltage or high-voltage transistor element. According to an embodiment of the present invention, for example, the semiconductor substrate 100 can include a silicon substrate, but is not limited thereto. According to an embodiment of the present invention, for example, the active region 101 can be a strip-shaped region and extend along a first direction D1. According to an embodiment of the present invention, for example, the trench isolation region 102 can include a shallow trench isolation structure.

[0060] As Figure 2 shown, the semiconductor transistor structure 1 further includes a first interlayer dielectric (ILD) layer 210 covering the semiconductor substrate 100. According to an embodiment of the present invention, for example, the first ILD layer 210 can include silicon oxide, but is not limited thereto.

[0061] As Figures 1 to 3 shown, the semiconductor transistor structure 1 further includes a metal gate MG embedded in the first ILD layer 210 and covering a part of the active region 101 and a part of the trench isolation region 102. The metal gate MG can be formed in the first ILD layer 210 by a replacement metal gate (RMG) manufacturing process. According to an embodiment of the present invention, for example, the metal gate MG can be strip-shaped and extend along a second direction D2, straddling the active region 101 such that both ends of the metal gate MG are directly above the trench isolation region 102. According to an embodiment of the present invention, the metal gate MG includes a metal filling layer ML and a work function metal layer MW. According to an embodiment of the present invention, for example, the metal filling layer ML includes a tungsten metal layer, but is not limited thereto.

[0062] Those skilled in the art should understand that the metal gate MG can also include a barrier layer, a high-k material layer, etc. For simplicity of illustration, these detailed structures are not shown in the figures. As Figure 2 shown, the semiconductor transistor structure 1 can include spacer walls SP between the first ILD layer 210 and the metal gate MG.

[0063] According to an embodiment of the present invention, the metal gate MG includes a first part MG-1 disposed directly above the active region 101 and a second part MG-2 disposed directly above the trench isolation region 102. The first part MG-1 is directly connected to the second part MG-2. As Figure 3As shown, according to an embodiment of the present invention, the first part MG-1 is thicker than the second part MG-2. According to an embodiment of the present invention, for example, the ratio t2 / t1 of the thickness t1 of the second part MG-2 to the thickness t1 of the first part MG-1 can be between 0.25 and 0.75. According to an embodiment of the present invention, for example, the thickness t1 of the first part MG-1 can be between 250 and 600 angstroms, while the thickness t1 of the second part MG-2 can be between 100 and 450 angstroms. As Figure 1 shown, according to an embodiment of the present invention, the width w of the second part MG-2 of the metal gate MG in the second direction D2 is greater than or equal to 0.07 micrometers.

[0064] As Figure 1 and Figure 3 shown, the semiconductor transistor structure 1 further includes a self-aligned contact (SAC) hard mask layer 120 disposed directly above the second part MG-2. According to an embodiment of the present invention, the SAC hard mask layer 120 directly contacts the second part MG-2. According to an embodiment of the present invention, the SAC hard mask layer 120 directly contacts the metal fill layer ML. According to an embodiment of the present invention, the top surface S1 of the SAC hard mask layer 120 is coplanar with the top surface S2 of the first part MG-1 of the metal gate MG. According to an embodiment of the present invention, for example, the SAC hard mask layer 120 may include a silicon nitride layer, but is not limited thereto.

[0065] As Figure 2 and Figure 3 shown, the semiconductor transistor structure 1 further includes a gate dielectric layer GOX disposed between the first part MG-1 of the metal gate MG and the active region 101. According to an embodiment of the present invention, for example, the gate dielectric layer GOX may include silicon oxide, but is not limited thereto.

[0066] As Figure 1 and Figure 2 shown, according to an embodiment of the present invention, the semiconductor transistor structure 1 further includes a source doping region 104 disposed in the active region 101 on the first side of the metal gate MG, and a drain doping region 106 disposed in the active region 101 on the opposite second side of the metal gate MG. Those skilled in the art should understand that dopants can be implanted into the source doping region 104 and the drain doping region 106, and an epitaxial layer can also be formed additionally.

[0067] As Figure 2 and Figure 3 shown, according to an embodiment of the present invention, the semiconductor transistor structure 1 further includes a second interlayer dielectric (ILD) layer 220 covering the first ILD layer 210, the SAC hard mask layer 120, and the metal gate MG. According to an embodiment of the present invention, for example, the second ILD layer 220 may be a low dielectric constant material layer or an ultra-low dielectric constant material layer.

[0068] As shown Figure 3 in FIG. 1, according to an embodiment of the present invention, the semiconductor transistor structure 1 further includes a contact plug CT, which is embedded in the second ILD layer 220 and extends into the SAC hard mask layer 120 to make electrical contact with the second part MG-1 of the metal gate MG. According to an embodiment of the present invention, the contact plug CT may include tungsten, but is not limited thereto.

[0069] Please refer to Figures 4 to 5 FIG. 2, Figure 4 which is a top view of a semiconductor transistor structure illustrated according to another embodiment of the present invention. Figure 5 FIG. 3 Figure 4 is a cross-sectional schematic view taken along the tangent line III-III' in FIG. 2, where the same layers, materials, or elements are still denoted by the same reference numerals. As shown Figure 4 in FIGS. 2 Figure 5 and 3, the semiconductor transistor structure 2 includes a semiconductor substrate 100, which has an active region 101 and a trench isolation region 102 surrounding the active region 101. According to an embodiment of the present invention, for example, the semiconductor transistor structure 2 may be a high-voltage transistor element or a high-voltage LDMOS element. According to an embodiment of the present invention, for example, the semiconductor substrate 100 may include a silicon substrate, but is not limited thereto. According to an embodiment of the present invention, for example, the active region 101 may be a long strip region and extend along the first direction D1. According to an embodiment of the present invention, for example, the trench isolation region 102 may include a shallow trench isolation structure.

[0070] As shown Figure 5 in FIG. 3, the semiconductor transistor structure 2 also includes a first ILD layer 210, which covers the semiconductor substrate 100. According to an embodiment of the present invention, for example, the first ILD layer 210 may include silicon oxide, but is not limited thereto.

[0071] As shown Figure 4 in FIGS. 2 Figure 5 and 3, the semiconductor transistor structure 2 also includes a metal gate MG, which is embedded in the first ILD layer 210 and covers a part of the active region 101 and a part of the trench isolation region 102. The metal gate MG may be formed in the first ILD layer 210 by using a replacement metal gate (RMG) manufacturing process. According to an embodiment of the present invention, for example, the metal gate MG may be a long strip and extend along the second direction D2, straddling the active region 101, such that both ends of the metal gate MG are located directly above the trench isolation region 102. According to an embodiment of the present invention, as shown Figure 5 in FIG. 3, the metal gate MG includes a metal filling layer ML and a work function metal layer MW. According to an embodiment of the present invention, for example, the metal filling layer ML includes a tungsten metal layer, but is not limited thereto.

[0072] Those skilled in the art should understand that the metal gate MG may also include a barrier layer, a high-k dielectric material layer, etc. For the sake of simplicity, these detailed structures are not shown in the figures.

[0073] According to an embodiment of the present invention, the metal gate MG includes a first portion MG-1 disposed directly above the active region 101 and a second portion MG-2 disposed directly above the trench isolation region 102. The first portion MG-1 is directly connected to the second portion MG-2. As Figure 5 shown, according to an embodiment of the present invention, the first portion MG-1 is thicker than the second portion MG-2. According to an embodiment of the present invention, for example, the ratio t2 / t1 of the thickness t2 of the second portion MG-2 to the thickness t1 of the first portion MG-1 may be between 0.25 and 0.75. According to an embodiment of the present invention, for example, the thickness t1 of the first portion MG-1 may be between 250 and 600 angstroms, and the thickness t2 of the second portion MG-2 may be between 100 and 450 angstroms. As Figure 4 shown, according to an embodiment of the present invention, the width w of the second portion MG-2 of the metal gate MG in the second direction D2 is greater than or equal to 0.07 micrometers.

[0074] As Figure 4 and Figure 5 shown, the semiconductor transistor structure 2 also includes an SAC hard mask layer 120 disposed directly above the second portion MG-2. According to an embodiment of the present invention, the SAC hard mask layer 120 is in direct contact with the second portion MG-2. According to an embodiment of the present invention, the SAC hard mask layer 120 is in direct contact with the metal fill layer ML. According to an embodiment of the present invention, the top surface S1 of the SAC hard mask layer 120 is coplanar with the top surface S2 of the first portion MG-1 of the metal gate MG. According to an embodiment of the present invention, for example, the SAC hard mask layer 120 may include a silicon nitride layer, but is not limited thereto.

[0075] As Figure 5 shown, the semiconductor transistor structure 2 also includes a gate dielectric layer GOX disposed between the first portion MG-1 of the metal gate MG and the active region 101. According to an embodiment of the present invention, for example, the gate dielectric layer GOX may include silicon oxide, but is not limited thereto.

[0076] As Figure 4As shown, according to an embodiment of the present invention, the semiconductor transistor structure 2 further includes a source doping region 104 disposed in the active region 101 on the first side of the metal gate MG, and a drain doping region 106 disposed in the active region 101 on the opposite second side of the metal gate MG. Those skilled in the art should understand that dopants can be implanted into the source doping region 104 and the drain doping region 106, and an epitaxial layer can also be formed additionally. According to an embodiment of the present invention, the active region 101, the source doping region 104, and the drain doping region 106 can be surrounded by a protection seal ring region 108.

[0077] As Figure 5 shown, according to an embodiment of the present invention, the semiconductor transistor structure 2 further includes a second interlayer dielectric (ILD) layer 220 covering the first ILD layer 210, the SAC hard mask layer 120, and the metal gate MG. According to an embodiment of the present invention, for example, the second ILD layer 220 can be a low dielectric constant material layer or an ultra-low dielectric constant material layer. According to an embodiment of the present invention, the semiconductor transistor structure 1 further includes a contact plug CT embedded in the second ILD layer 220 and extending into the SAC hard mask layer 120 to make electrical contact with the second part MG-1 of the metal gate MG. According to an embodiment of the present invention, the contact plug CT can include tungsten, but is not limited thereto.

[0078] Please refer to Figures 6 to 10 , which is a schematic diagram of a method for forming a semiconductor transistor structure according to an embodiment of the present invention. For simplicity of description, only the cross-section along the tangent line II-II' in Figure 1 is illustrated. As Figure 6 shown, first, a semiconductor substrate 100 is provided, having an active region 101 and a trench isolation region 102 surrounding the active region 101. According to an embodiment of the present invention, for example, the semiconductor substrate 100 can include a silicon substrate, but is not limited thereto. According to an embodiment of the present invention, for example, the trench isolation region 102 can include a shallow trench isolation structure. A first ILD layer 210 is formed on the semiconductor substrate 100. According to an embodiment of the present invention, for example, the first ILD layer 210 can include silicon oxide, but is not limited thereto.

[0079] Next, a replacement metal gate (RMG) fabrication process is performed to form a metal gate MG in the first interlayer dielectric (ILD) layer 210. The metal gate MG is embedded in the first ILD layer 210 and covers a part of the active region 101 and a part of the trench isolation region 102. According to an embodiment of the present invention, the metal gate MG straddles the active region 101 such that both ends of the metal gate MG are directly above the trench isolation region 102. According to an embodiment of the present invention, the metal gate MG includes a metal fill layer ML and a work function metal layer MW. According to an embodiment of the present invention, for example, the metal fill layer ML includes a tungsten metal layer, but is not limited thereto. A gate dielectric layer GOX is disposed between the first portion MG-1 of the metal gate MG and the active region 101. According to an embodiment of the present invention, for example, the gate dielectric layer GOX may include silicon oxide, but is not limited thereto.

[0080] According to an embodiment of the present invention, the metal gate MG includes a first portion MG-1 disposed directly above the active region 101 and a second portion MG-2 disposed directly above the trench isolation region 102. The first portion MG-1 is directly connected to the second portion MG-2.

[0081] As Figure 7 shown, a photolithography fabrication process is then performed to form a photoresist pattern PR on the first ILD layer 210 and the metal gate MG. The photoresist pattern PR includes an opening PO that exposes only the second portion MG-2 of the metal gate MG directly above the trench isolation region 102. According to an embodiment of the present invention, the width w of the opening PO is greater than or equal to 0.07 micrometers. An etching fabrication process is then performed to etch a partial thickness of the second portion MG-2 through the opening PO to form a recessed region R. At this time, the first portion MG-1 is thicker than the second portion MG-2. According to an embodiment of the present invention, for example, the ratio t2 / t1 of the thickness t2 of the second portion MG-2 to the thickness t1 of the first portion MG-1 may be between 0.25 and 0.75. According to an embodiment of the present invention, for example, the thickness t1 of the first portion MG-1 may be between 250 and 600 angstroms, and the thickness t2 of the second portion MG-2 may be between 100 and 450 angstroms.

[0082] As Figure 8 shown, a chemical vapor deposition (CVD) fabrication process is then performed to deposit a self-aligned contact (SAC) hard mask layer 120 over the entire semiconductor substrate 100 and to fill the recessed region R with the SAC hard mask layer 120. According to an embodiment of the present invention, for example, the SAC hard mask layer 120 may include a silicon nitride layer, but is not limited thereto.

[0083] As Figure 9As shown, a chemical mechanical polishing (CMP) process is then performed to remove the SAC hard mask layer 120 outside the recessed area R, leaving only the SAC hard mask layer 120 directly above the second part MG-2. According to an embodiment of the present invention, the SAC hard mask layer 120 is in direct contact with the second part MG-2. According to an embodiment of the present invention, the SAC hard mask layer 120 is in direct contact with the metal fill layer ML. According to an embodiment of the present invention, the top surface S1 of the SAC hard mask layer 120 is coplanar with the top surface S2 of the first part MG-1 of the metal gate MG. A chemical vapor deposition (CVD) process is then performed to deposit the second ILD layer 220 over the entire semiconductor substrate 100, such that the second ILD layer 220 covers the first ILD layer 210, the SAC hard mask layer 120, and the metal gate MG. According to an embodiment of the present invention, for example, the second ILD layer 220 may be a low-k dielectric material layer or an ultra-low-k dielectric material layer.

[0084] As Figure 10 shown, a contact plug CT is then formed, embedded in the second ILD layer 220 and extending into the SAC hard mask layer 120 to make electrical contact with the second part MG-1 of the metal gate MG. According to an embodiment of the present invention, the contact plug CT may include tungsten, but is not limited thereto.

[0085] In the present invention, since the SAC hard mask layer 120 of the medium-voltage or high-voltage transistor element is reduced to only directly above the second part MG-2 of the metal gate MG, it is possible to increase the margin of the SAC manufacturing process for a large gate area, avoid the over-etching problem of the work function metal layer during the SAC manufacturing process of the medium-voltage or high-voltage transistor element, and achieve the purpose of improving the height uniformity of the metal gate and enhancing the device performance.

[0086] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims

1. A semiconductor transistor structure, comprising: A semiconductor substrate having an active region and a trench isolation region surrounding the active region; A first interlayer dielectric layer covering the semiconductor substrate; A metal gate embedded in the first interlayer dielectric layer and covering the active region and the trench isolation region, wherein, The metal gate includes a first portion disposed directly above the active region and a second portion disposed directly above the trench isolation region, wherein the first portion is thicker than the second portion; A hard mask layer disposed on the second portion; And A gate dielectric layer disposed between the first portion of the metal gate and the active region.

2. The semiconductor transistor structure according to claim 1, wherein, The hard mask layer includes a silicon nitride layer.

3. The semiconductor transistor structure according to claim 1, wherein, The metal gate includes a metal fill layer and a work function metal layer.

4. The semiconductor transistor structure according to claim 3, wherein, The metal fill layer includes a tungsten metal layer.

5. The semiconductor transistor structure according to claim 3, wherein, The hard mask layer is in direct contact with the metal fill layer.

6. The semiconductor transistor structure according to claim 1, wherein, The top surface of the hard mask layer is coplanar with the top surface of the first portion of the metal gate.

7. The semiconductor transistor structure according to claim 1, wherein, Further comprising: A source doping region disposed on a first side of the metal gate; and A drain doping region disposed on a second opposite side of the metal gate.

8. The semiconductor transistor structure according to claim 1, wherein, Further comprising: A second interlayer dielectric layer covering the first interlayer dielectric layer, the hard mask layer, and the metal gate; and A contact plug embedded in the second interlayer dielectric layer and extending into the hard mask layer to make electrical contact with the second portion of the metal gate.

9. The semiconductor transistor structure according to claim 8, wherein, The contact plug includes tungsten.

10. The semiconductor transistor structure as described in claim 1, wherein, The width of the second portion of the metal gate is greater than or equal to 0.07 microns.

11. A method of forming a semiconductor transistor structure, comprising: Providing a semiconductor substrate having an active region and a trench isolation region surrounding the active region; Forming a first interlayer dielectric layer covering the semiconductor substrate; Forming a metal gate embedded in the first interlayer dielectric layer and covering the active region and the trench isolation region, wherein, The metal gate includes a first portion disposed directly above the active region and a second portion disposed directly above the trench isolation region, wherein the first portion is thicker than the second portion; Forming a hard mask layer on the second portion; And Forming a gate dielectric layer between the first portion of the metal gate and the active region.

12. The method according to claim 11, wherein, The hard mask layer includes a silicon nitride layer.

13. The method according to claim 11, wherein, The metal gate includes a metal fill layer and a work function metal layer.

14. The method according to claim 13, wherein, The metal fill layer includes a tungsten metal layer.

15. The method according to claim 13, wherein, The hard mask layer is in direct contact with the metal fill layer.

16. The method according to claim 11, wherein, The top surface of the hard mask layer is coplanar with the top surface of the first portion of the metal gate.

17. The method according to claim 11, wherein, Further comprising: Forming a source doping region on a first side of the metal gate; and Forming a drain doping region on a second opposite side of the metal gate.

18. The method according to claim 11, wherein Further comprising: Forming a second interlayer dielectric layer covering the first interlayer dielectric layer, the hard mask layer, and the metal gate; And Forming a contact plug embedded in the second interlayer dielectric layer and extending into the hard mask layer to make electrical contact with the second portion of the metal gate.

19. The method according to claim 18, wherein The contact plug includes tungsten.

20. The method according to claim 11, wherein, The width of the second portion of the metal gate is greater than or equal to 0.07 microns.

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