Crystalline semiconductor layer between bipolar transistor structure and field effect transistor structure

Abstract

Embodiments of the present disclosure provide a crystalline semiconductor layer between a bipolar transistor structure and a field effect transistor (FET) structure. The structure includes a dielectric layer on a back gate semiconductor layer, a bipolar transistor structure on the dielectric layer, an FET structure on the dielectric layer, and a crystalline semiconductor layer on the dielectric layer between the bipolar transistor structure and the FET structure. The crystalline semiconductor layer includes a terminal of the bipolar transistor structure and a terminal of the FET structure.

Description

Technical Field

[0001] The present disclosure provides a crystalline semiconductor layer located between a bipolar transistor structure and a field effect transistor structure. Background Art

[0002] Conventional integrated circuits may employ heterojunction bipolar transistors (HBTs). In the past, HBTs were vertically oriented. Lateral bipolar transistors are currently under development, at least in part to allow for easy integration into complementary metal oxide semiconductor (CMOS) process flows for semiconductor-on-insulator structures (e.g., silicon-on-insulator (SOI) structures). Effectively integrating a lateral bipolar transistor into the same device layer as a field effect transistor (FET) is a technical challenge. Summary of the Invention

[0003] Exemplary aspects of the present disclosure are designed to address the problems described herein and / or other problems not discussed.

[0004] Embodiments of the present disclosure provide a structure including: a dielectric layer on a back-gate semiconductor layer; a bipolar transistor structure on the dielectric layer; a field effect transistor (FET) structure on the dielectric layer; and a crystalline semiconductor layer on the dielectric layer, located between the bipolar transistor structure and the FET structure, wherein the crystalline semiconductor layer includes terminals of the bipolar transistor structure and terminals of the FET structure.

[0005] Additional embodiments of the present disclosure provide a structure including: a dielectric layer on a back-gate semiconductor layer; a crystalline semiconductor layer on the dielectric layer; a base structure located on the dielectric layer and adjacent to a first horizontal end of the crystalline semiconductor layer; and a gate structure located on the dielectric layer and adjacent to a second horizontal end of the crystalline semiconductor layer, wherein the crystalline semiconductor layer is horizontally located between the base structure and the gate structure.

[0006] Further additional embodiments of the present disclosure provide a structure including: a dielectric layer on a back-gate semiconductor layer; a contact to the dielectric layer; an emitter / collector (E / C) layer located on the dielectric layer and adjacent to a first horizontal end of the contact; a base structure located on the dielectric layer and adjacent to the E / C layer, wherein the E / C layer is horizontally located between the base structure and the contact; a source / drain (S / D) layer located on the dielectric layer and adjacent to a second horizontal end of the contact; and a gate structure located on the dielectric layer and adjacent to the S / D layer, wherein the S / D layer is horizontally located between the contact and the gate structure. Brief Description of the Drawings

[0007] The following detailed description of aspects of the present disclosure, made in conjunction with the accompanying drawings that illustrate various embodiments of the present disclosure, will more readily understand these and other features of the present disclosure, wherein:

[0008] Figure 1 A cross-sectional view of a crystalline semiconductor layer located between a bipolar transistor structure and a field effect transistor (FET) structure according to an embodiment of the present disclosure is shown.

[0009] Figure 2 A plan view of a structure according to an embodiment of the present disclosure is shown.

[0010] Figure 3 An example circuit diagram implemented by a structure according to an embodiment of the present disclosure is shown.

[0011] Figure 4 A cross-sectional view of a crystalline semiconductor layer located between a plurality of bipolar transistor structures and a plurality of FET structures according to an embodiment of the present disclosure is shown.

[0012] Figure 5 A plan view of a crystalline semiconductor layer located between a plurality of bipolar transistor structures and a plurality of FET structures according to an embodiment of the present disclosure is shown.

[0013] Figure 6 An example circuit diagram implemented by a structure according to another embodiment of the present disclosure is shown.

[0014] Figure 7 A cross-sectional view of a crystalline semiconductor layer and contacts located between a bipolar transistor structure and a field effect transistor (FET) structure according to another embodiment of the present disclosure is shown.

[0015] Figure 8 A plan view of a structure according to another embodiment of the present disclosure is shown.

[0016] Figure 9 An example circuit diagram implemented in a structure according to another embodiment of the present disclosure is shown.

[0017] Figure 10 A cross-sectional view of a crystalline semiconductor layer and contacts located between a plurality of bipolar transistor structures and a plurality of FET structures according to an embodiment of the present disclosure is shown.

[0018] Note that the accompanying drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended to depict only typical aspects of the present disclosure and should not be construed as limiting the scope of the present disclosure. In the drawings, like reference numerals denote like elements among the drawings. Detailed Description

[0019] In the following description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown, by way of illustration, specific exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings. It is to be understood that other embodiments may be used and changes may be made without departing from the scope of the present teachings. Accordingly, the following description is merely illustrative.

[0020] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or “above” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly above” another element, no intervening elements are present. It should also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, no intervening elements are present.

[0021] References in the specification to “one embodiment” or “an embodiment” and other variations thereof mean that a particular feature, structure, characteristic, etc. described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases “in one embodiment” or “in an embodiment” and any other variations that occur throughout the specification do not necessarily all refer to the same embodiment. It should be understood that in the case of using any of “ / ”, “and / or”, and “at least one of” such as in “A / B”, “A and / or B”, and “at least one of A and B” is intended to include only the first-listed option (a), or only the second-listed option (B), or both options (A and B) being selected. As other examples, in the case of “A, B, and / or C” and “at least one of A, B, and C”, these phrases are intended to include only the first-listed option (A), or only the second-listed option (B), or only the third-listed option (C), or only the first and second-listed options (A and B), or only the first and third-listed options (A and C), or only the second and third-listed options (B and C), or all three options (A and B and C) being selected. As will be apparent to those of ordinary skill in the art, this situation can be extended to many items listed.

[0022] Embodiments of the present disclosure provide a crystalline semiconductor layer located between a bipolar transistor structure and a field effect transistor (FET) structure. The structure includes a dielectric layer on a backgate semiconductor layer, a bipolar transistor structure on the dielectric layer, an FET structure on the dielectric layer, and a crystalline semiconductor layer on the dielectric layer between the bipolar transistor structure and the FET structure. The crystalline semiconductor layer includes terminals of the bipolar transistor structure and terminals of the FET structure. Compared with conventional device structures, the crystalline semiconductor layer can allow emitter / collector (E / C) terminals and source / drain (S / D) terminals to be defined in portions of the same active semiconductor material. In some cases, the various terminals can be defined in a continuous crystalline semiconductor layer. In other cases, the contacts can be located horizontally between the E / C terminals and the S / D terminals. The gate and base of the transistor can optionally be coupled together in another portion of the device layer. Both the bipolar transistor structure and the FET structure can be located above one or more backgate semiconductor materials and can be configured for simultaneous backgate biasing or independent backgate biasing in various embodiments.

[0023] A bipolar junction transistor (BJT) can take the form of a heterojunction bipolar transistor (HBT). A heterojunction bipolar transistor differs from other bipolar transistors in that it includes, for example, different types of semiconductor materials and different doping types. As discussed herein, the base of an HBT can be silicon germanium (SiGe), while the emitter and collector terminals can include crystalline silicon (Si). HBTs and other BJT structures operate using multiple "P-N" junctions. The term "P-N" refers to two adjacent materials having different conduction types (i.e., P-type and N-type), which can be induced by dopants within the adjacent materials. Doping generally refers to the process of adding an extrinsic material ("dopant") to a semiconductor structure to change its electrical properties (e.g., resistivity and / or conductivity). In cases where a specific doping type (e.g., p-type or n-type) is discussed herein, it should be understood that the opposite doping type can be implemented in alternative embodiments. Where applicable, implantation refers to a doping process in which ions are accelerated towards a solid surface to penetrate the solid to a predetermined range based on the energy of the implanted ions. Doping can also be achieved by epitaxially growing semiconductor materials of different conduction types in contact with each other (i.e., in-situ doping during epitaxy). In-situ doped epitaxy is particularly suitable for forming the HBT structures discussed herein.

[0024] When formed in a device, a P-N junction can operate as a diode. A diode is a two-terminal device that behaves differently from conductive or insulating materials between two electrical contact points. Specifically, a diode provides high conductivity from one contact to the other in one voltage bias direction (i.e., the "forward" direction), but provides little conductivity in the opposite direction (i.e., the "reverse" direction). In the case of a P-N junction, the forward and reverse orientations of the diode depend on the type and magnitude of the bias applied to the material composition of one or both terminals, thereby affecting the magnitude of the barrier. In the case of a junction between two semiconductor materials, the barrier will form along the interface between the two semiconductor materials.

[0025] Reference Figure 1 , Structure 100 according to an embodiment of the present disclosure is shown. Structure 100 may be located on a substrate 102, which includes, for example, one or more semiconductor materials. Substrate 102 may include, but is not limited to, silicon, germanium, silicon germanium (SiGe), silicon carbide (SiC), or any other common IC semiconductor substrate. In the case of SiGe, the germanium concentration in substrate 102 may be different from other SiGe-based structures described herein. A portion or all of substrate 102 may be strained and / or may be doped to any desired polarity or concentration. Additionally, some portions of substrate 102 may be doped to provide, for example, deep wells for other device structures on substrate 102 that are not explicitly shown or discussed herein.

[0026] Structure 100 may include embedded elements for electrically separating the active material formed above substrate 102 from other regions and / or materials. Some regions of substrate 102 may be doped to provide a back-gate semiconductor layer 104. The back-gate semiconductor layer 104 may specifically be a single-crystal semiconductor layer of P-type or N-type for conducting electricity and allowing electrical biasing. The back-gate semiconductor layer 104 may be a doped bulk semiconductor material, or in other examples, may be a single-crystal layer of crystalline silicon or any other suitable semiconductor material (e.g., silicon germanium). An insulator layer 106 may be located above substrate 102 and back-gate semiconductor layer 104. The insulator layer 106 may be, for example, an oxide layer (also referred to herein as a buried oxide (BOX) layer), such as a silicon dioxide layer, or any other suitable insulator material layer.

[0027] The structure 100 may further include one or more trench isolation layers (TI) 110. The TI 110 can be fabricated by forming a trench (not shown) and filling the trench with an insulating material such as an oxide. The TI 110 horizontally isolates the insulator layer 106, the back gate semiconductor layer 104, and other components thereon (e.g., the bipolar transistor structure and field effect transistor (FET) structure discussed herein) from any adjacent material regions. Each part of the structure 100, including its active semiconductor material and / or other devices (where applicable), can be formed on or above the portions of the insulator layer 106 isolated by the TI 110. Figure 1 One TI 100 is shown as an example, but multiple TIs 100 can be provided, as discussed elsewhere herein, to isolate the structure 100 from different types of structures and / or components. The active semiconductor layer 112 (e.g., a semiconductor-on-insulator (SOI) layer and / or other doped semiconductor material layer) located on the insulator 106 and separated from other structures by the TI 110 can define the active device regions for the bipolar junction transistor 120 and the field effect transistor 130 above the substrate 102. The TI 110 can be formed before the active semiconductor layer 112 is formed on the substrate 102, but this is not the case in all embodiments.

[0028] The insulator layer 106 and the TI 110 can be formed of any presently known or later developed material for providing electrical insulation and can include, by way of example: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, carbon (C)-doped oxide (i.e., organosilicate) (which includes atoms of silicon (Si), carbon (C), oxygen (O), and / or hydrogen (H)), thermosetting polyarylether, spin-on silicon-carbon-containing polymeric material, near-frictionless carbon (NFC), or layers thereof. The active semiconductor layer 112 can be located on the insulator layer 106, e.g., because it is formed by deposition and epitaxial growth of semiconductor material. In other cases (e.g., when not using an SOI stack), the active semiconductor layer 112 and the TI 110 can be planarized (e.g., by chemical mechanical planarization or other techniques) such that their upper surfaces are substantially coplanar with each other, such that the upper surface of the active semiconductor layer 112 is substantially coplanar with the TI 110.

[0029] The insulator layer 106 may extend horizontally through the structure 100 and / or may be a layer on which the active material is formed and / or defined. In additional embodiments, the insulator layer 106 may include oxygen doping to form a dielectric insulator or a buried oxide (“BOX”) layer over the substrate 102 and the back-gate semiconductor layer 104, thereby electrically isolating the overlying active material from the back-gate semiconductor layer 104 and / or the substrate 102. Thus, the insulator layer 106 may include other elements or molecules, such as Ge, N, or Si. However it is implemented, the insulator layer 106 may be as narrow as possible to provide better interaction with the overlying semiconductor material. In various embodiments, the insulator layer 106 may have a vertical thickness of about 2 nanometers (nm), but may also have various thicknesses, such as about 20 nm, about 500 nm, etc. Some portions (not shown) of the substrate 102 and / or the back-gate semiconductor layer 104 may not have the insulator layer 106 thereover, and / or multiple insulator layers 106 may be formed on the substrate 102 with different thicknesses. Additionally, various conductive particles (“dopants”) may be introduced into the substrate 102 through a process referred to herein as “pre-doping” of the substrate 102. It should be understood that the substrate 102 may be separately connected and used as a “back-bias” to modify the operation of some or all of the devices located above the insulator layer 106, even though such coupling is not explicitly shown in the figures for the sake of clarity of illustration.

[0030] Both the heterojunction bipolar transistor (HBT) structure 120 and the FET structure 130 can be formed over and within respective portions of the active semiconductor layer 112 delimited within the TI 110. An embodiment of the structure 100 integrally forms the BT structure 120 and the FET structure 130 structurally by disposing a crystalline semiconductor layer within the semiconductor layer 112. The formation of the structure 100 can include, for example, providing a fully depleted silicon-on-insulator (FDSOI) substrate that includes a thin insulating material layer between two semiconductor layers. Various isolation regions (i.e., the TI 110 discussed herein) are patterned to expose portions of the substrate initially located beneath the insulator layer. Various gate structures (e.g., dummy gates) can be formed on the upper semiconductor layer of the FDSOI substrate. A spacer 158 is then formed on the gate structures, and one or more of the gate structures can be removed and replaced with a base structure of the HBT or a functional transistor gate as discussed herein. The crystalline semiconductor layer 140 can be formed by epitaxial growth between the base and gate components of the BT structure 120 and the FET structure 130 and is thus shared therebetween. The crystalline semiconductor layer 140 can be doped, for example, by in-situ doping and / or doping during the formation of the semiconductor material over the insulator layer 106 and / or the back-gate semiconductor layer 104. According to one example, the crystalline semiconductor layer 140 can have the same doping polarity as the back-gate semiconductor layer 104, e.g., they can both have n-type doping. It should be understood that local implants and / or dopant diffusion from subsequent annealing steps can result in dopants of the same type as the crystalline semiconductor layer 140 also being located in portions of the back-gate semiconductor layer 104 beneath the crystalline semiconductor layer 140.

[0031] The crystalline semiconductor layer 140 can be subdivided into different regions, each region providing active semiconductor material for a terminal of the BT structure 120 and the FET structure 130, respectively. Specifically, the crystalline semiconductor layer 140 can include emitter / collector (E / C) terminals 142 and source / drain (S / D) terminals 144, which are defined by their relative proximity to the BT structure 120 and the FET structure 130. The crystalline semiconductor layer 140 itself can be structurally continuous and thus may not include material boundaries, interfaces, and / or other physical features for differentiating the terminals 142, 144. In the case where the BT structure 120 is located on the left side of the crystalline semiconductor layer 140 and the FET structure 130 is located on the right side of the crystalline semiconductor layer 140, the E / C terminal 142 can be the left half of the crystalline semiconductor layer 140, and the S / D terminal 144 can be the right half of the crystalline semiconductor layer 140. Conversely, in the case where the BT structure 120 is located on the right side of the crystalline semiconductor layer 140 and the FET structure 130 is located on the left side of the crystalline semiconductor layer 140, the E / C terminal 142 can be the right half of the crystalline semiconductor layer 140, and the S / D terminal 144 can be the left half of the crystalline semiconductor layer 140. Any other conceivable configuration and / or orientation of the terminals 142, 144 within the crystalline semiconductor layer 140 are possible. One or more intermediate contacts 146 can provide vertical electrical coupling between the crystalline semiconductor layer 140 and overlying metal lines and / or vias. Some portions of the crystalline semiconductor layer 140 can be converted into a silicide layer 148 to improve the conductivity between the intermediate contact 146 and the crystalline semiconductor layer 14, for example, by providing a conductive metal such as cobalt (Co), titanium (Ti), nickel (Ni), platinum (Pt), or similar materials on the upper surface of the target material. The conductive material can be annealed while in contact with the underlying semiconductor to produce the silicide layer 148 for electrically coupling the semiconductor material to the contact formed thereon. Then, any presently known or later developed solution (e.g., etching) can be used to remove the excess conductive material.

[0032] The BT structure 120 includes the E / C terminal 142 of the crystalline semiconductor layer 140 and other components located on the dielectric layer 106. The bipolar transistor structure further includes an E / C layer 150 located on the insulator layer 106, which is distal to the crystalline semiconductor layer 140 horizontally. The E / C layer 150 can be formed by a similar process (or in some cases, the same process) as that for forming the crystalline semiconductor layer 40 on the insulator layer 106. The E / C layer 150 can have the same doping type and / or a similar dopant concentration as the E / C terminal 142 of the crystalline semiconductor layer 140. The E / C layer 150 can be a single-crystalline structure. Optionally, the E / C layer 150 can have a different composition (e.g., silicon germanium (SiGe)) relative to the back-gate semiconductor layer 104 and / or the crystalline semiconductor layer 140, but generally has the same composition as the crystalline semiconductor layer 140. The E / C contact 154 formed of one or more metals or other conductors can be located on the E / C layer 150 to electrically couple the E / C layer 150 to the overlying metal wires and / or vias. The E / C layer 150 can also include a silicide layer thereon to improve the conductivity between the E / C layer 150 and the E / C contact 154.

[0033] The BT structure 120 includes: an intrinsic base 152 (i.e., undoped or lightly doped semiconductor material) located on the SOI layer 151 and an extrinsic base 156 located on the intrinsic base 152. The intrinsic base 152 is horizontally located between the E / C layer 150 and the E / C terminal 142 of the crystalline semiconductor layer 140. The intrinsic base 152 and the extrinsic base 156 together provide a base structure 157 to control the current flow between the E / C layer 150 and the E / C terminal 142 of the crystalline semiconductor layer 140. The base structure 157 itself defines the base terminal of the BT structure 120. The intrinsic base 152 can be a p-type doped single-crystalline SiGe and / or a similar semiconductor material having a conductivity type opposite to that of the E / C terminal 142 and the E / C layer 150 but a relatively low doping amount. The intrinsic base 152 can be located on the SOI layer 151 and above the insulator layer 106, above the back-gate semiconductor layer 104 (as Figure 1 、 3(as shown in FIGS. 5 and 7). The inner base 152 can be grown on the SOI layer 151 during any conventional replacement gate process and grown within the spacer 158. Optionally, portions of the SOI layer 151 can be removed to minimize its vertical thickness as much as possible while retaining sufficient semiconductor material to enable epitaxial growth thereon. The doping type of the inner base 152 is adjustable to provide NPN or PNP conduction types in the bipolar transistor. The outer base 156 can have the same doping polarity as the inner base 152 but with a higher dopant concentration. The outer base 156 can be formed by selectively epitaxially growing polycrystalline semiconductor in an opening above the inner base 152.

[0034] The BT structure 120 can also include a set of spacers 158 located on the outer surface of the outer base 156 and, in some cases, on the sidewalls of the inner base 152. The spacers 158 can be provided as one or more bodies of insulating material formed, for example, by deposition, thermal growth, etc. on the upper surface of the material to electrically and physically insulate the material subsequently formed on the coated material from other components. According to one example, the spacers 158 can have one or more nitride insulator materials (e.g., SiN) or other types of insulator materials (e.g., SiO2) formed to a desired thickness. In this case, for example, the spacers 158 can be formed by nitriding the exposed outer surface (e.g., sidewalls) of an initial gate structure (e.g., a "dummy gate") to convert its material composition to a nitride insulator (e.g., from polycrystalline Si to silicon nitride (SiN) or other semiconductor oxides).

[0035] In addition to providing electrical insulation, the spacer 158 can also affect the shape of the outer base 156 over the inner base 152. For example, the outer base 156 can be substantially T-shaped by having a lower portion that is horizontally located between the spacers 158 (e.g., physically constrained by the spacers 158) and an upper portion that extends horizontally above the spacers 158 (and thus, overhangs). The outer base 156 can be substantially T-shaped because the base structure 156 is formed within the spacers 158 (i.e., by forming an initial gate structure (not shown) and replacing the initial gate structure with the base structure 157). The advantage of this processing configuration is to provide more contact area for the contact to land on the base structure 157. However, in additional embodiments, the outer base 156 can have any of a variety of structural configurations that are not T-shaped. The position and size of the spacer 158 can be controlled during processing to further affect the size and shape of the outer base 156. It should be understood that by omitting or varying the shape or position of the spacer 158, the base material can be formed to have other geometries (e.g., shapes other than "T"). The outer base 156 can also include a silicide layer 148 thereon for stronger coupling to the base contact 160. The silicide layer 148 can be formed by the same process or in the same process stage as other materials having a silicide layer 148 discussed herein.

[0036] The FET structure 130 can also be coupled to the crystalline semiconductor layer 140 and can include the S / D terminals 144 of the crystalline semiconductor layer 140. The FET structure 130 also includes an S / D layer 162 located on the insulator layer 106 and a channel layer 166 horizontally located between the crystalline semiconductor layer 140 and the S / D layer 162. The S / D layer 162 can have the same (or similar) material composition and doping profile as the S / D terminals 144. Both the S / D terminals 144 of the crystalline semiconductor layer 140 and the S / D layer 162 can have the same conduction type, such as p-type doping. The channel layer 166 can also be located above the backgate semiconductor layer 104 and the insulator layer 106, but can have a doping type opposite to that of the S / D terminals 144 and the S / D layer 162. In the case where the BT structure 120 provides an "NPN" transistor structure, the inner base 152 and the channel layer 166 can have the same doping type. The backgate semiconductor layer 104 itself can define the backgate terminal of the BT structure 120 and the FET structure 130, as discussed in detail herein.

[0037] Other portions of the FET structure 130 can be located between the S / D terminals 144 and the S / D layer 162, and above the channel layer 166. The FET structure 130 can include, for example, a gate dielectric layer 168, which can include any thin layer of dielectric material that can prevent electrical coupling between the channel region 166 and the electroactive material above the gate dielectric layer 168, while allowing the electric field within the gate conductor 170 to affect the conductivity within the channel region 166. The gate dielectric layer 168 can include, for example, a "high-k" dielectric material (i.e., any material having a dielectric constant of at least 3.9) or other presently known or later developed gate dielectric materials, and can include, by way of example, hafnium silicate (HfSiO), hafnium oxide (HfO2), zirconium silicate (ZrSiO x ), zirconium oxide (ZrO2), silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or any combination of these materials.

[0038] The gate conductor 170, which includes a conductive metal (e.g., copper, aluminum, and / or other metal wiring materials) and / or an active semiconductor material (e.g., doped polycrystalline Si and / or SiGe), can be located above the gate dielectric layer 168. In the case where the gate conductor 170 includes an active semiconductor material, the gate material 170 can include a silicide layer 148 thereon to improve the electrical interface between the gate conductor 170 and the metal lines and / or vias coupled thereto. The gate dielectric layer 168 and the gate conductor 170 together define a gate structure 171. The gate structure 171 itself can define the gate terminal of the FET structure 130. The gate contact 172 can vertically couple the gate conductor 170 to a metal line, via, and / or other components through a wiring layer (not shown). The gate contact 172 is shown in dashed lines to indicate that it may be in a different plane from Figure 1 the other components shown. Another set of spacers 158 can also cover the sidewalls of the gate conductor 170, for example, in a manner similar to the outer base 156.

[0039] The back-gate semiconductor region 104 can be electrically coupled to the back-gate terminal 174 to further affect the characteristics of the BT structure 120 and / or the FET structure 130, such as the conductivity within the crystalline semiconductor layer 140 and / or other layers 150, 162. The simultaneous back-gate biasing of the BT structure 120 and the FET structure 130 can be achieved by applying a single bias voltage (“Vbg”) to the back-gate terminal 174, which in turn electrically biases the interconnected portion of the back-gate semiconductor region 104 below the insulator layer 106 and below the structures 120, 130. In some embodiments, the structures 120, 130 can be zero back-biased (e.g., by applying a Vbg of 0.0V to the back-gate terminal 174). In other embodiments, the structures 120, 130 can be forward back-biased or reverse back-biased. Those skilled in the art will recognize that forward back-biasing (FBB) refers to a biasing condition in which a particular Vbg places the emitter or collector of the BT structure 120 at a higher potential or reduces the threshold voltage of the FET structure 130. Reverse back-biasing (RBB) refers to a biasing condition in which a particular Vbg has the opposite effect on the BT structure 120 (e.g., where an FBB places the emitter at a higher electrical potential, it can place the collector at a higher electrical potential) or increases the threshold voltage of the FET structure 130. The presence of the E / C terminals 142 and the S / D terminals 144 within the crystalline semiconductor layer 140 results in the application of the same amount of back-bias to each of the structures 120, 130 via the back-gate terminal 174.

[0040] The back-gate contact 176 can be located on the back-gate terminal 174 (e.g., it can be in contact with the silicide layer 148) to provide electrical coupling between the back-gate semiconductor layer 104 and the overlying metal lines and / or vias. Like other semiconductor components discussed herein, the silicide layer 148 can be located on the back-gate terminal 174. Applying an electrical potential to the back-gate semiconductor region 104 via the back-gate terminal 174 can induce charge within the back-gate semiconductor region 104, thereby creating an electrical potential difference between the back-gate semiconductor region 104 and other semiconducting materials across the insulator layer 106 (e.g., the crystalline semiconductor layer 140, the E / C layer 150, the inner base 152, the S / D layer 162, the channel layer 166, etc.). Among other effects, this electrical potential difference between the back-gate semiconductor region 104 and the overlying semiconductor layer can also affect electrical characteristics, such as the biasing of transistor structures, the FET structure 130, etc. For example, the electrical biasing of the back-gate semiconductor region 104 can increase or decrease the threshold voltage of the FET structure 130, i.e., the minimum voltage required to induce conductivity across the channel region 166 from the S / D terminals 144 to the S / D layer 166.

[0041] Structure 100 may include an interlayer dielectric (ILD) layer 180 located above insulator layer 106 and any other components thereon. ILD layer 180 may include the same insulating material as insulator layer 106 or may include a different electrically insulating material for vertically separating the active material from overlying materials (e.g., various horizontally extending wires or vias). Nevertheless, for example, since insulator layer 106 is vertically located between backgate semiconductor layer 104 and various components such as BT structure 120, FET structure 130, crystalline semiconductor layer 140, etc., ILD layer 180 and insulator layer 106 constitute different components. ILD layer 180 may be formed by deposition and / or other techniques to provide an electrically insulating material and may then be planarized (e.g., using CMP) such that its upper surface remains above active semiconductor layer 112, BT structure 120, FET structure 130, crystalline semiconductor layer 140, etc.

[0042] As previously discussed, structure 100 includes various contacts 146, 154, 160, 164, 172, 176 for electrically coupling structure 100 to overlying metal wires or vias (not shown). Contacts 146, 154, 160, 164, 172, 176 may be formed by performing a controlled amount of vertical etching to form openings to one or more contact locations and then filling these openings with a conductor within a predetermined portion of ILD layer 180. Each of contacts 146, 154, 160, 164, 172, 176 may include any presently known or later developed conductive material configured for electrical contact, e.g., tungsten (W), copper (Cu), aluminum (Al), etc. Contacts 146, 154, 160, 164, 172, 176 may additionally include a refractory metal liner (not shown) located beside ILD layer 180 to prevent electromigration degradation, short circuits to other components, etc.

[0043] Figure 2 A plan view of structure 100 is shown, wherein Figure 1The cross-sectional view shown is indicated by view line 1-1. Optionally, the BT structure 120 and the FET structure 130 can be coupled together by a base contact 160 and / or a gate contact 172 shared between the outer base 156 and the gate conductor 170. In this case, only one of the base contact 160 or the gate contact 172 can be included such that the contacts 160, 172 present in the structure 100 are a single node for electrical coupling to the outer base 156 and the gate conductor 170. To provide this feature, a portion of the outer base 156 can overlap and physically interface with the gate conductor 170 above the TI 110 at a location remote from the crystalline semiconductor layer 140. In an alternative embodiment, the gate conductor 170 can be vertically located above the outer base 156 and electrically coupled to the outer base 156. Among other advantages, the coupling of the outer base 156 to the gate conductor 170 can allow a single conductor to control multiple transistor structures 120, 130, and / or reduce the number of wiring layers and / or conductive vias required to operate the structure 100.

[0044] Figure 2 The crystalline semiconductor layer 140 is also shown as laterally extending beyond the space between two pairs of transistor structures 120, 130, e.g., allowing one crystalline semiconductor structure 140 to define E / C terminals 142 and S / D terminals 144 for each pair of transistor structures 120, 130. To electrically isolate each pair of transistor structures 120, 130 from each other, a deep well barrier 190 (e.g., a semiconductor material having a doping type opposite to that of the active semiconductor material in the structure 100) can be horizontally located between the two pairs of transistor structures 120, 130 (e.g., as shown, horizontally along the Y-axis between the transistor structures 120, 130). Although Figure 2 two pairs of transistor structures 120, 130 with a deep well barrier 190 are shown, it should be understood that any desired number of pairs of transistor structures 120, 130 can be interconnected by one crystalline semiconductor layer 140.

[0045] Figure 3 An example circuit diagram is shown that can be implemented by an embodiment of the structure 100 shown in Figure 1 and Figure 2 . Figure 3The figure of can be implemented using two pairs of BT structures 120 and FET structures 130, i.e., two implementations of structure 100 at different positions. As shown, the source or drain of each FET structure 130 can be coupled to the emitter or drain of the corresponding BT structure 120 at a shared node (e.g., through crystalline semiconductor layer 140). This coupling is possible due to the consistent composition and doping type of crystalline semiconductor layer 140, allowing terminals 142, 144 to be defined therein. In addition, the back-gate bias of all structures 120, 130 can be achieved through back-gate contacts 176 to back-gate semiconductor layer 104 at different positions. Further, BT structure 120 and FET structure 130 can be coupled at a shared node through gate contact 172.

[0046] Now refer to Figure 4 and Figure 5 , additional embodiments of structure 100 can include multiple crystalline semiconductor structures 140 horizontally located between multiple pairs of BT structures 120 and FET structures 130. Figure 4 A cross-sectional view of such a structure is shown, Figure 5 and a plan view of the structure is provided, where view line 4-4 indicates Figure 4 the perspective view in. Structure 100 also includes a crystalline semiconductor layer 140 on insulator layer 106 located between two BT structures 120. Although not shown, additional implementations of structure 100 can include a crystalline semiconductor layer 140 located between two FET structures 130. In any case, each of the various BT structures 120 and FET structures 130 can be located on insulator layer 106 and above back-gate semiconductor layer 104. In addition to allowing multiple BT structures 120 and / or FET structures 130 to be formed close to each other above insulator layer 106, crystalline semiconductor layer 140 can also allow each of the various structures 120, 130 to be electrically biased through (one or more) back-gate terminals 174 shared by multiple BT structures 120 and / or FET structures 130. The crystalline semiconductor layer 40 between BT structures 120 can include two E / C terminals 142 located therein (i.e., one for each adjacent BT structure 120). Other crystalline semiconductor layers 140 located between one BT structure 120 and one FET structure 130 can be subdivided into E / C terminals 142 and S / D terminals 144, e.g., as discussed herein with respect to Figure 1 . In addition to adding additional BT structures 120, FET structures 130, crystalline semiconductor layers 140, etc., structure 100 may be similar or identical in other respects to embodiments of structure 100 discussed elsewhere herein.

[0047] Refer to together Figures 4 - 6, embodiments of structure 100 may implement paired source - collector - connected and / or drain - emitter - connected transistor structures, where a single node simultaneously electrically biases multiple structures 120, 130. The source - collector and / or drain - emitter connections may pass through the (one or more) crystalline semiconductor layers 140 that are subdivided into terminals 142, 144 discussed herein. As Figure 4 , Figure 5 shown, two BT structures 120 (or alternatively, two FET structures 130) may be coupled by another crystalline semiconductor layer 140 having only E / C terminals 142 therein. This configuration may allow the source and collector terminals to be shared between structures 120, 130, and also allow the emitter terminals to be shared between two BT structures 120. The back - gate contact 176 may be shared by all transistor structures 120, 130 of structure 100, and thus, the back - gate contact 76 may be a single back - gate node for all transistors in structure 100. In alternative embodiments discussed herein, there may be multiple back - gate contacts 176 for biasing fewer than all transistor structures 120, 130 in structure 100.

[0048] Referring Figure 7 , other embodiments of structure 100 may include features for independently doping each region of the back - gate semiconductor layer 104 and thus implementing a multi - level back - gate bias in the back - gate semiconductor layer 104, and / or (one or more) intermediate contacts 146 that extend entirely through a portion of the crystalline semiconductor layer 140. In some embodiments, the (one or more) intermediate contacts 146 may extend entirely through the vertical thickness of the crystalline semiconductor layer 140 to physically contact the upper surface of the insulator layer 106. The (one or more) intermediate contacts 146 may be wider above the crystalline semiconductor layer 140, for example, to provide a physical interface between the intermediate contact 146 and the silicide layer 148 on the crystalline semiconductor layer 140. In this case, the portion of the crystalline semiconductor layer 40 horizontally located between the BT structure 120 and the intermediate contact 146 may define the E / C terminal 142, and the portion of the crystalline semiconductor layer 40 horizontally located between the FET structure 130 and the intermediate contact 146 may define the S / D terminal 144. Although the crystalline semiconductor layer 140 is shown as discontinuous in the Figure 7 plane shown, it will be understood that other portions of the crystalline semiconductor layer 40 may surround the intermediate contact 146 in front of and behind the page plane.

[0049] Structure 100 may include additional features located within the back-gate semiconductor layer 104, and these features may be included in other embodiments of structure 100 even in cases where the intermediate contact(s) 146 do not fully extend through the crystalline semiconductor layer 140. Where needed, additional TIs 110 may define a plurality of back-gate semiconductor regions 104 below the BT structure 120 and the FET structure 130 such that each of the back-gate semiconductor regions 104 may electrically bias only certain BT structures 120 and / or FET structures 130. The back-gate semiconductor layer 104 may include one or more deep well barriers 190 to electrically isolate the back-gate semiconductor layer 104 into different regions having different doping types. For example, the deep well barrier 190 may be located below the intermediate contact(s) 146 and may be highly doped p-type. The portions of the back-gate semiconductor layer 104 on each side of the deep well barrier 190 may each have a doping type opposite to that of the deep well barrier 190 (e.g., they may both be doped n-type), but the presence of the deep well barrier 190 and the TI 110 allows different portions of the back-gate semiconductor layer 104 on each side of the deep well barrier 190 to have independent electrical bias levels. To provide different amounts of electrical bias, different additional back-gate contacts 176 to the back-gate semiconductor layer 104 may be provided on each side of the deep well barrier 190.

[0050] Referring together Figure 8 and Figure 9 , a BT structure 120 and an FET structure 130 may be coupled to each other through a shared portion of the back-gate semiconductor layer 104 or through equivalent via contacts and metal lines (not shown). Another BT structure 120 and an FET structure 130 may share a back-gate terminal through another portion of the back-gate semiconductor layer 104. The deep well barrier 190 may physically and electrically separate different portions of the back-gate semiconductor layer 104 from each other such that different back-gate terminals 174 electrically bias the desired pairs of structures 120, 130. In such cases, each pair of structures 120, 130 may have an independently controllable back-gate bias applied thereto. In such cases, separate back-gate contacts 176 to each structure 120, 130 may be provided to control the amount of back-gate bias. It should also be understood that the outer bases 156 and gate conductors 170 of each structure 120, 130 may be coupled to separate nodes and are thus capable of independent control.

[0051] Figure 10 Another embodiment of structure 100 is shown, where, as compared with Figure 4 and Figure 5Similarly, multiple crystalline semiconductor structures 140 are horizontally located between multiple pairs of BT structures 120 and FET structures 130. Structure 100 also includes a crystalline semiconductor layer 140 located on insulator layer 106 and between two BT structures 120, where an intermediate contact 146 vertically extends through crystalline semiconductor layer 104 to insulator layer 106 (e.g., also as Figure 5 shown and described herein). Additionally, a deep well barrier 190 may be located within deep well semiconductor layer 104 to allow different portions thereof to have different amounts of back-gate bias and / or different amounts of doping. According to one example, one portion of back-gate semiconductor layer 104 may provide a back-gate bias to BT structures 120 and FET structures 130 on one side of intermediate contact 146, and another portion of the back-gate semiconductor layer may provide a back-gate bias to BT structures 120 and FET structures 130 on the other side of intermediate contact 146.

[0052] Each portion of back-gate semiconductor layer 104 on a respective side of deep well barrier 190 may be coupled to its own back-gate terminal 174 and back-gate contact 176. It should be understood that additional deep well barriers 190 and / or back-gate terminals 174 and back-gate contacts 176 may be included to allow for individual biasing of each BT structure 120 and / or FET structure 130. Aside from the presence of the several BT structures 120, FET structures 130, crystalline semiconductor layer 140, back-gate terminals 174, back-gate contacts 176, and the presence of deep well barrier 190, structure 100 may be similar or identical in other respects to embodiments of structure 100 discussed elsewhere herein.

[0053] During operation, source-collector and / or drain-emitter connections may pass through (one or more) crystalline semiconductor layers 140 subdivided into terminals 142, 144 discussed herein. As Figure 7 shown, two BT structures 120 (or alternatively, two FET structures 130) may be coupled through another crystalline semiconductor layer 140 having only E / C terminals 142 therein. One back-gate contact 176 may be coupled to one portion of back-gate semiconductor layer 104 on one side of deep well barrier 190, and another back-gate contact 176 may be coupled to another portion of back-gate semiconductor layer 104 on the other side of deep well barrier 190. In additional embodiments, there may be more back-gate contacts 176 for individually biasing either of the BT structures 120 and / or FET structures 130 by including additional back-gate terminals 174, back-gate contacts 178, and deep well barriers 190 in structure 100.

[0054] Embodiments of the present disclosure can provide several technical advantages, examples of which are discussed herein. For example, embodiments of the present disclosure allow for the provision of both a BT structure 120 and a bipolar transistor structure 130 together above a single back-gate semiconductor layer 104 through the presence of a crystalline semiconductor layer 140. Despite the presence of E / C terminals 142 and S / D terminals 144 therein, the composition and doping of the crystalline semiconductor layer 140 can be substantially uniform. These structural characteristics allow structure 100 to occupy less surface area on the device than a combination of conventional bipolar transistors and FETs. During operation, the ability to apply the same back-gate bias to both the BT structure 120 and the FET structure 130 can accommodate the higher performance requirements of certain bipolar transistors and can reduce the total power consumption in the device.

[0055] The methods and structures described above are used to fabricate integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in an original wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single-chip package (e.g., a plastic carrier with leads fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier having either or both surface interconnections and buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices, as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with a display, keyboard, or other input device, and a central processing unit.

[0056] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly dictates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. "Optional" or "optionally" means that the subsequent described event or circumstance may or may not occur, and the description includes instances where the event occurs and instances where it does not.

[0057] Approximating language, as used throughout the specification and claims, may be applied to modify any quantitative representation that could permit variation without resulting in a change in the basic function to which it is related. Accordingly, a value modified by one or more terms, such as "about", "approximately", and "substantially", is not limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of the instrument used to measure the value. Throughout this specification and the claims, range limitations may be combined and / or interchanged, such ranges being recognized and including all the sub-ranges contained therein, unless the context or language indicates otherwise. The "about" applied to a particular value of a range applies to both values and may indicate + / - 10% of said value, unless otherwise dependent on the precision of the instrument measuring the value.

[0058] All structural, material, acts, and equivalents of the means or step plus function elements in the following claims are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure with various embodiments having various modifications as are suited to the particular use contemplated.

Claims

1. A structure, comprising: A dielectric layer on a back-gate semiconductor layer; A bipolar transistor structure on the dielectric layer; A field-effect transistor (FET) structure on the dielectric layer; And A crystalline semiconductor layer on the dielectric layer, located between the bipolar transistor structure and the FET structure, wherein the crystalline semiconductor layer includes terminals of the bipolar transistor structure and terminals of the FET structure.

2. The structure according to claim 1, wherein, The crystalline semiconductor layer includes a shared emitter / collector (E / C) and source / drain (S / D) semiconductor material having a single composition between the bipolar transistor structure and the FET structure.

3. The structure according to claim 1, wherein, The crystalline semiconductor layer includes: An emitter / collector (E / C) layer on the dielectric layer and the bipolar transistor structure; A source / drain (S / D) layer on the dielectric layer and adjacent to the FET structure; and A contact on the dielectric layer and horizontally between the E / C layer and the S / D layer.

4. The structure according to claim 3 further includes a trench isolation TI within the back-gate semiconductor layer located below the contact, wherein, A first portion of the back-gate semiconductor layer located below the bipolar transistor structure is electrically biased independently of a second portion of the back-gate semiconductor layer located below the FET structure.

5. The structure according to claim 1, further comprising: A trench isolation (TI) within the back-gate semiconductor layer; And A back-gate contact to the back-gate semiconductor layer, wherein the TI is located between the back-gate contact and the crystalline semiconductor layer.

6. The structure according to claim 1, wherein, The bipolar transistor structure includes: An inner base layer on the dielectric layer and coupled to the crystalline semiconductor structure, wherein the inner base layer has a doping type opposite to that of the crystalline semiconductor layer; An outer base layer on the inner base layer, wherein the outer base layer is substantially T-shaped; and A spacer on the inner base layer and adjacent to the outer base layer, wherein an upper portion of the outer base layer is above the spacer.

7. The structure according to claim 6, wherein The inner base layer includes p-doped silicon germanium (SiGe).

8. A structure, comprising: A dielectric layer on a back-gate semiconductor layer; A crystalline semiconductor layer on the dielectric layer; A base structure on the dielectric layer and adjacent to a first horizontal end of the crystalline semiconductor layer; And A gate structure on the dielectric layer and adjacent to a second horizontal end of the crystalline semiconductor layer, wherein the crystalline semiconductor layer is horizontally located between the base structure and the gate structure.

9. The structure according to claim 8, wherein, The crystalline semiconductor layer includes a shared emitter / collector (E / C) and source / drain (S / D) semiconductor material having a single composition between the base structure and the gate structure.

10. The structure according to claim 8, wherein, The base structure is coupled to the gate structure.

11. The structure according to claim 8, wherein, The base structure and the gate structure are located in one of a plurality of FET-bipolar transistor pairs that horizontally sandwich the crystalline semiconductor layer therebetween.

12. The structure according to claim 8, further comprising: A trench isolation (TI) within the back-gate semiconductor layer; And A back-gate contact to the back-gate semiconductor layer, wherein the TI is located between the back-gate contact and the crystalline semiconductor layer.

13. The structure according to claim 8, wherein, The base structure includes: An inner base layer, which is located above the dielectric layer and has a doping type opposite to that of the crystalline semiconductor layer; An outer base layer, which is located on the inner base layer, wherein the outer base layer is substantially T-shaped; and A spacer, which is located on the inner base layer and adjacent to the outer base layer, wherein the upper portion of the outer base layer is located above the spacer.

14. The structure according to claim 8, further comprising: An additional base structure on the dielectric layer; And An additional crystalline semiconductor layer on the dielectric layer, which is located between the bipolar transistor structure and the additional base structure, wherein the additional crystalline semiconductor layer defines an emitter terminal for the base structure and the additional base structure.

15. A structure, comprising: A dielectric layer on a back-gate semiconductor layer; A contact to the dielectric layer; An emitter / collector E / C layer, which is located on the dielectric layer and adjacent to a first horizontal end of the contact; A base structure, which is located on the dielectric layer and adjacent to the E / C layer, wherein the E / C layer is horizontally located between the base structure and the contact; A source / drain S / D layer, which is located on the dielectric layer and adjacent to a second horizontal end of the contact; and A gate structure, which is located on the dielectric layer and adjacent to the S / D layer, wherein the S / D layer is horizontally located between the contact and the gate structure.

16. The structure according to claim 15 further includes a trench isolation TI within the back-gate semiconductor layer located below the contact, wherein, A first portion of the back-gate semiconductor layer located below the base structure is electrically biased independently of a second portion of the back-gate semiconductor layer located below the gate structure.

17. The structure according to claim 15, further comprising: A trench isolation TI located within the back-gate semiconductor layer; And A back-gate contact to the back-gate semiconductor layer, wherein the TI is located between the back-gate contact and the contact.

18. The structure according to claim 15, wherein, The base structure comprises: An inner base layer, which is located above the dielectric layer and has a doping type opposite to that of the E / C layer; An outer base layer, which is located on the inner base layer, wherein the outer base layer is substantially T-shaped; and A spacer, which is located on the inner base layer and adjacent to the outer base layer, wherein the upper portion of the outer base layer is located above the spacer.

19. The structure according to claim 18, wherein, The inner base layer comprises p-doped silicon germanium SiGe.

20. The structure according to claim 15, wherein The base structure is coupled to the gate structure.

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