Semiconductor device and semiconductor package including same

Abstract

The invention provides a semiconductor device and a semiconductor package including the same. A semiconductor device includes: an integrated circuit layer including a transistor; a first interconnect layer on a front side of the integrated circuit layer; a second interconnect layer on the back side of the integrated circuit layer; and a connection terminal on the second interconnection layer, in which the second interconnection layer includes: an insulating layer; an interconnection structure in the insulating layer; an active contact disposed between the interconnect structure and the source / drain region of the transistor and connected to the source / drain region; and a dummy metal structure spaced apart from the interconnect structure in the first direction, where the dummy metal structure does not overlap with the connection terminal in a second direction perpendicular to the first direction.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor device and a semiconductor package including the semiconductor device. Background Art

[0002] A backside thinning process has been introduced to address the wiring complexity of the back-end-of-line (BEOL) of one or more transistors, such as fin field-effect transistors (FinFETs) and nanosheet transistors (also referred to as multi-bridge-channel field-effect transistors (MBCFETs)).

[0003] Such a manufacturing process of a semiconductor device involving these transistors allows for the formation of one or more metal patterns for power delivery on the back side (opposite to the BEOL side) of the transistors. These metal patterns formed on the back side of the transistors are referred to as BSPDN or BSPDN structures, and the backside thinning process is referred to as the BSPDN process. Summary of the Invention

[0004] Embodiments of the inventive concept provide a semiconductor device and a semiconductor package including the semiconductor device, the semiconductor device having improved reliability by effectively discharging heat generated in the transistors to its back side.

[0005] An embodiment of the inventive concept provides a semiconductor device including: an integrated circuit layer including transistors; a first interconnect layer on a front side of the integrated circuit layer; a second interconnect layer on a back side of the integrated circuit layer; and connection terminals on the second interconnect layer, wherein the second interconnect layer includes: an insulating layer; an interconnect structure in the insulating layer; active contacts disposed between the interconnect structure and source / drain regions of the transistors and connected to the source / drain regions; and dummy metal structures spaced apart from the interconnect structure in a first direction, wherein the dummy metal structures do not overlap with the connection terminals in a second direction perpendicular to the first direction.

[0006] An embodiment of the inventive concept provides a semiconductor package including: a package substrate; and a first semiconductor device on the package substrate, wherein the first semiconductor device includes: an integrated circuit layer including transistors; a first interconnect layer on a front side of the integrated circuit layer; a second interconnect layer on a back side of the integrated circuit layer; and connection terminals on the second interconnect layer, wherein the second interconnect layer includes: an insulating layer; an interconnect structure in the insulating layer; active contacts disposed between the interconnect structure and source / drain regions of the transistors and connected to the source / drain regions; and dummy metal structures spaced apart from the interconnect structure in a first direction, wherein the dummy metal structures have a grid shape when observed in a plan view.

[0007] One embodiment of the inventive concept provides a semiconductor device comprising: an integrated circuit layer including transistors; a first interconnect layer on a front side of the integrated circuit layer; a second interconnect layer on a back side of the integrated circuit layer; and connection terminals on the second interconnect layer, wherein the transistors include: stacked channel patterns; gates surrounding the channel patterns; and first source / drain regions and second source / drain regions spaced apart from each other with the channel patterns interposed therebetween, wherein the semiconductor device further includes: first active contacts protruding from the first interconnect layer and connected to the first source / drain regions; second active contacts protruding from the second interconnect layer and connected to the second source / drain regions, wherein the second interconnect layer includes: an insulating layer including first and second depressions at a bottom of the second interconnect layer; an interconnect structure in the insulating layer; dummy metal structures disposed in the insulating layer and spaced apart from the interconnect structure; under-bump patterns filling the first depressions and disposed between the connection terminals and the insulating layer; and insulating patterns filling the second depressions and spaced apart from the under-bump patterns in a first direction, and wherein the insulating layer and the insulating patterns include different insulating materials. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments of the inventive concept will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The drawings represent non-limiting example embodiments as described herein.

[0009] Figure 1 is a cross-sectional view of a semiconductor device according to some embodiments of the inventive concept.

[0010] Figure 2 is Figure 1 an enlarged view of region “CU” in

[0011] Figure 3 is a plan view showing Figure 1 a first region and a second region of the semiconductor device.

[0012] Figure 4 , Figure 5 and Figure 6 are enlarged views corresponding to region “CU” in Figure 1 respectively.

[0013] Figure 7 is a cross-sectional view of a semiconductor package including a semiconductor device according to some embodiments of the inventive concept.

[0014] Figure 8 is a cross-sectional view of a semiconductor package including a semiconductor device according to some embodiments of the inventive concept.

[0015] Figure 9 , Figure 10 and Figure 11is a cross-sectional view showing a process of manufacturing a semiconductor device according to some embodiments of the inventive concept. Detailed embodiments

[0016] Hereinafter, a semiconductor device according to an embodiment of the inventive concept will be described with reference to the accompanying drawings.

[0017] Figure 1 is a cross-sectional view of a semiconductor device according to some embodiments of the inventive concept. Figure 2 is Figure 1 an enlarged view of the region “CU” in Figure 3 is a plan view showing Figure 1 a first region and a second region of the semiconductor device of

[0018] Referring to Figures 1 to 3 , the semiconductor device 1000 may be, for example, a logic chip. Specifically, the semiconductor device 1000 may be a logic chip such as an application specific integrated circuit (ASIC), a central processing unit (CPU), a graphics processing unit (GPU), and an application processor (AP).

[0019] The semiconductor device 1000 may include an integrated circuit layer ICL, a first interconnect layer 100, a second interconnect layer 200, connection terminals 260, a support substrate 400, and an adhesive layer 410. The first interconnect layer 100 may also be referred to as a signal interconnect layer 100. The second interconnect layer 200 may also be referred to as a power distribution interconnect layer 200.

[0020] The integrated circuit layer ICL may include an integrated circuit IC. The integrated circuit IC may include transistors. The transistors may have a gate-all-around FET structure or a multi-bridge-channel FET structure. The transistors may include a plurality of channel patterns CH, gates GE, and source / drain patterns SD. The plurality of channel patterns CH may be stacked in sequence. The source / drain patterns SD may also be referred to as source / drain regions SD.

[0021] The gates GE may be disposed on the channel patterns CH, fill the space between the channel patterns CH, and surround all sides of the channel patterns CH. The source / drain patterns SD may be spaced apart from each other such that the channel patterns CH are interposed therebetween. Each of the channel patterns CH and the source / drain patterns SD may include a semiconductor material such as silicon (Si), germanium (Ge), or silicon germanium (SiGe). A device isolation layer may be filled between the integrated circuits IC. The device isolation layer may include an oxide, for example, silicon oxide (SiO2).

[0022] The first active contact CA1 can be provided on one of a pair of adjacent source / drain patterns SD, and a channel pattern CH is disposed between the pair of adjacent source / drain patterns SD. Similarly, the second active contact CA2 can be provided on the other source / drain pattern SD of the pair of adjacent source / drain patterns SD. The first active contact CA1 can also be referred to as a front-side active contact CA1, and the second active contact CA2 can also be referred to as a back-side active contact CA2. The first active contact CA1 and the second active contact CA2 can be respectively connected to different source / drain patterns SD. A gate contact CB can be provided on a gate GE. The gate contact CB can be connected to the gate GE by penetrating a gate capping pattern CP covering the upper surface of the gate GE. The upper portion of the first active contact CA1 adjacent to the gate contact CB can be filled with an upper insulating pattern IP.

[0023] In this specification, a first direction D1 is defined as a first direction D1 parallel to the upper surface of the channel pattern CH. A second direction D2 is defined as a direction parallel to the upper surface of the channel pattern CH and perpendicular to the first direction D1. A third direction D3 is defined as a direction perpendicular to the upper surface of the channel pattern CH.

[0024] A first interconnect layer 100 can be disposed on the front side of an integrated circuit layer ICL. The first interconnect layer 100 can include a first insulating layer 110 and a first interconnect structure 120 disposed in the first insulating layer 110. The first insulating layer 110 can include an insulating material such as an oxide (e.g., SiO2). The first interconnect structure 120 can include a metal such as copper or aluminum. Each first interconnect structure 120 can include a plurality of first interconnect lines 121 stacked in the third direction D3 and first interconnect vias 122 interposed therebetween. The plurality of first interconnect lines 121 can be configured to route signals along a specific path.

[0025] A second interconnect layer 200 can be disposed on the back side of the integrated circuit layer ICL. The second interconnect layer 200 can include a second insulating layer 210, a second interconnect structure 220, and a dummy metal structure 230.

[0026] The second interconnect layer 200 can include first regions A1 and second regions A2 that are alternately and repeatedly arranged. The first region A1 is where the second interconnect structure 220 is provided, and the second region A2 is where the dummy metal structure 230 is disposed. Optionally, the first region A1 can be a portion of the second interconnect layer 200 that overlaps with a connection terminal 260 in the third direction D3, and the second region A2 can be another portion of the second interconnect layer 200 that does not overlap with the connection terminal 260 in the third direction D3.

[0027] The second insulating layer 210 may include a plurality of lower insulating layers. Each lower insulating layer may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and may include an inorganic insulating material.

[0028] The second interconnect structure 220 may include a plurality of second interconnect lines 221 stacked in the third direction D3 and second interconnect vias 222 disposed therebetween. Referring to Figure 3 , each second interconnect line 221 may include a first extension portion 2211 extending in the first direction D1 or a second extension portion 2212 extending in the second direction D2. In some cases, the second extension portion 2212 may connect two first extension portions 2211 to each other. The interconnect via 222 may be disposed at one or both ends of the second interconnect line 221. Most of the second interconnect structure 220 may be used as a power rail for transmitting power and form a power distribution network.

[0029] The dummy metal structure 230 may be spaced apart from the interconnect structure 220 in the first direction D1. The dummy metal structure 230 may not be electrically connected to the interconnect structure 220. The dummy metal structure 230 may include a plurality of grid patterns 231 and dummy vias 232 connecting the plurality of grid patterns 231 to each other. As Figure 3 shown, each grid pattern 231 may include a plurality of first dummy lines 2311 and a plurality of second dummy lines 2312 forming a grille shape. The first dummy lines 2311 may be spaced apart from each other in the second direction D2 and extend in the first direction D1. The second dummy lines 2312 may be spaced apart from each other in the first direction D1 and extend in the second direction D2. The first dummy lines 2311 and the second dummy lines 2312 may cross each other. The dummy via 232 may be disposed on the first dummy lines 2311, the second dummy lines 2312, or at their intersections.

[0030] The second interconnect structure 220 and the dummy metal structure 230 may include a metal such as copper or aluminum. The second interconnect line 221 may include the same metal material as the grid pattern 231 adjacent to it in the first direction D1. The second interconnect via 222 may include the same metal material as the dummy via 232 adjacent to it in the first direction D1.

[0031] The number of stacked grid patterns 231 may be equal to the number of stacked second interconnect lines 221. The number of dummy vias 232 may be greater than the number of second interconnect vias 222. For example, the number of dummy vias 232 in contact with one grid pattern 231 may be greater than the number of second interconnect vias 222 in contact with one second interconnect line 221.

[0032] According to some embodiments, the height 222H of the second interconnection path 222 and the height 232H of the dummy path 232 may be substantially the same. The height 222H of the second interconnection path 222 may correspond to the separation distance between the second interconnect lines 2221 adjacent to each other in the third direction D3. The height 232H of the dummy path 232 may correspond to the separation distance between the grid patterns 231 adjacent to each other in the third direction D3.

[0033] Some of the second interconnect structures 220 in the second interconnect structure 220 may be used as signal lines. These signal lines may not contact other second interconnect structures 220 and may not be connected to each other within the second interconnect layer 200. The first signal contact SC1 may be provided to protrude from the first interconnect structure 120 toward the integrated circuit layer ICL. The second signal contact SC2 connected to the first signal contact SC1 may be provided from some of the second interconnect structures 220 that form the signal lines. At least one of the first signal contact SC1 and the second signal contact SC2 may penetrate the integrated circuit layer ICL. The first signal contact SC1 and the second signal contact SC2 may be connected to each other. According to some embodiments, the first signal contact SC1 and the second signal contact SC2 may be in direct contact. Both the first signal contact SC1 and the second signal contact SC2 may be electrically connected to the above-mentioned gate contact CB.

[0034] The second insulating layer 210 may fill the space between the second interconnect structure 220 and the dummy metal structure 230, the space between the stacked second interconnect lines 221, the space between the stacked grid patterns 231, and the intersection of the first dummy line 2311 and the second dummy line 2312. The second insulating layer 210 may include a first recess R1 and a second recess R2 at its lower portion. The first recess R1 may be provided in a first region A1 of the second interconnect layer 200, and the second recess R2 may be provided in a second region A2 of the second interconnect layer 200. The first recess R1 may overlap the second interconnect structure 220 in a third direction D3. The second recess R2 may overlap the dummy metal structure 230 in the third direction D3. The first recess R1 may expose the lower surface of the lowermost second interconnect line 221M among the stacked second interconnect lines 221. The lowermost second interconnect line 221M may include a pad (e.g., an aluminum pad). An under bump pattern 250 may be provided in the first recess R1. The under bump pattern 250 may fill at least a part of the first recess R1. The under bump pattern 250 may extend onto the lower surface of the second insulating layer 210. The under bump pattern 250 may be electrically connected to the second interconnect structure 220 through the pad and may not be electrically connected to the dummy metal structure 230. The under bump pattern 250 may include a metal material such as titanium, nickel, copper, etc. A connection terminal 260 may be provided on the under bump pattern 250. The connection terminal 260 may include a conductive material such as solder containing tin, silver, etc. The connection terminal 260 may have a shape such as a pillar or a protrusion. The second recess R2 may not expose the lowermost grid pattern 231M among the grid patterns 231. The depth X2 of the second recess R2 may be less than the depth X1 of the first recess R1. The depth X2 of the second recess R2 and the depth X1 of the first recess R1 may be measured in the third direction D3. An insulating pattern 240 may be provided in the second recess R2. The insulating pattern 240 may fill at least a part of the second recess R2. The insulating pattern 240 may include an insulating material different from the insulating material of the second insulating layer 210. Both the insulating pattern 240 and the second insulating layer 210 may include a low dielectric material. The insulating pattern 240 may include a material having a higher thermal conductivity than the second insulating layer 210. For example, the insulating pattern 240 may include a carbon-containing polymer, aluminum oxide (Al2O3), boron nitride (BN), and / or an epoxy polymer compound. According to some embodiments, the insulating pattern 240 may extend onto the lower surface of the second insulating layer 210. A support substrate 400 may be provided on the first interconnect layer 100. The support substrate 400 may be, for example, a silicon substrate. An adhesive layer 410 may be provided between the support substrate 400 and the first interconnect layer 100. For example, the adhesive layer 410 may include a material such as silicon oxide or silicon nitride.

[0035] According to an embodiment of the present inventive concept, the semiconductor device 1000 may include a dummy metal structure 230 that is electrically insulated from the power rail and signal line of the second interconnect structure 220 on the back side of the integrated circuit layer ICL and disposed adjacent thereto. The dummy metal structure 230 may serve as a heat sink to dissipate heat generated by the second interconnect structure 220 during operation of the semiconductor device 1000. When the second interconnect structure 220 and the dummy metal structure 230 are electrically connected, the dummy metal structure 230 may also serve as a path for current, thereby increasing the total resistance. In addition, the second interconnect structure 220 may be electrically connected to the integrated circuit layer ICL, and charges generated by plasma generated during the manufacturing process may be transferred to the integrated circuit layer ICL, reducing the reliability of the semiconductor device 1000. In contrast, according to an embodiment of the present inventive concept, the second interconnect structure 220 may be electrically insulated from the dummy metal structure 230, thereby reducing damage caused by plasma. In addition, the insulating pattern 240 disposed adjacent to the dummy metal structure 230 may include a material having a high thermal conductivity, maximizing the heat dissipation effect.

[0036] Figure 4 , Figure 5 and Figure 6 is a diagram showing a semiconductor device according to some embodiments, and corresponds to Figure 2 In addition to the following description, since it is similar to the Figures 1 to 3 The contents of the description are the same, so repeated descriptions will be omitted.

[0037] Reference Figure 4 , the semiconductor device according to some embodiments may not include the insulating pattern 240. In other words, the insulating pattern 240 may not fill the second recess R2.

[0038] Reference Figure 5 According to some embodiments, the second recess R2 may expose the lowermost mesh pattern 231M. The depth of the second recess R2 may be substantially the same as the depth of the first recess R1. The insulating pattern 240 may be in direct contact with the lowermost mesh pattern 231M.

[0039] Reference Figure 6 , the semiconductor device according to some embodiments may not include the insulating pattern 240. The second recess R2 may expose the lowermost mesh pattern 231M, and a depth of the second recess R2 may be substantially the same as a depth of the first recess R1.

[0040] Figure 7 is a cross-sectional view of a semiconductor package including a semiconductor device according to some embodiments of the inventive concept.

[0041] Reference Figure 7, the semiconductor package 2000 may include a semiconductor device 1000 and a package substrate 300 disposed under the semiconductor device 1000. The package substrate 300 may be one of the following: an interposer substrate, a printed circuit board, a redistribution substrate, or another semiconductor device. When the package substrate 300 is a semiconductor device, the semiconductor device 1000 located on top may be referred to as the first semiconductor device 1000, and the semiconductor device 300 located at the bottom may be referred to as the second semiconductor device 300. A plurality of connection pads 320 may be provided on the package substrate 300, and each connection pad 320 is in contact with a connection terminal 260. The plurality of connection pads 320 may be electrically connected to the semiconductor device 1000 through the connection terminals 260. The connection pads 320 may be connected to vias 330 provided thereunder. A solder mask layer 310 may be provided on the upper surface of the package substrate 300, exposing at least a part of the upper surface of the connection pads 320. An underfill layer UF may be provided between the package substrate 300 and the semiconductor device 1000. The underfill layer UF may be in contact with the insulating layer 210 and the insulating pattern 240. The underfill layer UF may fill the space between the connection terminals 260. The underfill layer UF may include an epoxy compound. According to some embodiments, the insulating pattern 240 may be omitted, and the second recess R2 may not be filled (refer to Figure 4 and Figure 6 ). The underfill layer UF may fill the second recess R2 and be spaced apart from the dummy metal structure 230 (refer to Figure 4 ). According to some embodiments, the underfill layer UF may fill the second recess R2 and may be in contact with the dummy metal structure 230 (refer to Figure 6 ).

[0042] Figure 8 is a cross-sectional view of a semiconductor package including a semiconductor device according to some embodiments of the inventive concept. Except for those described below, since it is the same as the content described in Figure 7 , the repeated description will be omitted.

[0043] Refer to Figure 8, the semiconductor package 3000 may further include a molding structure 500. A underfill layer UF between the semiconductor device 1000 and the package substrate 300 may be omitted. The molding structure 500 may cover the upper surface and the side surfaces of the semiconductor device 1000 and the upper surface of the package substrate 300. The molding structure 500 may extend between the semiconductor device 1000 and the package substrate 300 and may contact the lower surfaces of the insulating layer 210 and the insulating pattern 240. The molding structure 500 may fill the space between the connection terminals 260. The molding structure 500 may include an epoxy molding compound. According to some embodiments, the insulating pattern 240 may be omitted and the second recess R2 (refer to Figure 4 and Figure 6 ) may not be filled. The molding structure 500 may fill the second recess R2 and be spaced apart from the dummy metal structure 230 (refer to Figure 4 ). According to some embodiments, the molding structure 500 may fill the second recess R2 and may contact the dummy metal structure 230 (refer to Figure 6 ).

[0044] Figures 9 to 11 are views showing a process of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0045] Refer to Figure 9, an integrated circuit IC including transistors can be formed on the front surface of a semiconductor substrate (e.g., a wafer). The transistors can be formed using an MBCFET or GAA formation process. After forming the transistors, a first active contact CA1 connected to the source / drain pattern SD and a gate contact CB connected to the gate GE can be formed. A first interconnect layer 100 can be formed on the front surface of the semiconductor substrate. The first interconnect layer 100 can be bonded to a support substrate 400 through an adhesive layer 410. A process can be performed to reduce the thickness of the back surface of the semiconductor substrate. This reduction in thickness can expose the source / drain pattern SD and form an integrated circuit layer ICL. The integrated circuit layer ICL can be formed by reducing the thickness of the semiconductor substrate on which the integrated circuit IC is formed. A second active contact CA2 can be formed on the source / drain pattern SD. Subsequently, a second interconnect layer 200 can be formed on the integrated circuit IC. Forming the second interconnect layer 200 includes several steps. For example, the several steps include: forming a first lower insulating layer, forming a first metal layer on the first lower insulating layer, and patterning the first metal layer to simultaneously form a second interconnect line 221 and a grid pattern 231. Subsequently, the several steps further include: forming a second lower insulating layer covering the second interconnect line 221 and the grid pattern 231, forming via holes for interconnecting and dummy via holes exposing the second interconnect line 221 and the grid pattern 231 in the second lower insulating layer, forming a second metal layer filling the via holes for interconnecting and the dummy via holes, and patterning the second metal layer to simultaneously form a second interconnect via 222 and a dummy via 232. The second interconnect structure 220 can be formed by repeating the formation of the second interconnect line 221 and the second interconnect via 222. The dummy metal structure 230 can be formed by repeating the formation of the grid pattern 231 and the dummy via 232. The second insulating layer 210 can be formed by repeating the formation of the lower insulating layer, where a third lower insulating layer is formed on the topmost second interconnect line 221M and the topmost grid pattern 231M. The topmost second interconnect line 221M can include pads (e.g., aluminum pads). Thereafter, a first recess R1 and a second recess R2 can be formed at the upper surface of the second insulating layer 210. An under bump layer 250L can be formed on the upper surface of the second insulating layer 210, filling part of both the first recess R1 and the second recess R2. The under bump layer 250L can include at least one of nickel, gold, copper, titanium, and tungsten. The under bump layer 250L can be composed of a single layer or multiple layers.

[0046] Referring to Figure 10, a first photomask pattern PR1 including a first opening OP1 exposing a first recess R1 may be formed on the bump lower layer 250L. The first photomask pattern PR1 may be formed using a photoresist material through an exposure and development process. The first photomask pattern PR1 may fill a second recess R2. Using the bump lower layer 250L as an electrode, an initial connection terminal 260P may be formed through an electroplating process. The bump lower layer 250L may be used as a seed layer for this electroplating process.

[0047] Referring to Figure 11 , the first photomask pattern PR1 may be removed. The bump lower layer 250L in a portion that does not overlap with the initial connection terminal 260P in the third direction D3 may be removed using the initial connection terminal 260P as an etch mask. This process patterns the bump lower layer 250L to form a bump under pattern 250. Then, a second photomask pattern PR2 may be formed, the second photomask pattern PR2 covering the upper surface of the initial connection terminal 260P and the upper surface of the second insulating layer 210 and including a second opening OP2 exposing the second recess R2. Then a heat transfer insulating layer 240L may be formed to fill the second recess R2. Depending on the material used (e.g., aluminum oxide), the heat transfer insulating layer 240L may be formed through a deposition process such as a chemical vapor deposition process. Optionally, if the heat transfer insulating layer 240L includes an insulating material such as a spin-on hard mask, the heat transfer insulating layer 240L may be formed by coating and spinning the insulating material.

[0048] Referring again to Figure 1 and Figure 2 , the second photomask pattern PR2 may be removed. For example, other portions of the heat transfer insulating layer 240L covering the second photomask pattern PR2 may be removed by lift-off except for the portion of the heat transfer insulating layer 240L filling the second recess R2. The heat transfer insulating layer 240L filling the second recess R2 remains to form an insulating pattern 240. The connection terminal 260 may be formed from the initial connection terminal 260P by performing a reflow process. According to some embodiments, the reflow process may be performed after forming the bump under pattern 250 and before forming the second photomask pattern PR2. In addition, the semiconductor device 1000 may be completed through a sawing process.

[0049] According to an embodiment of the inventive concept, a semiconductor device may include a dummy metal structure disposed adjacent to a power rail and a signal line on a back side of an integrated circuit layer but electrically insulated therefrom. In addition, an insulating pattern disposed adjacent to the dummy metal structure and exposed to the outside may include a material having a high thermal conductivity. The combination of the dummy metal structure and the insulating pattern may enhance the heat dissipation effect of the semiconductor device.

[0050] Although the embodiments have been described above, those skilled in the art will understand that many modifications and variations can be made without departing from the spirit and scope of the inventive concept set forth in the appended claims. Therefore, the embodiments of the inventive concept should be considered illustrative rather than restrictive, and the spirit and scope of the inventive concept are indicated by the appended claims.

[0051] This application claims priority to Korean Patent Application No. 10-2024-0003948, filed with the Korean Intellectual Property Office on January 10, 2024, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: an integrated circuit layer including transistors; a first interconnect layer on a front side of the integrated circuit layer; a second interconnect layer on a back side of the integrated circuit layer; and connection terminals on the second interconnect layer, wherein the second interconnect layer includes: an insulating layer; an interconnect structure in the insulating layer; active contacts disposed between the interconnect structure and source / drain regions of the transistors and connected to the source / drain regions; and dummy metal structures spaced apart from the interconnect structure in a first direction, and wherein the dummy metal structures do not overlap the connection terminals in a second direction perpendicular to the first direction.

2. The semiconductor device according to claim 1, wherein the interconnect structure includes interconnect lines and at least one interconnect via connected to the interconnect lines, and wherein the dummy metal structures include a grid pattern and a plurality of dummy vias connected to the grid pattern.

3. The semiconductor device according to claim 2, wherein the number of the dummy vias directly contacting one of the grid patterns is greater than the number of the interconnect vias directly contacting one of the interconnect lines.

4. The semiconductor device according to claim 1, wherein the dummy metal structures are not electrically connected to the interconnect structure.

5. The semiconductor device according to claim 1, wherein the interconnect structure includes a plurality of stacked interconnect lines, wherein the dummy metal structures include a plurality of stacked grid patterns, and wherein the number of the plurality of stacked interconnect lines is the same as the number of the plurality of stacked grid patterns.

6. The semiconductor device according to claim 5, wherein the interconnect lines are at the same level as the grid pattern adjacent to them in the first direction.

7. The semiconductor device according to claim 1, wherein the insulating layer includes a first recess disposed under the interconnect structure and a second recess spaced apart from the first recess in the first direction and overlapping the dummy metal structures in the second direction, wherein the semiconductor device further includes: a under-bump pattern disposed in the first recess and interposed between the connection terminals and the interconnect structure; and an insulating pattern disposed in the second recess, and wherein the insulating pattern includes an insulating material different from the insulating layer.

8. The semiconductor device according to claim 7, wherein the insulating pattern includes aluminum oxide (Al2O3), bismuth oxide (Bi2O3), silicon carbide (SiC), boron nitride (BN), carbon (C), and / or an epoxy polymer compound.

9. The semiconductor device according to claim 7, wherein the depth of the first recess is greater than or equal to the depth of the second recess.

10. The semiconductor device according to claim 7, wherein the second recess exposes the dummy metal structures.

11. The semiconductor device according to claim 7, wherein the second recess is spaced apart from the dummy metal structures.

12. The semiconductor device according to claim 1, further comprising: A first signal contact that extends in the second direction from the first interconnect layer towards the integrated circuit layer; and A second signal contact that extends in the second direction from the second interconnect layer towards the integrated circuit layer, wherein the first signal contact and the second signal contact are in contact with each other.

13. A semiconductor package, comprising: A package substrate; and A first semiconductor device on the package substrate, wherein the first semiconductor device includes: An integrated circuit layer including transistors; A first interconnect layer on the front side of the integrated circuit layer; A second interconnect layer on the back side of the integrated circuit layer; and Connection terminals on the second interconnect layer, wherein the second interconnect layer includes: An insulating layer; An interconnect structure in the insulating layer; Active contacts disposed between the interconnect structure and the source / drain regions of the transistors and connected to the source / drain regions; and Dummy metal structures spaced apart from the interconnect structure in a first direction, and wherein the dummy metal structures have a grid shape when viewed in a plan view.

14. The semiconductor package according to claim 13, wherein the package substrate includes an interposer substrate, a printed circuit board, or a redistribution substrate.

15. The semiconductor package according to claim 14, wherein the insulating layer includes a first recess disposed under the interconnect structure and a second recess spaced apart from the first recess in the first direction, wherein the second recess vertically overlaps with the dummy metal structures, and wherein the semiconductor package further includes an under-bump pattern disposed in the first recess and interposed between the connection terminals and the interconnect structure.

16. The semiconductor package according to claim 15, further including an underfill layer disposed between the package substrate and the first semiconductor device, wherein the underfill layer fills the second recess.

17. The semiconductor package according to claim 15, further including a molding structure covering the upper surface of the package substrate and the side and upper surfaces of the first semiconductor device, wherein the molding structure fills the space between the package substrate and the first semiconductor device and fills the second recess.

18. The semiconductor package according to claim 13, wherein the grid shape includes: At least two first dummy lines extending in the first direction, At least two second dummy lines extending in a second direction perpendicular to the first direction, wherein the at least two first dummy lines and the at least two second dummy lines cross each other.

19. The semiconductor package according to claim 15, further including an insulating pattern filling the second recess, wherein the insulating pattern includes aluminum oxide (Al2O3), bismuth oxide (Bi2O3), silicon carbide (SiC), boron nitride (BN), carbon (C), and / or epoxy polymer compounds.

20. A semiconductor device, comprising: An integrated circuit layer including transistors; A first interconnect layer on the front side of the integrated circuit layer; A second interconnect layer on the back side of the integrated circuit layer; and Connection terminals on the second interconnect layer, Wherein the transistor includes: Stacked channel patterns; A gate surrounding the channel patterns; and A first source / drain region and a second source / drain region, spaced apart from each other with the channel patterns interposed therebetween, Wherein the semiconductor device further includes: A first active contact protruding from the first interconnect layer and connected to the first source / drain region; and A second active contact protruding from the second interconnect layer and connected to the second source / drain region, Wherein the second interconnect layer includes: An insulating layer including a first recess and a second recess at the bottom of the second interconnect layer; An interconnect structure in the insulating layer; A dummy metal structure disposed in the insulating layer and spaced apart from the interconnect structure; An under-bump pattern filling the first recess and disposed between the connection terminal and the insulating layer; and An insulating pattern filling the second recess and spaced apart from the under-bump pattern in a first direction, and Wherein the insulating layer and the insulating pattern include different insulating materials.

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