NLDMOS and preparation method of NLDMOS
By setting up a top structure in NLDMOS to form an N-P-N-P-N structure, the problem of insufficient ESD protection effect and integration in the prior art is solved, and bidirectional ESD protection and integration improvement are achieved.
Patent Information
- Application Number
- CN202510405982.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-02
- Publication Date
- 2025-07-11
AI Technical Summary
The existing NLDMOS has shortcomings in taking into account the ESD protection effect and integration, and additional ESD protection devices are needed to achieve bidirectional protection.
By setting up a top structure in the substrate, a bidirectional conduction N-P-N-P-N structure is formed, and a PNPN structure is formed using the first well region, buried layer, body region and source region, and a NPNP structure is connected in parallel to achieve bidirectional ESD protection without the need for additional ESD protection devices.
While achieving bidirectional ESD protection, it improves integration, simplifies the structure and reduces the number of devices.
Smart Images
Figure CN120302718A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of microelectronics technology, and in particular to an NLDMOS and a method for manufacturing an NLDMOS. Background Art
[0002] The Bipolar-CMOS-DMOS (BCD) process can integrate three different manufacturing technologies on the same chip, including manufacturing bipolar transistors for high-precision processing of analog signals, complementary metal oxide semiconductors (CMOS) for designing digital control circuits, and discrete metal oxide semiconductor (DMOS) devices for developing power supplies and high-voltage switching devices. Among them, DMOS devices mainly include two types, one is a vertical double-diffused MOSFET (VDMOS), and the other is a lateral double-diffused MOSFET (LDMOS).
[0003] In the prior art, two ESD paths, positive and negative, are required to achieve bidirectional protection. Generally, the base is protected against ESD through a PNPN structure, and an additional ESD protection device is used to connect to the cathode (i.e., the P-sub terminal) to protect the P-sub terminal from ESD. Therefore, it is impossible to balance the ESD protection effect and the integration degree. Summary of the Invention
[0004] The technical problem solved by the present invention is to provide an NLDMOS and a method for manufacturing an NLDMOS, so as to improve the integration degree while taking into account the ESD protection effect.
[0005] To solve the above technical problem, the technical solution of the present invention provides an NLDMOS, including: a substrate, in which a buried layer is provided; a body region, a first well region, a source region, a base region, and an anti-parallel structure located on the buried layer, the body region and the first well region are independent of each other, the source region and the base region are adjacent and both are located in the body region, the source region is connected to the anode, the base region is connected to the base, the anti-parallel structure is located in the first well region and is connected to the cathode, the anti-parallel structure includes a first heavily doped region and a second heavily doped region in close contact along the surface direction of the substrate, wherein the conductive types of the substrate, the body region, the base region, the first well region, and the first heavily doped region are P-type, and the conductive types of the buried layer, the source region, and the second heavily doped region are N-type.
[0006] Optionally, it further includes: an N-type drift region and a drain region. The drift region is located on the top surface of the buried layer and between the body region and the first well region. The drain region is a heavily doped region and is located within the drift region.
[0007] Optionally, it further includes: a gate structure. The gate structure is located on the junction surface between the body region and the drift region, and the source region and the drain region are respectively located on both sides of the gate structure.
[0008] Optionally, it further includes: an N-type second well region and a third heavily doped region. The second well region is located on the top surface of the buried layer and between the drift region and the first well region. The third heavily doped region is located within the second well region. The third heavily doped region and the second heavily doped region are respectively located on both sides of the first heavily doped region. The third heavily doped region is connected to the HVBN terminal.
[0009] Optionally, it further includes: a first isolation structure. The first isolation structure is located between the first heavily doped region and the third heavily doped region and between the first well region and the second well region. The depths of the first well region and the second well region are both greater than the height of the first isolation structure.
[0010] Optionally, it further includes: a P-type third well region and a fourth heavily doped region. The third well region is located on the top surface of the buried layer and between the drift region and the second well region. The fourth heavily doped region is located within the third well region.
[0011] Optionally, it further includes: a second isolation structure. The second isolation structure is located between the third heavily doped region and the fourth heavily doped region and between the second well region and the third well region. The depths of the second well region and the third well region are both greater than the height of the second isolation structure.
[0012] Optionally, it further includes: a third isolation structure. The third isolation structure is located between the drain region and the fourth heavily doped region and between the drift region and the third well region. The depths of the drift region and the third well region are both greater than the height of the third isolation structure.
[0013] Optionally, the NLDMOS is a ring structure.
[0014] Correspondingly, the technical solution of the present invention further provides a method for manufacturing an NLDMOS to manufacture the NLDMOS as described in any one of the above.
[0015] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0016] In the NLDMOS provided by the technical solution of the present invention, the top-to-top structure is located in the first well region and connected to the cathode, and the top-to-top structure includes a first heavily doped region and a second heavily doped region that are in close contact along the surface direction of the substrate. Therefore, by providing a second heavily doped region in the first well region that can form a top-to-top structure with the first heavily doped region, not only can a PNPN structure be formed based on the first well region, the buried layer, the body region, and the source region as the ESD conduction path of the base, but also an NPNP structure parallel to the PNPN structure is formed based on the second heavily doped region, the first well region, the buried layer, and the body region as the ESD conduction path of the cathode. Thus, the NLDMOS forms a bidirectional N-P-N-P-N structure with a simple structure, achieving bidirectional ESD protection without the need to provide additional ESD protection devices. Therefore, while taking into account the ESD protection effect, the integration degree is improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 is a schematic structural diagram of an NLDMOS;
[0018] Figure 2 is Figure 1 a partial equivalent circuit diagram of
[0019] Figure 3 is a schematic structural diagram of the NLDMOS according to an embodiment of the present invention;
[0020] Figure 4 is Figure 3 the equivalent circuit diagram of the ESD protection circuit in
[0021] DESCRIPTION OF THE REFERENCE NUMERALS
[0022] 1, 11, 21 - PNP structure; 2, 12, 22 - NPN structure;
[0023] 100, 200 - substrate; 110, 210 - buried layer; 120, 220 - body region; 121, 221 - source region; 122, 222 - base region; 130, 230 - drift region; 131, 231 - drain region; 140, 150, 160 - well region; 141, 151, 161 - heavily doped region; 170, 270 - gate structure; 240 - third well region; 241 - fourth heavily doped region; 250 - second well region; 251 - third heavily doped region; 260 - first well region; 261 - first heavily doped region; 262 - second heavily doped region; 281 - first isolation structure; 282 - second isolation structure; 283 - third isolation structure. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0024] As described in the background art, the existing NLDMOS cannot take into account both the ESD protection effect and the integration degree. The following is a detailed description with reference to the drawings.
[0025] Figure 1 It is a schematic structural diagram of an NLDMOS.
[0026] Please refer to Figure 1 , the NLDMOS may include: a substrate 100 and a gate structure 170.
[0027] There are buried layers 110, body regions 120, source regions 121, base regions 122, drift regions 130, drain regions 131, well regions 140, heavily doped regions 141, well regions 150, heavily doped regions 151, well regions 160 and heavily doped regions 161 distributed in the substrate 100. Among them, the conduction types of the substrate 100, body regions 120, base regions 122, well regions 140, heavily doped regions 141, well regions 160 and heavily doped regions 161 are all N-type, and the conduction types of the buried layers 110, source regions 121, drift regions 130, drain regions 131, well regions 150 and heavily doped regions 151 are all P-type.
[0028] The body regions 120, drift regions 130, well regions 140, well regions 150 and well regions 160 are all located on the top surface of the buried layer 110. The well region 140 is located between the body region 120 and the well region 160, the drift region 130 is located between the body region 120 and the well region 140, and the well region 150 is located between the well region 140 and the well region 160. The source region 121 and the base region 122 are located in the body region 120. The source region 121 is connected to the anode (i.e., the S terminal shown in Figure 2 ), and the base region 122 is connected to the base (i.e., the B terminal shown in Figure 2 ). The drain region 131 is located in the drift region 130, and the drain region 131 is connected to the drain (i.e., the D terminal shown in Figure 2 ). The heavily doped region 141 is located in the well region 140. The heavily doped region 151 is located in the well region 150, and the heavily doped region 151 is connected to the Hvbn terminal. The heavily doped region 161 is located in the well region 160, and the heavily doped region 161 is connected to the cathode (i.e., the PSUB terminal shown in Figure 2 ). The gate structure 170 is located on the surface of the substrate 100 between the source region 121 and the drain region 131, and the gate structure 170 is connected to the G terminal.
[0029] It should be noted that Figure 1 in order to facilitate understanding and explanation, the P-type region above the buried layer 110 is filled in blue, and the N-type region above the buried layer 110 is filled in red.
[0030] Please refer to Figure 2 , Figure 2 is Figure 1 a local equivalent circuit diagram of Figure 1In the NLDMOS, the well region 160, the buried layer 110, and the body region 120 form a PNP structure 1. The buried layer 110, the body region 120, and the source region 121 form an NPN structure 2. The PNP structure 1 and the NPN structure 2 are connected back-to-back to form a PNPN structure, which serves as the ESD release path for the B terminal, achieving ESD protection for the B terminal.
[0031] However, this NLDMOS still requires an additional ESD protection device to connect to the PSUB terminal to form an ESD release path for the PSUB terminal for ESD protection of the PSUB terminal. Therefore, to achieve the ESD protection effect, the integration of the NLDMOS is relatively low.
[0032] To solve the above technical problems, the technical solution of the present invention provides an NLDMOS and a preparation method thereof. By arranging an opposite structure located in the first well region and connected to the cathode in the substrate, a bidirectional conduction N-P-N-P-N structure is formed, thereby achieving two-way ESD protection through a simple structure without the need to set up additional ESD protection devices. Thus, while taking into account the ESD protection effect, the integration is improved.
[0033] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
[0034] The terms "first", "second", "third", "fourth", etc. (if any) in the specification, claims, and drawings of the present invention are used to distinguish similar objects and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order different from those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices. In addition, directional terms such as above, below, up, down, upward, downward, left, right, etc. are used relative to the exemplary embodiments as shown in the figures, with the upward or upper direction facing the top of the corresponding figure and the downward or lower direction facing the bottom of the corresponding figure.
[0035] Figure 3It is a schematic structural diagram of the NLDMOS according to an embodiment of the present invention.
[0036] Please refer to Figure 3 , the NLDMOS may include: a substrate 200.
[0037] In this embodiment, the substrate 200 is a silicon substrate 200.
[0038] In other embodiments, the substrate may include at least one of the following materials: Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III / V compound semiconductors. Or the substrate 200 may further include silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanide on insulator (S-SiGeOI), silicon germanide on insulator (SiGeOI) or germanium on insulator (GeOI), etc.
[0039] The conductivity type of the substrate 200 is P-type.
[0040] There is a buried layer 210 in the substrate 200, and the conductivity type of the buried layer 210 is N-type, that is, the buried layer 210 is an N-type buried layer 210 (NBL).
[0041] The substrate 200 below the buried layer 210 is connected to the cathode, that is Figure 3 the PSUB terminal shown in
[0042] The NLDMOS further includes: a body region 220, a first well region 260, a source region 221, a base region 222 and a butting structure located on the buried layer 210.
[0043] The conductivity types of both the body region 220 and the first well region 260 are P-type.
[0044] The body region 220 and the first well region 260 are independent of each other, and both the body region 220 and the first well region 260 are located on the top surface of the buried layer 210. Through the inverted buried layer 210, the conduction between the body region 220 and the first well region 260 and the substrate 200 below the buried layer 210 is blocked.
[0045] Both the source region 221 and the base region 222 are located in the body region 220, and the source region 221 and the base region 222 are adjacent. Among them, the source region 221 is connected to the anode, that is Figure 3 the S terminal shown in Figure 3 the B terminal shown in
[0046] The butting structure is located in the first well region 260 and is connected to the cathode, that is Figure 3 the PSUB terminal shown in
[0047] The opposite structure includes a first heavily doped region 261 and a second heavily doped region 262. The first heavily doped region 261 and the second heavily doped region 262 are in close contact along the surface direction of the substrate 200. Among them, the conduction type of the first heavily doped region 261 is P-type, and the conduction type of the second heavily doped region 262 is N-type.
[0048] It should be noted that Figure 3 For the sake of easy understanding and explanation, the P-type region above the buried layer 210 is indicated by blue filling, and the N-type region above the buried layer 210 is indicated by red filling.
[0049] Since the opposite structure is located in the first well region 260 and connected to the cathode, and the opposite structure includes a first heavily doped region 261 and a second heavily doped region 262 in close contact along the surface direction of the substrate 200, therefore, by setting a second heavily doped region 262 in the first well region 260 that can form an opposite structure with the first heavily doped region 261, not only can a PNPN structure be formed based on the first well region 260, the buried layer 210, the body region 220, and the source region 221 as the ESD conduction path of the base, but also a parallel NPNP structure is formed based on the second heavily doped region 262, the first well region 260, the buried layer 210, and the body region 220 as the ESD conduction path of the cathode. Thus, the NLDMOS forms a bidirectional N-P-N-P-N structure with a simple structure, realizing ESD bidirectional protection without setting additional ESD protection devices. Thereby, while taking into account the ESD protection effect, the integration degree is improved.
[0050] Specifically, please refer to Figure 4 , in the NLDMOS of this embodiment, since there is a buried layer 210 in the substrate 200, and the body region 220, the first well region 260, the source region 221, the base region 222, and the opposite structure are distributed. The body region 220 and the first well region 260 are independent of each other. The body region 220 and the first well region 260 are both located on the top surface of the buried layer 210. The source region 221 and the base region 222 are adjacent and both located in the body region 220. The source region 221 is connected to the anode, and the base region 222 is connected to the base. The first well region 260 has a first heavily doped region 261. And the conduction types of the substrate 200, the body region 220, the base region 222, the first well region 260, and the first heavily doped region 261 are P-type, and the conduction types of the buried layer 210 and the source region 221 are N-type. Therefore, the first well region 260, the buried layer 210, and the body region 220 form a PNP structure 11, and the buried layer 110, the body region 120, and the source region 121 form an NPN structure 12. The PNP structure 11 and the NPN structure 12 are connected back to back to form a PNPN structure. The S end is connected in series with a resistor R1 and short-circuited with the base of the PNPN structure (i.e., Figure 4 the B end in
[0051] On this basis, since the second heavily doped region 262 is provided in the first well region 260, the second heavily doped region 262 is in close contact with the first heavily doped region 261 along the surface direction of the substrate 100 to form a butting structure in the first well region 260. Therefore, the second heavily doped region 262, the first well region 260, and the buried layer 210 also form an NPN structure 22, and further, the first well region 260, the buried layer 210, and the body region 220 also form a PNP structure 21. The NPN structure 22 and the PNP structure 21 are connected back-to-back to form an NPNP structure. The second heavily doped region 262 is connected in series with a resistor R2 and shorted to the base (i.e., the first well region 260) of the NPN structure 22, thereby serving as an ESD release path for the PSUB terminal to achieve ESD protection for the cathode.
[0052] Thus, through the butting structure, the first heavily doped region, the first well region, the buried layer, the body region, and the source region are reused multiple times to achieve bidirectional ESD protection. Therefore, while taking into account the ESD protection effect, the integration degree is improved.
[0053] Please continue to refer to Figure 3 , the NLDMOS further includes: an N-type drift region 230 and a drain region 231.
[0054] The drift region 230 is located on the top surface of the buried layer 210 and between the body region 220 and the first well region 260.
[0055] The drain region 231 is located in the drift region 230, and the base region 222 and the drain region 231 are respectively located on both sides of the source region 221.
[0056] Furthermore, the drain region 231 is a heavily doped region.
[0057] Please continue to refer to Figure 3 , the NLDMOS further includes: an N-type second well region 250 and a third heavily doped region 251.
[0058] The second well region 250 is located on the top surface of the buried layer 210 and between the drift region 230 and the first well region 260. In addition, there is a gap between the first well region 260 and the second well region 250.
[0059] In other embodiments, the first well region 260 may also be in contact with the second well region 250.
[0060] The third heavily doped region 251 is located in the second well region 250, and the third heavily doped region 251 and the second heavily doped region 262 are respectively located on both sides of the first heavily doped region 261. Among them, the third heavily doped region 251 is connected to the HVBN terminal, and the HVBN terminal refers to the high voltage n-type burried layer terminal, that is, the high-voltage buried layer 210.
[0061] In addition, the NLDMOS further includes: a first isolation structure 281.
[0062] The first isolation structure 281 is located between the first heavily doped region 261 and the third heavily doped region 251, and the first isolation structure 281 is also located between the first well region 260 and the second well region 250. Moreover, the depths of both the first well region 260 and the second well region 250 are greater than the height of the first isolation structure 281.
[0063] Please continue to refer to Figure 3 , a P-type third well region 240 and a fourth heavily doped region 241 are also distributed in the substrate 200.
[0064] The third well region 240 is located on the top surface of the buried layer 210, and is located between the drift region 230 and the second well region 250.
[0065] The fourth heavily doped region 241 is located within the third well region 240.
[0066] In addition, the NLDMOS further includes: a second isolation structure 282.
[0067] The second isolation structure 282 is located between the third heavily doped region 251 and the fourth heavily doped region 241, and the second isolation structure 282 is also located between the second well region 250 and the third well region 240. Moreover, the depths of both the second well region 250 and the third well region 240 are greater than the height of the second isolation structure 282.
[0068] In addition, the NLDMOS further includes: a third isolation structure 283.
[0069] The third isolation structure 283 is located between the drain region 231 and the fourth heavily doped region 241, and the third isolation structure 283 is also located between the drift region 230 and the third well region 240. Moreover, the depths of both the drift region 230 and the third well region 240 are greater than the height of the third isolation structure 283.
[0070] Please continue to refer to Figure 3 , the NLDMOS may further include: a gate structure 270.
[0071] The gate structure 270 is located on the junction surface between the body region 220 and the drift region 230, and the source region 221 and the drain region 231 are respectively located on both sides of the gate structure 270.
[0072] Furthermore, the gate structure 270 includes a polysilicon gate and a gate oxide layer located between the surface of the body region 220 and the drift region 230 and the polysilicon gate.
[0073] In one embodiment, the NLDMOS is a ring structure.
[0074] Specifically, it may be a concentric annular structure centered on the base region 222, or a racetrack-shaped annular structure, and the present application does not limit this.
[0075] In a specific embodiment, the NLDMOS is an annular structure, the body region 220 is located at the center, the drift region 230 surrounds and encloses the body region 220, the third well region 240 surrounds and encloses the drift region 230, the second well region 250 surrounds and encloses the third well region 240, and the first well region 260 surrounds and encloses the second well region 250.
[0076] Similarly, the source region 221, the drain region 231, the first heavily doped region 261, the second heavily doped region 262, the third heavily doped region 251, the fourth heavily doped region 241, the gate structure 270, the isolation structure, etc. can all be annular structures.
[0077] Correspondingly, the embodiment of the present invention further provides a method for manufacturing an NLDMOS to manufacture the above-mentioned NLDMOS.
[0078] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.
Claims
1. A kind of NLDMOS, characterized in that, Comprising: A substrate having a buried layer therein; A body region, a first well region, a source region, a base region, and an anti-top structure located on the buried layer. The body region and the first well region are independent of each other. The source region and the base region are adjacent and both located in the body region. The source region is connected to the anode, the base region is connected to the base electrode, and the anti-top structure is located in the first well region and connected to the cathode. The anti-top structure includes a first heavily doped region and a second heavily doped region in close contact along the surface direction of the substrate. Among them, the conductive types of the substrate, the body region, the base region, the first well region, and the first heavily doped region are P-type, and the conductive types of the buried layer, the source region, and the second heavily doped region are N-type.
2. The NLDMOS according to claim 1, wherein Further comprising: An N-type drift region and a drain region. The drift region is located on the top surface of the buried layer and between the body region and the first well region. The drain region is a heavily doped region and is located within the drift region.
3. The NLDMOS according to claim 2, wherein Further comprising: A gate structure located on the interface surface between the body region and the drift region, with the source region and the drain region located on both sides of the gate structure respectively.
4. The NLDMOS according to claim 2 or 3, characterized in that, Further comprising: An N-type second well region and a third heavily doped region. The second well region is located on the top surface of the buried layer and between the drift region and the first well region. The third heavily doped region is located within the second well region. The third heavily doped region and the second heavily doped region are located on both sides of the first heavily doped region respectively, and the third heavily doped region is connected to the HVBN terminal.
5. The NLDMOS according to claim 4, wherein Further comprising: A first isolation structure located between the first heavily doped region and the third heavily doped region and between the first well region and the second well region. The depths of the first well region and the second well region are both greater than the height of the first isolation structure.
6. The NLDMOS according to claim 4, wherein Further comprising: A P-type third well region and a fourth heavily doped region. The third well region is located on the top surface of the buried layer and between the drift region and the second well region. The fourth heavily doped region is located within the third well region.
7. The NLDMOS according to claim 6, wherein Further comprising: A second isolation structure located between the third heavily doped region and the fourth heavily doped region and between the second well region and the third well region. The depths of the second well region and the third well region are both greater than the height of the second isolation structure.
8. The NLDMOS according to claim 6, wherein Further comprising: A third isolation structure located between the drain region and the fourth heavily doped region and between the drift region and the third well region. The depths of the drift region and the third well region are both greater than the height of the third isolation structure.
9. The NLDMOS according to any one of claims 1 to 8, characterized in that, The NLDMOS is a ring structure.
10. A method for manufacturing an NLDMOS, characterized in that, Fabricate the NLDMOS according to any one of claims 1 to 9.