A method for improving the heat dissipation performance of AlGaInP red light Micro LED chips

Abstract

The present application discloses a method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip, comprising the following steps: S1, epitaxial structure preparation: substrate and buffer layer processing, etch stop layer and ohmic contact layer growth, and functional layer stacking epitaxy; S2, silicon-based substrate patterning: dielectric layer and metal structure preparation; S3, diamond ohmic contact layer integration: p-type conductive diamond film processing, metal reflection and bonding; S4, substrate removal and n-type structure formation: substrate stripping and n-type contact; S5, back-end process integration: electrode and optical structure preparation; the present application significantly improves the heat dissipation performance of the chip; the series resistance is reduced by 30%-50%; the resistivity of the p / n-type diamond ohmic contact layer is 1-2 orders of magnitude lower than that of ITO; GaAs material absorption and metal shading are avoided, and combined with a microlens array, the red light transmittance is increased from 75% to more than 90%; it is compatible with existing MOCVD, CVD and photolithography processes, and can achieve large-scale production of 2-12 inch wafers, reducing manufacturing costs.

Description

Technical Field

[0001] The present invention relates to the technical field of Micro LED chip preparation, and in particular to a method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip. Background Art

[0002] In AlGaInP red light Micro LED chips, the traditional ITO (indium tin oxide) material as an ohmic contact layer has significant defects: its thermal conductivity is only 10-20 , heat accumulation under high current density causes the chip junction temperature to rise, causing the quantum well efficiency to decrease and the wavelength to drift; at the same time, the transmittance of ITO in the red light band (620-660nm) is about 80%-90%, and an additional metal layer is required to reduce the contact resistance, further introducing the shading effect; diamond material has ultra-high thermal conductivity (2000 The advantages of high red light transmittance (>95%) and doping-adjustable conductivity make it an ideal solution to the above problems; however, the lattice mismatch between diamond and AlGaInP materials (about 12%) and the graphic preparation process of the ohmic contact layer are the key technical difficulties that restrict its practical application. Summary of the Invention

[0003] The purpose of the present invention is to provide a method for improving the heat dissipation performance of AlGaInP red light Micro LED chips. By replacing traditional ITO materials with conductive diamond materials, combining epitaxial structure design with chip process optimization, efficient heat dissipation, low contact resistance and high transmittance can be achieved.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] A method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip, comprising the following steps:

[0006] S1, epitaxial structure preparation:

[0007] Substrate and buffer layer processing: Select n-type GaAs substrate, clean it, and then use MOCVD to grow n-type GaAs buffer layer, controlling the doping concentration, thickness and temperature;

[0008] Etching stop layer and ohmic contact layer growth: epitaxial growth of n-type on the buffer layer Etch the barrier layer and then grow the n-type GaN / InGaN ohmic contact layer by MOCVD;

[0009] Functional layer stacking epitaxy: epitaxially grow n-type AlInP confinement layer, n-type superlattice structure, undoped spacer layer, quantum well structure, p-type spacer layer, p-type confinement layer, p-type superlattice, p-type graded layer and p-type heavily doped layer on the ohmic contact layer in sequence, with precise control of the parameters of each layer;

[0010] S2, silicon substrate patterning:

[0011] Preparation of dielectric layer and metal structure: cleaning silicon wafer / silicon-based CMOS, deposition by PECVD The dielectric layer is photolithographically formed into a Cr metal mask, and after etching, a seed layer is sputtered and Cu metal is electroplated, and then CMP polishing is performed. The height difference between the dielectric layer and the Cu metal and The root mean square roughness of the dielectric layer is measured to ensure that it is within the required range;

[0012] S3, Diamond Ohmic Contact Layer Integration:

[0013] Processing of p-type conductive diamond film: After cleaning the epitaxial wafer, grow the p-type conductive diamond film by CVD / PVD, form the mesa structure by photolithography, etch through the quantum well structure, and use ALE to repair sidewall damage and deposit the passivation layer.

[0014] Metal reflection and bonding: Etching the passivation layer to open holes to the p-type conductive diamond film layer, depositing the metal reflection layer, PECVD preparation Protective layer, backside deposition Controlling warpage of film layers; Hybrid bonding of silicon-based substrates and epitaxial structures;

[0015] S4, substrate removal and n-type structure formation:

[0016] Substrate stripping and n-type contact: etching to remove backside plating Film layer, wet etching removes GaAs substrate and buffer layer, exposes n-type GaN / InGaN layer, grows n-type conductive diamond film layer by CVD / PVD and etches into shape;

[0017] S5, back-end process integration:

[0018] Preparation of electrodes and optical structures: Deposit metal electrodes and form microlens arrays or metasurface structures through photolithography and etching to improve light extraction efficiency.

[0019] In a preferred embodiment, in step S1, the doping source of the n-type GaAs buffer layer is disilane, and the doping concentration is 2.0×10 18 -3.0×10 18 cm -3 , thickness is 100-300nm, and film forming temperature is 620-700℃.

[0020] In a preferred embodiment, in step S1, the n-type In the etching stop layer, x is 0.1-0.2, y is 0.5, and its doping source is disilane with a doping concentration of 1.0×10 17 -1.5×10 18 cm -3 , thickness is 100-300nm, and film forming temperature is 700-780℃.

[0021] In a preferred embodiment, in step S1, the doping source of the n-type GaN / InGaN ohmic contact layer is monosilane, and the doping concentration is 5.0×10 18 -2.0×10 19 cm -3 The thickness is 10-40nm, the film forming temperature is 700-950℃, and the film forming method is low V / III ratio rapid nucleation and high V / III ratio rapid film forming.

[0022] A preferred solution is that in step S2, the The thickness of the dielectric layer is 1-3 μm; the thickness of the Cr metal mask is 50-150 nm.

[0023] A preferred solution is that in step S2, after CMP polishing, The height difference between the dielectric layer and the Cu metal is ≤5nm, The root mean square roughness (Rq) of the dielectric layer is less than 0.2 nm, the test area is 2 μm × 2 μm, and there are no particles larger than 1 μm in the 10 μm × 10 μm area.

[0024] In a preferred embodiment, in step S3, the p-type conductive diamond film layer has a thickness of 10-300 nm and is prepared by chemical vapor deposition (CVD) or physical vapor deposition (PVD), with the doping source being boron. The mobility and carrier concentration are improved by optimizing the boron-carbon ratio, growth temperature, methane concentration, and annealing temperature.

[0025] In a preferred embodiment, in step S3, the etching size of the mesa structure is 1-50 μm in diameter, the pixel spacing is 2-75 μm, and the etching gas is and ; The passivation layer is 、 、 or , with a thickness of 10-100nm.

[0026] In a preferred embodiment, in step S3, the metal reflective layer is one or more of Cr, Au, and Ag, with a thickness of 5-100 nm, and is deposited by sputtering or electron beam evaporation; the bonding accuracy of the hybrid bonding is 50-100 nm, the bonding temperature is 100-400°C, and the pressure is 10-100 KN.

[0027] In a preferred solution, in step S4, the thickness of the n-type conductive diamond film layer is 10-300 nm, and it is prepared by CVD / PVD, the doping source is nitrogen or phosphorus, and the conductivity is improved by optimizing the growth temperature, doping and annealing temperature.

[0028] Due to the application of the above technical solution, the beneficial effects of this application compared with the prior art are:

[0029] 1. Significantly improved heat dissipation performance: The thermal conductivity of diamond is more than 100 times that of ITO. The chip junction temperature is reduced by 15-20°C under high current density (50A / cm²), and the thermally induced brightness decay rate is reduced from 15% to less than 8%.

[0030] 2. Optimization of photoelectric performance: Series resistance is reduced by 30%-50%; the resistivity of the p / n-type diamond ohmic contact layer is 1-2 orders of magnitude lower than that of ITO.

[0031] 3. Light output power increased by more than 25%: By avoiding GaAs material absorption and metal shading, combined with the microlens array, the red light transmittance is increased from 75% to more than 90%.

[0032] 4. Strong process compatibility: Compatible with existing MOCVD, CVD and photolithography processes, it can achieve large-scale production of 2-12 inch wafers and reduce manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 This is a flow chart of a method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip according to the present invention;

[0035] Figure 2 Schematic diagram of the processing of steps S1-1 to S1-4 in the method of embodiment 1 of the present invention;

[0036] Figure 3Schematic diagram of the processing of step S2-1 in the method of embodiment 1 of the present invention;

[0037] Figure 4 Schematic diagram of the processing of step S2-2 in the method of embodiment 1 of the present invention;

[0038] Figure 5 Schematic diagram of the processing of step S2-3 in the method of embodiment 1 of the present invention;

[0039] Figure 6 Schematic diagram of the processing of step S2-4 in the method of embodiment 1 of the present invention;

[0040] Figure 7 Schematic diagram of the processing of steps S3-1 to S3-2 in the method of embodiment 1 of the present invention;

[0041] Figure 8 Schematic diagram of the processing of step S3-3 in the method of embodiment 1 of the present invention;

[0042] Figure 9 Schematic diagram of the processing of step S3-4 in the method of embodiment 1 of the present invention;

[0043] Figure 10 Schematic diagram of the processing of step S3-5 in the method of embodiment 1 of the present invention;

[0044] Figure 11 Schematic diagram of the processing of step S3-6 in the method of embodiment 1 of the present invention;

[0045] Figure 12 Schematic diagram of the processing of step S3-7 in the method of embodiment 1 of the present invention;

[0046] Figure 13 Schematic diagram of the processing of step S4-1 in the method of embodiment 1 of the present invention;

[0047] Figure 14 Schematic diagram of the processing of step S4-2 in the method of embodiment 1 of the present invention;

[0048] Figure 15 Schematic diagram of the processing of step S4-3 in the method of embodiment 1 of the present invention;

[0049] Figure 16 Schematic diagram of the processing of step S5-1 in the method of embodiment 1 of the present invention;

[0050] Among them, 1. GaAs substrate; 2. n-type GaAs buffer layer; 3. n-type Etching stop layer; 4. n-type GaN / InGaN ohmic contact layer; 5. n-type AlInP confinement layer; 6. n-type superlattice structure; 7. Non-doped Spacer layer; 8. Non-doped Graded layer; 9. InGaP / Undoped quantum well structure; 10, p-type Spacer layer; 11, p-type AlInP or confinement layer; 12. p-type superlattice structure; 13. p-type graded layer; 14. p-type heavily doped layer; 15. silicon wafer or silicon-based CMOS; 16. Dielectric layer; 17, Cr metal mask; 18, seed layer; 19, Cu metal; 20, p-type conductive diamond film layer; 21, mask layer; 22, passivation layer; 23, metal reflective layer; 24, Membrane layer; 25. film layer; 26, n-type conductive diamond film layer; 27, electrode metal film layer; 28, microlens array. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0052] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0053] In this application, terms such as "upper," "lower," "left," "right," "front," "back," "top," "bottom," "inner," "outer," "center," "vertical," "horizontal," "transverse," and "longitudinal" indicate positions or locations based on the positions or locations shown in the accompanying drawings. These terms are primarily intended to better describe the present invention and its embodiments and are not intended to limit the devices, elements, or components indicated to having a specific orientation, or to being constructed or operated in a specific orientation.

[0054] Furthermore, some of the above terms may be used to express other meanings besides indicating a position or location. For example, the term "on" may also be used to indicate a dependency or connection in certain circumstances. Those skilled in the art will understand the specific meanings of these terms in the present invention based on the specific circumstances.

[0055] Furthermore, the terms "installed," "disposed," "provided with," "connected," "connected," and "socketed" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral structures; mechanical connections or electrical connections; direct connections or indirect connections through an intermediary; or internal communication between two devices, elements, or components. Those skilled in the art will understand the specific meanings of these terms in the present invention based on specific circumstances.

[0056] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0057] Example 1

[0058] See Figure 1-16 The present application provides a method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip, comprising the following specific steps:

[0059] S1-1, select an n-type doped GaAs substrate 1 (wafer size 2-12 inches, thickness 350-650 μm, single polish / double polish), clean it with acetone, isopropyl alcohol (IPA), and deionized water, and then use an MOCVD system to epitaxially grow an n-type GaAs buffer layer 2 on the substrate, controlling the doping concentration, thickness, and film formation temperature of the buffer layer within the required range; specifically, the doping source of the n-type GaAs buffer layer 2 is disilane, and the doping concentration is 2.0×10 18 -3.0×10 18 cm -3 , thickness is 100-300nm, film forming temperature is 620-700℃; relieve stress between substrate and epitaxial layer, provide uniform conductive path;

[0060] S1-2, epitaxially grow n-type on the above buffer layer at the required temperature Etch the stop layer 3, and determine the value range of x, y and the film thickness range of the etch stop layer; specifically, the n-type In the etching stop layer 3, x is 0.1-0.2, y is 0.5, and its doping source is disilane with a doping concentration of 1.0×10 17 -1.5×10 18 cm -3, thickness is 100-300nm, film forming temperature is 700-780℃; the etching barrier layer provides a selective etching boundary;

[0061] S1-3, placing the substrate in a MOCVD reaction chamber, and epitaxially growing an n-type GaN / InGaN ohmic contact layer 4 at a certain temperature; specifically, the doping source of the n-type GaN / InGaN ohmic contact layer 4 is monosilane, and the doping concentration is 5.0×10 18 -2.0×10 19 cm -3 The thickness is 10-40nm, the film forming temperature is 700-950℃, and the film forming method is low V / III ratio rapid nucleation and high V / III ratio rapid film forming; the n-type GaN / InGaN ohmic contact layer 4 has a large band gap (3.4eV), has very weak absorption of red light, and has a high doping concentration (>10 19 cm -3 ) Reduce contact resistance;

[0062] S1-4, epitaxially growing multiple functional layers on the ohmic contact layer in sequence, including an n-type AlInP confinement layer 5, an n-type superlattice structure 6, an undoped spacer layer, a quantum well structure, a p-type spacer layer, a p-type confinement layer, a p-type superlattice structure 12, a p-type graded layer 13, and a p-type heavily doped layer 14, with precise control over the growth temperature, thickness, doping concentration, and doping source of each layer; specifically;

[0063] n-type AlInP confinement layer 5: Grow a 10-400 nm n-type AlInP confinement layer 5 at 700-780°C with a doping concentration of 1.0×10 17 -1.5×10 18 cm -3 , limiting carrier diffusion and improving injection efficiency;

[0064] n-type superlattice structure 6: growing 5-25 periods of n-type at the same temperature / Superlattice structure, where x1 is 0.1-0.2, y1=0.5,

[0065] x2 is 0.8-0.9, y2=0.5, the single layer thickness is 2.5-25nm, and the doping concentration is 1.0×10 17 -1.5×10 18 cm -3 ; Adjust the band structure and optimize electron transport;

[0066] Undoped spacer layer: grow 40-80nm undoped spacer layer Spacer layer 7, wherein x is 0.6-0.8, y=0.5, and multiple layers of non-doped spacer layer are grown between the non-doped spacer layer and the n-type superlattice structure 6

[0067] Gradient layer 8, x changes gradually from 0.8-0.9 to 0.6-0.8, y=0.5; relieves interface stress and reduces carrier scattering;

[0068] Quantum well structure: 1-5 cycles of InGaP / grown at 710-790℃ Undoped quantum well structure 9, where x is 0.7-0.8, y=0.5, and the InGaP thickness is 2-4 nm. Thickness is 5-8nm; red light emission (wavelength 620-660nm) is achieved through quantum confinement effect;

[0069] P-type spacer layer: 40-80nm p-type grown at 700-780℃ Spacer layer 10, x is 0.8-0.9, y=0.5, doping source is , the doping concentration is 1.0×10 18 -3.0×10 18 cm -3 ;

[0070] P-type confinement layer: 10-400nm p-type AlInP or The limiting layer 11, x is 0.9-0.95, y=0.5, and the doping source is , the doping concentration is 1.0×10 18 -3.0×10 18 cm -3 ;

[0071] P-type superlattice structure 12: p-type with 5-25 periods grown at the same temperature / Superlattice structure, x1 is 0.1-0.2, y1=0.5, x2 is 0.8-0.9, y2=0.5, each layer thickness is 2.5-25nm, and the doping concentration is 1.0×10 18 -3.0×10 18 cm -3 ;

[0072] P-type graded layer 13: 20-60nm p-type layers are grown sequentially at the same temperature Gradient layer (x1 is 0.8-0.9, y1=0.5), 10-20nm p-type Gradient layer (x2 changes from 0.8-0.9 to 0.2-0.3, y2=0.5), 10-20 nm p-type Gradient layer (x3 changes from 0.2-0.3 to 0.01, y3=0.5), the doping concentration of the three layers is 1.0×10 18-3.0×10 18 cm -3 ;

[0073] P-type heavily doped layer 14:

[0074] 20-60nm p-type GaP-1 is grown sequentially at 720-800℃, with a film formation rate of about 1-3μm / h. The doping source is or C, with a doping concentration of 2.0×10 18 -4.0×10 18 cm -3 ;

[0075] 80-120nm p-type GaP-2 is grown at 520-560℃, with a film growth rate of about 6-10μm / h. The doping source is or C, with a doping concentration of 2.0×10 18 -4.0×10 18 cm -3 ;

[0076] 10-30 nm p-type GaP-3 was grown at 520-560 °C, with C as the doping source and a doping concentration of 1.0×10 19 -3.0×10 19 cm -3 ;

[0077] Forming a hole transport channel, ultimately reducing the p-side contact resistance through the p-type GaP-3 heavily doped layer;

[0078] S2-1, select silicon wafer or silicon-based CMOS15 (wafer size 2-12 inches), clean it with acetone, isopropyl alcohol (IPA), and deionized water, and use PECVD equipment to generate a 1-3μm thick layer on its surface. Dielectric layer 16; then A Cr metal mask 17 with a thickness of 50-150 nm is formed on the dielectric layer 16 by photolithography, and then a desmearing process is performed to form a high-precision patterned substrate, providing a flat interface for subsequent bonding.

[0079] S2-2, the silicon wafer or silicon-based CMOS15 after the above treatment is cleaned and dried with acetone, isopropyl alcohol (IPA), and deionized water, and then the ICP etching equipment is used to The dielectric layer 16 is etched, and the etching gas is , ,Ar, , etc., the etching depth is 1-3μm and the width is 1-5μm;

[0080] S2-3, the etched silicon wafer or silicon-based CMOS15 is cleaned and dried with acetone, isopropyl alcohol (IPA), and deionized water, and then sputtered. A seed layer 18 is formed on the dielectric layer 16. The metal of the seed layer 18 is not limited to Ti, Cu, etc., and the thickness of the seed layer 18 is 10-300 nm. Then, Cu metal 19 is deposited on the seed layer 18 using an electroplating device.

[0081] S2-4, right The dielectric layer 16, the Cr metal mask 17, the seed layer 18 and the Cu metal 19 are polished. The height difference between the dielectric layer 16 and the Cu metal 19 and The root mean square roughness of the dielectric layer 16 is measured to ensure that it is within the required range. Specifically, The height difference between the dielectric layer 16 and the Cu metal 19 is ≤5nm, The root mean square roughness (Rq) of the dielectric layer 16 is less than 0.2 nm, the test area is 2 μm × 2 μm, and there are no particles larger than 1 μm in the 10 μm × 10 μm area;

[0082] S3-1, the epitaxial wafer prepared in step S1-4 is cleaned and dried with acetone, isopropyl alcohol (IPA), and deionized water, and a p-type conductive diamond film layer 20 is grown on the surface thereof using a chemical vapor deposition (CVD) or physical vapor deposition (PVD) device, with boron as the doping source. The mobility and carrier concentration are improved by optimizing the boron-carbon ratio (1:50-1:200), growth temperature (700-900°C), methane concentration (5%-15%), and annealing temperature (800-1000°C);

[0083] S3-2, after cleaning with acetone, isopropyl alcohol (IPA), and deionized water and drying, a mask layer 21 is prepared on the p-type conductive diamond film layer 20 through coating, exposure, and development. The material types include PR colloid, The dielectric layer 16, the Cr metal mask 17, etc. are etched by plasma etching, reactive ion etching (RIE) and other etching equipment to etch the p-type conductive diamond film layer 20; then, ICP etching is used to perform mesa etching on the epitaxial wafer, and the etching size is 1-50μm in diameter, the pixel pitch is 2-75μm, and the etching gas is and ; Carve through the quantum well structure;

[0084] S3-3, after cleaning with acetone, isopropyl alcohol (IPA), and deionized water and drying, the ALE equipment is used to repair the damaged layer of the mesa-etched sidewall, and then a passivation layer 22 is deposited on the sidewall. The passivation layer 22 is 、 、 or , with a thickness of 10-100 nm; the passivation layer 22 on the top of the mesa etching is opened by processes such as coating, exposure, development, and ICP etching until the p-type conductive diamond film layer 20 is etched; then a stripping process is performed, and after coating again, exposure, and development, a metal reflective layer 23 is deposited by sputtering or electron beam evaporation process, wherein the metal reflective layer 23 is one or more of Cr, Au, and Ag, with a thickness of 5-100 nm, and a stripping process is performed;

[0085] S3-4, after cleaning with acetone, isopropyl alcohol (IPA), and deionized water and drying, PECVD or ICPCVD equipment is used to generate Protective layer, the film thickness is about 0.5-1μm, and 0.5-1μm is deposited on the back The film layer 24 effectively controls the wafer warpage;

[0086] S3-5, using PECVD or ICPCVD equipment to deposit 0.5-2μm on the surface of the epitaxial wafer The film layer 25 eliminates the abnormal pores in the process, and then is cleaned and dried with acetone, isopropyl alcohol (IPA), and deionized water, and then CMP polishing is performed. The root mean square roughness (Rq) of the film layer 25 is less than 0.2 nm, and the test area is 2 μm × 2 μm;

[0087] S3-6, using electron beam evaporation or sputtering equipment On the film layer 25, after coating, exposure and development, a 50-150nm Cr metal mask 17 is deposited and the film is stripped. After cleaning with acetone, isopropyl alcohol (IPA) and deionized water and drying, an ICP etching device is used to The film layer 25 is etched, and the etching gas is , ,Ar, , The etching depth is 1-2μm and the width is 1-5μm. After cleaning with acetone, isopropyl alcohol (IPA) and deionized water and drying, a seed layer 18 is formed. The metal of the seed layer 18 is not limited to Ti, Cu, etc. The thickness of the seed layer 18 is 10-300nm. Then, Cu metal 19 is deposited by electroplating equipment. CMP equipment is used for The film layer 25, the Cr metal mask 17, the seed layer 18 and the Cu metal 19 are polished. The height difference between the film layer 25 and the Cu metal 19 and The root mean square roughness of the film layer 25 is measured to ensure that it is within the required range. Specifically, The height difference between the film layer 25 and the Cu metal 19 is ≤5nm, The root mean square roughness (Rq) of the film layer 25 is less than 0.2 nm, the test area is 2 μm × 2 μm, and there are no particles larger than 1 μm in the 10 μm × 10 μm area;

[0088] S3-7, hybrid bonding of silicon wafer or silicon-based CMOS 15 and GaAs substrate 1, with a bonding accuracy requirement of 50-100nm. In addition, it is necessary to control and optimize parameters such as temperature (100-400℃) and pressure (10-100KN) to ensure the quality of the bonding interface; the diamond film layer has both high transmittance (red light band > 95%) and low resistivity (<10 -4 ), the reflective layer improves light extraction efficiency, and the bonding process achieves electrical interconnection and mechanical support;

[0089] S4-1, using ICP etching equipment to etch the back of silicon wafer or silicon-based CMOS15 The film layer 24 is removed;

[0090] S4-2, using and The GaAs substrate 1 and the n-type GaAs buffer layer 2 were removed by solution; after cleaning with acetone, isopropyl alcohol (IPA), and deionized water and drying, HCl and The solution is wet-etched until the n-type GaN / InGaN ohmic contact layer 4 is exposed; the highly absorbing GaAs substrate 1 is completely removed;

[0091] S4-3, using chemical vapor deposition (CVD) and physical vapor deposition (PVD) equipment, grow a 10-300 nm n-type conductive diamond film 26 on the n-type GaN / InGaN ohmic contact layer 4. By optimizing process parameters such as growth temperature (600-850°C), nitrogen and phosphorus doping concentration (5.0×10 17 -2.0×10 19 cm -3 ), annealing temperature (700-950°C), etc., can improve the mobility and carrier concentration of the conductive diamond film layer, and form a low-resistance contact between the n-type diamond layer and the n-type GaN / InGaN ohmic contact layer 4, thereby improving its conductive performance; after cleaning with acetone, isopropyl alcohol (IPA), and deionized water and drying, a mask is prepared by coating with glue, exposing, and developing; and the n-type conductive diamond film layer 26 is etched using plasma etching and reactive ion etching (RIE) equipment;

[0092] S5-1, using ICP etching, dry etching the epitaxial wafer, the etching gas is and After removing the relevant masks, the process is cleaned and dried with acetone, isopropyl alcohol (IPA), and deionized water, and then the electrode metal film layer 27 and the microlens array 28 or metasurface structure are deposited through processes such as glue coating, exposure, and development. The microlens array 28 reduces total reflection loss, and combined with the high transmittance of the diamond film layer, the light extraction efficiency (LEE) is increased by 30%-50% compared to traditional solutions, thereby improving the performance of the Micro LED chip.

[0093] Example 2

[0094] This application provides a 4-inch AlGaInP red light Micro LED chip preparation method, including the following steps:

[0095] S1-1, a 4-inch n-type GaAs substrate 1 with a thickness of 350 μm was selected. The surface was double-polished and ultrasonically cleaned in acetone for 10 minutes, isopropyl alcohol (IPA) for 10 minutes, and rinsed with deionized water for 5 minutes. After drying with nitrogen, an n-type GaAs buffer layer 2 was epitaxially grown on the substrate using a MOCVD system. The doping source was disilane with a flow rate of 50 sccm and a doping concentration of 2.5×10 18 cm -3 , with a thickness of 200nm and a film forming temperature of 650℃; it relieves the stress of the substrate and epitaxial layer and provides a uniform conductive path;

[0096] S1-2, epitaxially grow n-type on the above buffer layer at the required temperature Etch the stop layer 3, and determine the value range of x, y and the film thickness range of the etch stop layer; specifically, the n-type In the etching stop layer 3, x is 0.15, y is 0.5, and its doping source is disilane with a flow rate of 30 sccm and a doping concentration of 1.20×10 17 cm -3 , thickness is 200nm, film forming temperature is 750℃; the etch barrier layer provides a selective etching boundary;

[0097] S1-3, placing the substrate in a MOCVD reaction chamber, and epitaxially growing an n-type GaN / InGaN ohmic contact layer 4 at a certain temperature; specifically, the doping source of the n-type GaN / InGaN ohmic contact layer 4 is monosilane, with a flow rate of 80 sccm and a doping concentration of 1.8×10 19 cm -3 , thickness is 25nm, film forming temperature is 850℃, film forming mode is low V / III ratio rapid nucleation and high V / III ratio rapid film forming, specifically, V / III ratio (TMG / ) = 50 (nucleation stage), V / III ratio (TMG / ) = 200 (film formation stage); the n-type GaN / InGaN ohmic contact layer 4 has a large band gap (3.4eV), has very weak absorption of red light, and has a high doping concentration (>10 19 cm -3 ) Reduce contact resistance;

[0098] S1-4, epitaxially growing multiple functional layers on the ohmic contact layer in sequence, including an n-type AlInP confinement layer 5, an n-type superlattice structure 6, an undoped spacer layer, a quantum well structure, a p-type spacer layer, a p-type confinement layer, a p-type superlattice structure 12, a p-type graded layer 13, and a p-type heavily doped layer 14, with precise control over the growth temperature, thickness, doping concentration, and doping source of each layer; specifically:

[0099] n-type AlInP confinement layer 5: A 300 nm thick n-type AlInP confinement layer 5 was grown at 750°C with a doping concentration of 1.5×10 18 cm -3 , limiting carrier diffusion and improving injection efficiency;

[0100] n-type superlattice structure 6: growing 8 periods of n-type at the same temperature / Superlattice structure, where x1 is 0.1, y1=0.5, x2 is 0.85, y2=0.5, the single layer thickness is 10nm, and the doping concentration is 1.0×10 18 cm -3 ; Adjust the band structure and optimize electron transport;

[0101] Undoped spacer layer: Grow 60nm undoped Spacer layer 7, wherein x=0.75, y=0.5, a multilayer non-doped spacer layer is grown between the non-doped spacer layer and the n-type superlattice structure 6 Gradient layer 8, x gradually changes from 0.8 to 0.6, y = 0.5; relieves interface stress and reduces carrier scattering;

[0102] Quantum well structure: 3-period InGaP / Undoped quantum well structure 9, where x is 0.75, y = 0.5, and the InGaP thickness is 3 nm. Thickness is 6nm; red light emission (wavelength 630nm) is achieved through quantum confinement effect;

[0103] P-type spacer layer: 60nm p-type grown at 750℃ Spacer layer 10, x=0.85, y=0.5, doping source is , the doping concentration is 2.0×10 18 cm -3 ;

[0104] P-type confinement layer: 200nm p-type AlInP or The limiting layer 11, x=0.9, y=0.5, the doping source is , the doping concentration is 2.0×10 18 cm -3 ;

[0105] P-type superlattice structure 12: p-type with 8 periods grown at the same temperature / Superlattice structure, x1=0.1, y1=0.5, x2=0.85, y2=0.5, each layer thickness is 10nm, and the doping concentration is 1.0×10 18 cm -3 ;

[0106] P-type graded layer 13: 40nm p-type is grown sequentially at the same temperature Graded layer (x1=0.8, y1=0.5), 10nm p-type Gradient layer (x2 changes from 0.8 to 0.2, y2=0.5), 10nm p-type Gradient layer (x3 changes from 0.2 to 0.01, y3 = 0.5), the doping concentration of the three layers is 2.0×10 18 cm -3 ;

[0107] P-type heavily doped layer 14:

[0108] 40nm p-type GaP-1 was grown sequentially at 750℃ with a film growth rate of about 3μm / h. The doping source was or C, with a doping concentration of 2.0×10 18 cm -3 ;

[0109] 100nm p-type GaP-2 was grown at 550℃ with a film growth rate of about 10μm / h. The doping source was or C, with a doping concentration of 2.0×10 18 cm -3 ;

[0110] 20 nm p-type GaP-3 was grown at 550 °C, with C as the doping source and a doping concentration of 2.0×10 19 cm -3 ;

[0111] Forming a hole transport channel, ultimately reducing the p-side contact resistance through the p-type GaP-3 heavily doped layer;

[0112] S2-1, select 4-inch silicon wafer or silicon-based CMOS15, clean it with acetone, isopropyl alcohol (IPA), and deionized water, and use PECVD equipment to generate a 2μm thick layer on its surface. Dielectric layer 16; then A Cr metal mask 17 with a thickness of 80 nm is formed on the dielectric layer 16 by photolithography, and then a resist stripping process is performed to form a high-precision patterned substrate, providing a flat interface for subsequent bonding.

[0113] S2-2, the silicon wafer or silicon-based CMOS15 after the above treatment is cleaned and dried with acetone, isopropyl alcohol (IPA), and deionized water, and then the ICP etching equipment is used to The dielectric layer 16 is etched, and the etching gas is , the etching depth is 2μm and the width is 3μm;

[0114] S2-3, the etched silicon wafer or silicon-based CMOS15 is cleaned and dried with acetone, isopropyl alcohol (IPA), and deionized water, and then sputtered. A seed layer 18 is formed on the dielectric layer 16. The metal of the seed layer 18 is not limited to Ti, Cu, etc., and the film thickness of the seed layer 18 is 100nm. Subsequently, Cu metal 19 is deposited on the seed layer 18 using an electroplating device. The electroplating thickness is 5μm and the current density is 20mA / cm².

[0115] S2-4, right The dielectric layer 16, the Cr metal mask 17, the seed layer 18 and the Cu metal 19 are polished. The height difference between the dielectric layer 16 and the Cu metal 19 and The root mean square roughness of the dielectric layer 16 is measured to ensure that it is within the required range. Specifically, The height difference between the dielectric layer 16 and the Cu metal 19 is 2nm. The root mean square roughness Rq of the dielectric layer 16 is 0.15 nm, the test area is 2 μm × 2 μm, and there are no particles larger than 1 μm in the 10 μm × 10 μm area;

[0116] S3-1, the epitaxial wafer prepared in step S1-4 is cleaned and dried with acetone, isopropyl alcohol (IPA), and deionized water, and a p-type conductive diamond film layer 20 is grown on its surface using a chemical vapor deposition (CVD) or physical vapor deposition (PVD) device, with boron as the doping source, by optimizing the boron-carbon ratio of 1:100 ( / ), growth temperature (800℃), methane concentration (10%) and annealing temperature (900℃) to improve mobility and carrier concentration;

[0117] S3-2, after cleaning with acetone, isopropyl alcohol (IPA), and deionized water and drying, a mask layer 21 is prepared on the p-type conductive diamond film layer 20 through coating, exposure, and development. The material types include PR colloid, The dielectric layer 16, the Cr metal mask 17, etc. are etched by plasma etching, reactive ion etching (RIE) and other etching equipment to etch the p-type conductive diamond film layer 20; then, ICP etching is used to perform mesa etching on the epitaxial wafer, the etching size is 10 μm in diameter, the pixel pitch is 35 μm, and the etching gas is and ; Carve through the quantum well structure;

[0118] S3-3, after cleaning with acetone, isopropyl alcohol (IPA), and deionized water and drying, the ALE equipment is used to repair the damaged layer of the mesa-etched sidewall, and then a passivation layer 22 is deposited on the sidewall. The passivation layer 22 is , with a thickness of 20nm; the passivation layer 22 on the top of the mesa etching is opened by processes such as coating, exposure, development and ICP etching until the p-type conductive diamond film layer 20 is etched; then a stripping process is performed, and after coating again, exposure and development, a metal reflective layer 23 is deposited by sputtering or electron beam evaporation process. The metal reflective layer 23 is Cr and Au, with a thickness of 30nm, and the stripping process is performed;

[0119] S3-4, after cleaning with acetone, isopropyl alcohol (IPA), and deionized water and drying, PECVD or ICPCVD equipment is used to generate The protective layer has a film thickness of about 0.5 μm and a 0.5 μm film is deposited on the back. The film layer 24 effectively controls the wafer warpage;

[0120] S3-5, using PECVD or ICPCVD equipment to deposit 1μm on the surface of the epitaxial wafer The film layer 25 eliminates the abnormal pores in the process, and then is cleaned and dried with acetone, isopropyl alcohol (IPA), and deionized water, and then CMP polishing is performed. The root mean square roughness of the film layer 25 is Rq = 0.15 nm, and the test area is 2 μm × 2 μm;

[0121] S3-6, using electron beam evaporation or sputtering equipment On the film layer 25, a 100nm Cr metal mask 17 is deposited after coating, exposure, and development, and then the film is stripped. After cleaning with acetone, isopropyl alcohol (IPA), and deionized water, the film is then dried using an ICP etching device. The film layer 25 is etched, and the etching gas is The etching depth is 2μm and the width is 5μm. After cleaning with acetone, isopropyl alcohol (IPA) and deionized water and drying, the seed layer 18 is formed. The metal of the seed layer 18 is not limited to Ti, Cu, etc. The thickness of the seed layer 18 is 200nm. Then, the Cu metal 19 is deposited by electroplating equipment. The CMP equipment is used for The film layer 25, the Cr metal mask 17, the seed layer 18 and the Cu metal 19 are polished. The height difference between the film layer 25 and the Cu metal 19 and The root mean square roughness of the film layer 25 is measured to ensure that it is within the required range. Specifically, The height difference between the film layer 25 and the Cu metal 19 is 2nm. The root mean square roughness Rq of the film layer 25 is 0.15 nm, the test area is 2 μm × 2 μm, and there are no particles larger than 1 μm in the 10 μm × 10 μm area;

[0122] S3-7, hybrid bonding of silicon wafer or silicon-based CMOS 15 and GaAs substrate 1, with a bonding accuracy requirement of 80nm. In addition, it is necessary to control and optimize parameters such as temperature (300℃) and pressure (80KN) to ensure the quality of the bonding interface; the diamond film layer has both high transmittance (red light band > 95%) and low resistivity (<10 -4 ), the reflective layer improves light extraction efficiency, and the bonding process achieves electrical interconnection and mechanical support;

[0123] S4-1, using ICP etching equipment to etch the back of silicon wafer or silicon-based CMOS15 The film layer 24 is removed;

[0124] S4-2, using a volume ratio of 7:1 and The GaAs substrate 1 and the n-type GaAs buffer layer 2 were removed by the solution at an etching rate of 6 μm / min. After cleaning with acetone, isopropyl alcohol (IPA), and deionized water, the substrate was dried by HCl and The solution is wet-etched until the n-type GaN / InGaN ohmic contact layer 4 is exposed; the highly absorbing GaAs substrate 1 is completely removed;

[0125] In step S4-3, a 150 nm thick n-type conductive diamond film 26 is grown on the n-type GaN / InGaN ohmic contact layer 4 using chemical vapor deposition (CVD) and physical vapor deposition (PVD) equipment. By optimizing process parameters such as growth temperature (650°C), nitrogen and phosphorus doping concentrations (1.0×10 19 cm -3), annealing temperature (800°C), etc., can improve the mobility and carrier concentration of the conductive diamond film layer, and form a low-resistance contact between the n-type diamond layer and the n-type GaN / InGaN ohmic contact layer 4, thereby improving its conductive performance; after cleaning with acetone, isopropyl alcohol (IPA), and deionized water and drying, a mask is prepared by coating with glue, exposing, and developing; and the n-type conductive diamond film layer 26 is etched using plasma etching and reactive ion etching (RIE) equipment;

[0126] S5-1, using ICP etching, dry etching the epitaxial wafer, the etching gas is and After removing the relevant masks, the process is cleaned and dried with acetone, isopropyl alcohol (IPA), and deionized water, and then the electrode metal film layer 27 and the microlens array 28 or metasurface structure are deposited through processes such as glue coating, exposure, and development. The microlens array 28 reduces total reflection loss, and combined with the high transmittance of the diamond film layer, the light extraction efficiency (LEE) is increased by 45% compared to traditional solutions, thereby improving the performance of the Micro LED chip.

[0127] The Micro LED chips produced through the above steps and the chips with traditional ITO solutions were tested for series resistance, light output power, junction temperature, and light extraction efficiency. The specific testing methods are as follows:

[0128] 1. Series resistance test

[0129] 1. Test principle: By measuring the voltage drop of the chip at different current densities, the series resistance is calculated using Ohm's law. The formula is: ,in is the threshold voltage, and I is the injected current.

[0130] 2. Test equipment: semiconductor parameter analyzer (such as Keysight B1500A), probe station (accuracy ±1μm), constant temperature sample stage (temperature control ±0.5℃).

[0131] 3. Test steps:

[0132] The chip was fixed on the probe station, and a tungsten probe (25 μm in diameter) was used to contact the p / n electrodes;

[0133] Apply forward bias (0-5V), scan current density range: 10-1000A / cm²;

[0134] Current-voltage (IV) curves were recorded, and the series resistance was calculated by linear fitting the slope of the curve.

[0135] Test environment: room temperature (25°C), nitrogen atmosphere (to avoid oxidation).

[0136] 4. Data Processing

[0137] Excluding the influence of the built-in electric field generated by quantum well luminescence, the linear region with current density > 100A / cm² was used for fitting.

[0138] Unit conversion: Chip area × resistance value = (Specific contact resistivity).

[0139] 2. Optical output power test

[0140] 1. Test Principle: The chip's luminous power is measured by a photodetector, and the luminous efficiency is calculated based on the injected current. The detector's spectral response needs to be calibrated (red light band 620-660nm).

[0141] 2. Test equipment: spectrometer (such as Ocean Optics HR4000), integrating sphere (diameter 15 cm, reflectivity > 99%), current source (accuracy ±0.1%).

[0142] 3. Test steps:

[0143] Place the chip in the center of the integrating sphere, touch the probe to the electrode, and inject a current of 10μA (corresponding to a current density of approximately 100A / cm²);

[0144] The spectrometer has a scanning wavelength range of 600-700 nm, a resolution of 1 nm, and an integration time of 100 ms;

[0145] Deduct the dark current background (the noise value when the light source is turned off) and calculate the integrated value of the optical power in the 620-660nm band;

[0146] The test was repeated three times and the average value was taken to reduce random errors.

[0147] 4. Calibration method:

[0148] The integrating sphere response was calibrated using a standard red LED (NIST traceable, wavelength 630 nm, power 10 μW).

[0149] The spectrometer needs to be calibrated regularly using a tungsten-halogen lamp to calibrate the light intensity-wavelength curve.

[0150] Junction temperature test

[0151] 1. Test principle: Use an infrared thermal imager to measure the chip surface temperature, and use the thermal resistance model to calculate the junction temperature. The formula is: ,in is the surface temperature, is the thermal resistance, and P is the power consumption.

[0152] 2. Test equipment: infrared thermal imager (resolution 640×512, wavelength range 7-14μm), DC power supply (power accuracy ±0.5%), heat sink (temperature control ±1°C).

[0153] 3. Test steps:

[0154] The chip was fixed to a heat sink (temperature 25°C) and a continuous current density of 1000A / cm² (close to actual operating conditions) was applied.

[0155] Wait 30 minutes until thermal equilibrium (temperature fluctuation < 0.5°C) and use a thermal imager to capture the temperature distribution on the chip surface.

[0156] Select the center pixel of the luminous area (spatial resolution < 10 μm) to record the temperature ;

[0157] Obtaining thermal resistance through ANSYS simulation , calculate the junction temperature .

[0158] 4. Error correction:

[0159] The thermal imager needs to be calibrated for emissivity (diamond surface emissivity is 0.7, GaAs emissivity is 0.3);

[0160] The test was carried out in a dark room to exclude interference from ambient light.

[0161] 4. Light Extraction Efficiency (LEE) Test

[0162] 1. Test Principle: Light extraction efficiency is defined as the ratio of the chip's output light power to its internal luminous power. It is measured indirectly using the following methods:

[0163] Integrating sphere method to measure actual optical power ;

[0164] Electroluminescence spectroscopy (EL) method is used to measure the internal quantum efficiency (IQE) and calculate the internal luminous power based on the injected current. ;

[0165] LEE= / ×100%.

[0166] 2. Test equipment: electroluminescence spectrometer (EL, resolution 0.1nm), fluorescence quantum efficiency measurement system (such as Horiba FluoroMax).

[0167] 3. Test steps

[0168] Step 1, EL spectrum and IQE calculation:

[0169] Apply a current density of 100 A / cm² and collect EL spectra (620-660 nm);

[0170] By formula Calculate, where hv is the photon energy and e is the electron charge;

[0171] Step 2, LEE calculation:

[0172] Integrating sphere measurement =15μW (current 10μA);

[0173] Assuming IQE=80%, then ( is the radiative recombination efficiency, which is taken as 0.9);

[0174] Calculate LEE.

[0175] The Micro LED chip produced in Example 2 and a traditional ITO chip (a 4-inch GaAs LED epitaxial chip purchased from Jiangxi MTC Semiconductor Co., Ltd.) were tested using the above test method, and the following comparative information was obtained:

[0176] The performance test comparison table is as follows:

[0177]

[0178] The beneficial effects of this application compared with the prior art are:

[0179] 1. Significantly improved heat dissipation performance: The thermal conductivity of diamond is more than 100 times that of ITO. The chip junction temperature is reduced by 15-20°C under high current density (50A / cm²), and the thermally induced brightness decay rate is reduced from 15% to less than 8%.

[0180] 2. Optimization of photoelectric performance: Series resistance is reduced by 30%-50%: The resistivity of the p / n-type diamond ohmic contact layer is 1-2 orders of magnitude lower than that of ITO.

[0181] 3. Light output power increased by more than 25%: By avoiding GaAs material absorption and metal shading, combined with the microlens array, the red light transmittance is increased from 75% to more than 90%.

[0182] 4. Strong process compatibility: Compatible with existing MOCVD, CVD and photolithography processes, it can achieve large-scale production of 2-12 inch wafers and reduce manufacturing costs.

[0183] Finally, it should be noted that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or make equivalent replacements for some of the technical features therein. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip, characterized in that: The steps include: S1, epitaxial structure preparation: Substrate and buffer layer processing: Select n-type GaAs substrate, clean it, and then use MOCVD to grow n-type GaAs buffer layer, controlling the doping concentration, thickness and temperature; Etching stop layer and ohmic contact layer growth: epitaxial growth of n-type on the buffer layer Etch the barrier layer and then grow the n-type GaN / InGaN ohmic contact layer by MOCVD; Functional layer stacking epitaxy: epitaxially grow n-type AlInP confinement layer, n-type superlattice structure, undoped spacer layer, quantum well structure, p-type spacer layer, p-type confinement layer, p-type superlattice, p-type graded layer and p-type heavily doped layer on the ohmic contact layer in sequence, with precise control of the parameters of each layer; S2, silicon substrate patterning: Preparation of dielectric layer and metal structure: cleaning silicon wafer / silicon-based CMOS, deposition by PECVD The dielectric layer is photolithographically formed into a Cr metal mask, and after etching, a seed layer is sputtered and Cu metal is electroplated, and then CMP polishing is performed. The height difference between the dielectric layer and the Cu metal and The root mean square roughness of the dielectric layer is measured to ensure that it is within the required range; S3, Diamond Ohmic Contact Layer Integration: Processing of p-type conductive diamond film: After cleaning the epitaxial wafer, grow the p-type conductive diamond film by CVD / PVD, form the mesa structure by photolithography, etch through the quantum well structure, and use ALE to repair sidewall damage and deposit the passivation layer. Metal reflection and bonding: Etching the passivation layer to open holes to the p-type conductive diamond film layer, depositing the metal reflection layer, PECVD preparation Protective layer, backside deposition Controlling warpage of film layers; Hybrid bonding of silicon-based substrates and epitaxial structures; S4, substrate removal and n-type structure formation: Substrate stripping and n-type contact: etching to remove back plating Film layer, wet etching removes GaAs substrate and buffer layer, exposes n-type GaN / InGaN layer, grows n-type conductive diamond film layer by CVD / PVD and etches into shape; S5, back-end process integration: Preparation of electrodes and optical structures: Deposit metal electrodes and form microlens arrays or metasurface structures through photolithography and etching to improve light extraction efficiency.

2. The method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip according to claim 1, characterized in that: In step S1, the doping source of the n-type GaAs buffer layer is disilane, and the doping concentration is 2.0×10 18 -3.0×10 18 cm -3 , thickness is 100-300nm, and film forming temperature is 620-700℃.

3. The method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip according to claim 1, characterized in that: In step S1, the n-type In the etching stop layer, x is 0.1-0.2, y is 0.5, and its doping source is disilane with a doping concentration of 1.0×10 17 -1.5×10 18 cm -3 , thickness is 100-300nm, and film forming temperature is 700-780℃.

4. The method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip according to claim 1, wherein: In step S1, the doping source of the n-type GaN / InGaN ohmic contact layer is monosilane, and the doping concentration is 5.0×10 18 -2.0×10 19 cm -3 The thickness is 10-40nm, the film forming temperature is 700-950℃, and the film forming method is low V / III ratio rapid nucleation and high V / III ratio rapid film forming.

5. The method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip according to claim 1, wherein: In step S2, the The thickness of the dielectric layer is 1-3 μm; the thickness of the Cr metal mask is 50-150 nm.

6. The method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip according to claim 1, wherein: In step S2, after CMP polishing, The height difference between the dielectric layer and the Cu metal is ≤5nm, The root mean square roughness (Rq) of the dielectric layer is less than 0.2 nm, the test area is 2 μm × 2 μm, and there are no particles larger than 1 μm in the 10 μm × 10 μm area.

7. The method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip according to claim 1, wherein: In step S3, the p-type conductive diamond film layer has a thickness of 10-300 nm and is prepared by chemical vapor deposition (CVD) or physical vapor deposition (PVD). The doping source is boron. The mobility and carrier concentration are improved by optimizing the boron-carbon ratio, growth temperature, methane concentration and annealing temperature.

8. The method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip according to claim 1, wherein: In step S3, the etching size of the mesa structure is 1-50 μm in diameter, 2-75 μm in pixel pitch, and the etching gas is and ; The passivation layer is 、 、 or , with a thickness of 10-100nm.

9. The method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip according to claim 1, wherein: In step S3, the metal reflective layer is one or more of Cr, Au, and Ag, with a thickness of 5-100 nm, and is deposited by sputtering or electron beam evaporation process; the bonding accuracy of the hybrid bonding is 50-100 nm, the bonding temperature is 100-400° C., and the pressure is 10-100 KN.

10. The method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip according to claim 1, wherein: In step S4, the n-type conductive diamond film layer has a thickness of 10-300 nm and is prepared by CVD / PVD, with nitrogen or phosphorus as the doping source, and the conductive performance is improved by optimizing the growth temperature, doping and annealing temperature.

Images