Self-aligned bottom pinning SOT-MRAM process

Abstract

The invention discloses a self-alignment bottom pinning SOT-MRAM process, and solves the technical problem of inaccurate overlay of an MTJ unit on a bottom electrode in an existing bottom pinning SOT-MRAM. The method comprises the following steps of: firstly, preparing a nano strip-shaped bottom electrode on the surface of a bottom pinning magnetic tunnel junction full-film layer sample by adopting a positive photoresist photoetching process, and depositing an insulating medium in situ to protect a side wall; preparing a top electrode by using a negative photoresist process in a direction which is vertically crossed with the bottom electrode, and growing a top electrode material through magnetron sputtering, so that an MTJ pattern is naturally formed in a crossed region; selectively covering the through holes according to the type of a hard mask material and depositing a hard mask; etching along the hard mask and growing an insulating medium to protect the side wall; and finally completing the growth of the external electrode material. According to the invention, through the vertical crossing self-alignment process, the problem of overlay deviation of the nano-sized MTJ is effectively solved, the storage density of the SOT-MRAM is increased, and the power consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the field of micro-nano processing technology, and particularly to a self-aligned bottom pinned SOT-MRAM process. Background Art

[0002] With the rapid development of information technology, data storage technology has become a core part of the modern information technology field. As a non-volatile storage technology, magnetic random access memory (MRAM) has attracted much attention due to its unique storage mechanism - using two different magnetization directions of magnetic materials to represent binary data "0" and "1". Compared with traditional static random access memory (SRAM) and dynamic random access memory (DRAM), MRAM has significant advantages such as low power consumption, fast read and write speeds, and long-term data retention ability, and is particularly suitable for fields with extremely high requirements for data reliability, such as Internet of Things devices, mobile electronic products, automotive electronics, and aerospace.

[0003] Spin-orbit torque magnetic random access memory (SOT-MRAM), as one of the main implementation forms of MRAM technology, its characteristic of separating read and write avoids the risk of breakdown of the MgO barrier layer and improves the durability of the device. The write speed of SOT-MRAM can reach the picosecond level, and the write power consumption can be reduced to the femtojoule level, with broad application prospects.

[0004] The core device of MRAM is the magnetic tunnel junction (MTJ). The MTJ of traditional SOT-MRAM has a bottom electrode top pinned structure, that is, substrate / seed layer / bottom electrode / free layer / barrier layer / fixed layer / synthetic antiferromagnetic layer (SAF layer) / capping layer. This structure has several bottlenecks: First, it is difficult to ensure the quality of the SAF layer in the multi-layer film grown by magnetron sputtering, and element diffusion will occur during the annealing process, resulting in pinning failure; second, in the manufacturing process, dry etching is extremely prone to cause a backsputtering process, leading to a short circuit in the barrier layer, especially in nano-sized MTJs; in industrial mass production, there are challenges in the dry etching stop process using the endpoint detection method, and it is difficult to ensure that the etching stop endpoint of each MTJ precisely and consistently stops at the bottom electrode layer. This inconsistency will have a negative impact on the write performance of the device, and further lead to a decrease in the mass production yield. The 2023 IEDM conference reported a new type of SOT device with a top electrode bottom pinned structure (hereinafter simply referred to as bottom pinned SOT-MRAM), that is, substrate / seed layer (bottom electrode) / synthetic antiferromagnetic layer (SAF layer) / fixed layer / barrier layer / free layer / top electrode / protective layer. This device structure can solve the technical bottlenecks of traditional bottom electrode top pinned SOT-MRAM and has received extensive attention. However, as the MTJ size shrinks, the lithography overlay alignment difficulty of bottom pinned SOT-MRAM increases significantly, which will lead to a decrease in the device yield.

[0005] To address this issue, the present invention proposes a vertical cross self-aligned bottom pinned SOT-MRAM process. By performing lithography twice on the lateral and longitudinal nanowires to define the cross region as the magnetic tunnel junction (MTJ) pattern, the self-alignment effect is achieved, solving the overlay problem of the bottom pinned SOT-MRAM. Summary of the Invention

[0006] The object of the present invention is to provide a self-aligned bottom pinned SOT-MRAM process to solve the technical problem of misalignment of the MTJ unit on the bottom electrode in the existing bottom pinned SOT-MRAM.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] A self-aligned bottom pinned SOT-MRAM process provided by the present invention includes the following steps:

[0009] S1: On the surface of the bottom pinned magnetic tunnel junction full film layer sample, a bottom electrode is prepared by using a positive photoresist lithography process. Subsequently, an insulating medium is deposited in-situ to protect the sidewalls of the bottom electrode. After stripping the positive photoresist, the top electrode is exposed, and the surface is planarized.

[0010] S2: In the direction perpendicular to the bottom electrode, the top electrode pattern area is exposed by using a negative photoresist process, and the top electrode material is grown by magnetron sputtering, so that the magnetic tunnel junction pattern is formed in the vertical cross region of the top electrode and the bottom electrode.

[0011] S3: Perform the following operations according to the selected type of hard mask material:

[0012] If an insulating hard mask material is selected, on the basis of retaining the negative photoresist, the through holes at both ends of the top electrode are covered by using a positive photoresist process. After depositing the insulating hard mask material, the negative photoresist and the positive photoresist are stripped, and the top electrode through holes and the bottom electrode pattern are exposed.

[0013] If a conductive hard mask material is selected, on the basis of retaining the negative photoresist, the conductive hard mask material is directly deposited.

[0014] S4: Use a positive photoresist to cover the through holes at both ends of the top electrode and the bottom electrode. Based on the hard mask pattern, the MTJ sidewalls are etched to expose them. An insulating medium is deposited in-situ to protect the sidewalls. After stripping the positive photoresist, the through holes are exposed.

[0015] S5: Use a negative photoresist process to expose the through holes of the top electrode and the bottom electrode, and grow the external electrode material.

[0016] Furthermore, the structure of the bottom pinned magnetic tunnel junction full film layer sample is: substrate / seed layer / synthetic antiferromagnetic layer / fixed layer / barrier layer / free layer / top electrode / cover layer.

[0017] Further, in step S1, the pattern of the bottom electrode is nano-strip-shaped, the width of the nano-strip is consistent with the width of the MTJ unit, and surface planarization is achieved through chemical mechanical polishing.

[0018] Further, in step S2, the top electrode pattern is prepared by a negative photoresist process, and is a nano-strip that intersects the bottom electrode perpendicularly. The width of the top electrode is the same as that of the bottom electrode, and the top electrode material is selected from materials that can provide spin current or orbital current.

[0019] Further, in step S3, the insulating hard mask material includes at least one of SiO2 and SiN x The conductive hard mask material is a metal conductive hard mask material, including at least one of Ru, Ta, Pt, Cr, W, and TiN.

[0020] Further, in step S3, if the insulating hard mask material is grown, the through holes of the top electrode are covered in advance by a positive photoresist process without precise alignment. The length of the through holes is reserved for 3 - 5 μm, and the width of the through holes is equal to the width of the top electrode pattern. If the conductive hard mask material is grown, the through holes of the top electrode do not need to be covered.

[0021] Further, in step S4, the through holes of the top electrode and the bottom electrode are covered by a positive photoresist process before etching. The length of the through holes is reserved for 3 - 5 μm without precise alignment.

[0022] Further, in step S4, only the barrier layer on the sidewall of the MTJ is exposed during etching, and no etching stop process is required.

[0023] Further, the capping layer material is selected from a single layer of Pt, Ta, Ru, W, Cr or a double-layer structure of Cr / Pt, Ru / Pt, Ru / Gd, and the thickness is 5 - 8 nm.

[0024] Further, the protective material for the sidewall is selected from Si3N4, SiO2, Al2O3, Ta2O5, TiN or SiON, and is formed by physical vapor deposition or plasma enhanced chemical vapor deposition process.

[0025] Based on the above technical solutions, the embodiments of the present invention can at least produce the following technical effects:

[0026] (1) The self-aligned bottom pinned SOT-MRAM process provided by the present invention adopts two vertical cross-alignments, so that the MTJ pattern is naturally formed at the intersection, solving the problem of device failure caused by misalignment in the bottom pinned SOT-MRAM. In addition, the present invention can reduce the size of the SOT electrode to be the same as that of the MTJ, and its accuracy can be close to the exposure limit of the lithography machine, thereby greatly reducing the write current of the device.

[0027] (2) The self-aligned bottom-pinned SOT-MRAM process provided by the present invention adopts a negative photoresist process, and directly grows a top electrode on the top of the MTJ. This step, as the second step of the vertical cross-lithography process, not only defines the shape of the MTJ, but also solves the connection problem between the magnetic tunnel junction and the external electrode in the traditional SOT-MRAM device process.

[0028] (3) The self-aligned bottom-pinned SOT-MRAM process provided by the present invention adopts a positive photoresist process to effectively protect the through-holes at both ends of the top and bottom electrodes. This process ensures that the through-holes are not damaged during the subsequent etching process and the in-situ deposition process of the insulating medium, thereby maintaining their integrity. Finally, these protected through-holes can be used to reliably connect to the external circuit to achieve the conduction of electrical signals. Description of the Drawings

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0030] Figure 1 It is a flowchart of an embodiment of the present invention;

[0031] Figure 2 It is a top view of step S1 of the present invention;

[0032] Figure 3 It is a top view of step S2 of the present invention;

[0033] Figure 4 It is a top view of step S3 of the present invention;

[0034] Figure 5 It is a top view of step S4 of the present invention;

[0035] Figure 6 It is a top view of step S5 of the present invention;

[0036] Figure 7 It is a cross-sectional view of step S1 of the present invention;

[0037] Figure 8 It is a cross-sectional view of step S2 of the present invention;

[0038] Figure 9 It is a cross-sectional view of step S3 of the present invention;

[0039] Figure 10 It is a cross-sectional view of step S4 of the present invention;

[0040] Figure 11It is a sectional view of step S5 of the present invention;

[0041] In the figure: 1. Sample surface; 2. Positive photoresist; 3. Insulating medium; 4. Negative photoresist; 5. Top electrode; 6. Metal hard mask; 7. Etched sample surface; 8. Outer electrode. Specific implementation manner

[0042] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0043] The object of the present invention is achieved through the following technical solutions:

[0044] A self-aligned bottom pinned SOT-MRAM process, comprising the following steps:

[0045] S1: On the sample surface, a bottom electrode nanobar is prepared by a positive photoresist lithography process. Subsequently, an insulating medium is deposited in situ to protect the sidewalls. After the positive photoresist is peeled off, the top electrode is exposed, and then the surface is planarized.

[0046] In a preferred implementation manner, the sample is a bottom pinned magnetic tunnel junction full film layer sample, that is, its structure is substrate / seeding layer (bottom electrode) / synthetic antiferromagnetic layer (SAF layer) / fixed layer / barrier layer / free layer / top electrode / cover layer, and the top electrode layer provides spin current or orbital current for data writing.

[0047] In a preferred implementation manner, in step S1, the bottom electrode is prepared by a positive photoresist process, including four processes of spin coating, lithography, development, and etching; after the sample is coated with an insulating medium by an evaporation process and then peeled off, after the positive photoresist is peeled off, the surface of the bottom electrode is exposed and the sidewalls are protected.

[0048] S2: In the direction perpendicular to the intersection of the bottom electrode, the top electrode pattern area is exposed by a negative photoresist process, and then the top electrode material is grown by a magnetron sputtering technique. The intersection of the top and bottom electrodes perpendicularly forms the pattern of the MTJ;

[0049] S3: On the premise of retaining the photoresist in the previous step, if insulating hard mask materials such as SiO2 and SiNx are selected, first use the positive photoresist process to cover the vias at both ends of the top electrode, then grow the hard mask material, and then strip the negative photoresist and positive photoresist as a whole to expose the top electrode vias and the bottom electrode pattern; if conductive hard mask materials such as Ru and Ta are selected, directly grow the hard mask material.

[0050] In a preferred embodiment, in step S2, the pattern of the top electrode is reserved by using the negative photoresist process, including spin coating, lithography, and development; the nanobar region after development intersects and is perpendicular to the bottom electrode. Subsequently, the top electrode material is grown by magnetron sputtering, and the negative photoresist does not need to be stripped in this step.

[0051] In a preferred embodiment, in step S3, the positive photoresist process covers three key steps: spin coating, lithography, and development. Since the negative photoresist in step S2 has been subjected to high-temperature baking, the negative photoresist will not be etched during the development process in step S3. Subsequently, after the growth of the hard mask material is completed, the negative photoresist and positive photoresist (if any) are stripped, finally leaving the required top electrode pattern and exposing the top electrode vias.

[0052] In a preferred embodiment, in step S3, the cross-sectional area between the bottom electrode and the top electrode directly determines the size of the MTJ unit. Since the self-alignment technology is adopted and the overlay between the MTJ unit and the write electrode is not required, the size of the prepared MTJ can approach the accuracy limit of the lithography machine.

[0053] S4: Use positive photoresist to cover the vias at both ends of the top and bottom electrodes; etch to expose the MTJ sidewalls based on the hard mask pattern, in-situ deposit an insulating medium to protect the sidewalls, and finally strip the positive photoresist to expose the vias;

[0054] In a preferred embodiment, in step S4, the positive photoresist process used before etching the top electrode pattern includes spin coating, lithography, and development.

[0055] S5: Finally, use the negative photoresist process to expose the vias of the top and bottom electrodes and grow the external electrode material.

[0056] In a preferred embodiment, the capping layer material of the bottom-pinned SOT-MRAM all-film layer is preferably a single-layer material of platinum (Pt), tantalum (Ta), ruthenium (Ru), tungsten (W), chromium (Cr), or a bilayer material such as Cr / Pt, Ru / Pt, Ru / Gd, with a thickness of 5-8 nm to prevent the all-film layer from being oxidized.

[0057] In a preferred embodiment, the sidewall protection material is preferably silicon nitride (Si3N4), silicon dioxide (SiO2), aluminum oxide (Al2O3), tantalum pentoxide (Ta2O5), titanium nitride (TiN), silicon oxynitride (SiON), and an appropriate deposition process such as physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), etc. can be used to form the sidewall protection layer.

[0058] In a preferred embodiment, the planarization process can employ any suitable planarization process well-known in the semiconductor industry, including chemical mechanical polishing (CMP), electrochemical mechanical polishing (ECMP), or ion milling.

[0059] In a preferred embodiment, in the above-described stripping process, organic stripping solutions such as acetone, N-methylpyrrolidone (NMP), dimethyl sulfoxide (DMSO), etc. can be used and soaked at room temperature or high temperature.

[0060] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. The above embodiments and the descriptions in the specification only illustrate the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the present invention claimed. The scope of the present invention claimed is defined by the appended claims and their equivalents.

Claims

1. A self-aligned bottom pinned SOT-MRAM process, characterized in that, Including the following steps: S1: On the surface of the bottom-pinned magnetic tunnel junction full-film layer sample, a bottom electrode is prepared by positive photoresist lithography process. Subsequently, an insulating dielectric is deposited in-situ to protect the sidewalls of the bottom electrode. After stripping the positive photoresist, the top electrode is exposed, and the surface is planarized; S2: In the direction perpendicular to the bottom electrode, the pattern area of the top electrode is exposed by negative photoresist process, and the top electrode material is grown by magnetron sputtering, so that a magnetic tunnel junction pattern is formed in the perpendicular crossing area of the top electrode and the bottom electrode; S3: Perform the following operations according to the selected type of hard mask material: If an insulating hard mask material is selected, on the basis of retaining the negative photoresist, the through holes at both ends of the top electrode are covered by positive photoresist process. After depositing the insulating hard mask material, the negative photoresist and the positive photoresist are stripped, and the through holes of the top electrode and the pattern of the bottom electrode are exposed; If a conductive hard mask material is selected, on the basis of retaining the negative photoresist, the conductive hard mask material is directly deposited; S4: Use positive photoresist to cover the through holes at both ends of the top electrode and the bottom electrode. Based on the hard mask pattern, the sidewalls of the MTJ are etched, and an insulating dielectric is deposited in-situ to protect the sidewalls. After stripping the positive photoresist, the through holes are exposed; S5: Use negative photoresist process to expose the through holes of the top electrode and the bottom electrode, and grow the outer electrode material.

2. The self-aligned bottom pinned SOT-MRAM process according to claim 1, wherein The structure of the bottom-pinned magnetic tunnel junction full-film layer sample is: substrate / seed layer / synthetic antiferromagnetic layer / fixed layer / barrier layer / free layer / top electrode / cover layer.

3. The self-aligned bottom-pinned SOT-MRAM process according to claim 1, wherein In step S1, the pattern of the bottom electrode is nano-strip-shaped. The width of the bottom electrode defines the longitudinal dimension of the MTJ, and the surface is planarized by chemical mechanical polishing.

4. The self-aligned bottom pinned SOT-MRAM process according to claim 1, wherein In step S2, the top electrode pattern is prepared by a negative photoresist process and is a nanobar that intersects the bottom electrode perpendicularly. Its width defines the lateral dimension of the MTJ. ， The top electrode material is selected from materials that can provide spin current or orbital current.

5. The self-aligned bottom-pinned SOT-MRAM process according to claim 1, wherein In step S3, the insulating hard mask material includes at least one of SiO2 and SiN x and the conductive hard mask material is a metal conductive hard mask material, including at least one of Ru, Ta, Pt, Cr, W, and TiN.

6. The self-aligned bottom-pinned SOT-MRAM process according to claim 1, wherein In step S3, if an insulating hard mask material is grown, the through holes of the top electrode are covered in advance by positive photoresist process. Precise alignment is not required, and the length of the through hole is reserved for 3-5um, and the width of the through hole is equal to the width of the top electrode pattern. If a conductive hard mask material is grown, the through holes of the top electrode do not need to be covered.

7. The self-aligned bottom-pinned SOT-MRAM process according to claim 1, characterized in that, In step S4, before etching, the through holes of the top electrode and the bottom electrode are covered by positive photoresist process. The length of the through hole is reserved for 3-5um, and precise alignment is not required.

8. The self-aligned bottom pinning SOT-MRAM process according to claim 1, wherein In step S4, only the barrier layer of the MTJ sidewall is exposed during etching, and no etch stop process is required.

9. The self-aligned bottom pinning SOT-MRAM process according to claim 2, wherein The cover layer material is selected from a single layer of Pt, Ta, Ru, W, Cr or a double-layer structure of Cr / Pt, Ru / Pt, Ru / Gd, and the thickness is 5-8nm.

10. The self-aligned bottom pinning SOT-MRAM process according to claim 1, wherein The protective material for the sidewall is selected from Si3N4, SiO2, Al2O3, Ta2O5, TiN or SiON, and is formed by physical vapor deposition or plasma enhanced chemical vapor deposition process.

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