Area enhanced getter architecture for wafer level vacuum packaged uncooled focal plane array

Abstract

Methods and systems are disclosed that utilize an enhanced area getter architecture for wafer level vacuum package of an uncooled focal plane array (FPA) assembly. The FPA assembly includes a device die having a first device surface, an infrared detector array disposed on the first device surface, and an infrared reference pixel disposed on the first device surface, and a window die bonded to the device die. The window die includes a recess and includes a first die surface covering the infrared detector array, a second die surface covering the infrared reference pixel, and a die wall surface joining the first die surface and the second die surface. The grain wall surface forms a perimeter of the recess, and a getter material is disposed on at least one of the grain wall surface or the first grain surface.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 430,953, entitled "Enhanced Area Getter Architecture for Wafer - level Vacuum Packaged Uncooled Focal Plane Array", filed on Dec. 7, 2022, the disclosure of which is incorporated herein by reference in its entirety for all purposes. Background Art

[0003] As optoelectronic detector technology continues to evolve, new designs can offer significantly improved resolution compared to past technologies. The resolution of an optoelectronic detector is determined at least in part by the number of pixels in the detector array. Generally, the more pixels in the detector array, the more detail can be provided during an imaging operation. Improved technologies have enabled manufacturing operations to produce pixels of much smaller size to maintain the overall form factor of the detector array while incorporating more pixels to provide improved resolution.

[0004] Despite the progress made in detector arrays, there is still a need in the art for improved methods and systems related to detector arrays. Summary of the Invention

[0005] According to various aspects of the present disclosure, embodiments of the present disclosure relate to methods and systems having an enhanced area getter architecture for wafer - level vacuum packaged uncooled focal plane arrays.

[0006] According to an embodiment of the present invention, a focal plane array (FPA) component is provided. The FPA component includes: a device die having a first device surface, an infrared detector array disposed on the first device surface, and an infrared reference pixel array disposed on the first device surface; and a window die bonded to the device die. The window die includes a recess and includes a first die surface covering the infrared detector array, a second die surface covering the infrared reference pixel array, and a die wall surface connecting the first die surface and the second die surface. The die wall surface forms a perimeter of the recess. The FPA component further includes a getter material disposed on at least one of the die wall surface or the first die surface.

[0007] In some embodiments, the recess extends into the window die in a first direction, and the first die surface overlaps with the infrared detector array in a plane orthogonal to the first direction. In various embodiments, a getter material is disposed on a portion of the second die surface. In some embodiments, the second die surface overlaps with the infrared reference pixel array in a plane orthogonal to the first direction. In various embodiments, the perimeter of the recess is defined by four die wall surfaces, and the getter material is disposed on the four die wall surfaces. In some embodiments, the FPA assembly further includes a sealing ring disposed between the device die and the window die and surrounding the recess. In various embodiments, the window die, the device die, and the sealing ring form a sealed cavity that overlaps with the infrared detector array. In some embodiments, the sealing ring includes solder ring metallization and a solder joint. In various embodiments, the infrared reference pixel array is disposed outside the perimeter of the recess. In some embodiments, the getter material includes titanium. In some embodiments, the getter material is non-optically transmissive. In various embodiments, the getter material forms an optical barrier structure for the infrared reference pixel array. In some embodiments, the pixel elements of the infrared reference pixel array are configured the same as the pixel elements of the infrared detector array. In various embodiments, the pixel elements of the infrared detector array include microbolometer detector pixel elements.

[0008] According to another embodiment of the present invention, a method of manufacturing a focal plane array (FPA) assembly is provided. The method includes: providing a carrier wafer having a bonding side and a planar side opposite the bonding side, providing a silicon-on-insulator wafer having a first side and a second side opposite the first side, and providing a device wafer having a plurality of solder joints. The method further includes bonding the first side of the silicon-on-insulator wafer to the bonding side of the carrier wafer, forming a plurality of sealing ring metalizations on the second side of the silicon-on-insulator wafer, and etching recesses in the second side of the silicon-on-insulator wafer to expose a portion of the bonding side of the carrier wafer and form a plurality of recess walls. The method further includes: forming a first anti-reflection coating on a first portion of the planar side of the carrier wafer, forming a second anti-reflection coating on a second portion of the bonding side of the carrier wafer, depositing a getter material on a third portion of the bonding side of the carrier wafer, on the plurality of recess walls, and on a fourth portion of the second side of the silicon-on-insulator wafer; and bonding the device wafer to the second side of the silicon-on-insulator wafer.

[0009] In some embodiments, etching the recess in the second side of the silicon-on-insulator wafer is performed by conducting a dry etch followed by a wet etch. In various embodiments, the device wafer includes an infrared detector pixel array and infrared reference pixels. In some embodiments, the infrared reference pixels are configured the same as the pixel elements of the infrared detector pixel array. In some embodiments, depositing the getter material is performed using a shadow mask. In various embodiments, a first portion of the bonding side of the carrier wafer is disposed inside the plurality of recess walls. In some embodiments, a fourth portion of the second side of the silicon-on-insulator wafer is disposed outside the plurality of recess walls. In various embodiments, bonding the device wafer to the silicon-on-insulator wafer is performed by attaching a plurality of solder joints to a plurality of seal ring metalizations on the second side of the silicon-on-insulator wafer. In some embodiments, depositing the getter material is performed after forming the first anti-reflection coating.

[0010] Many advantages over the conventional techniques are achieved through the present disclosure. For example, embodiments of the present disclosure provide methods and systems for an enhanced area getter architecture applicable to wafer-level vacuum packaging of uncooled focal plane arrays (FPAs). The embodiments enable the use of cavities formed within the window die in the FPA assembly to increase the surface area on which the getter material can be formed, thereby increasing the getter adsorption capacity within the cavities. In some embodiments, the getter material is formed on the surface of the window die not etched with recesses, on the surface of the carrier die in the recess area, and on the sidewall surfaces of the recesses. The getter material area is increased by increasing the surface area of the sidewalls for the getter deposition material, thereby increasing the getter adsorption capacity within the cavities. In various embodiments, the recess can be made deeper or shallower by adjusting the thickness of the window die. When the optical aperture permits, the recess depth can be increased, thereby increasing the available getter area. Additionally, embodiments of the present disclosure enable the use of the enhanced area getter architecture to act as a blocking structure for optically blind reference pixels. These and other embodiments of the present disclosure, along with many advantages and features of the present invention, will be described in more detail in conjunction with the following text and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Aspects of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, which are intended to be described in connection with the present invention content, the detailed description, and any preferred and / or specific embodiments disclosed in other ways or otherwise. However, the various aspects can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of illustration only and are intended to make the present disclosure exhaustive and complete and to fully convey the full scope to those skilled in the art.

[0012] Figures 1A to 1CShows a wafer-level vacuum packaging process for a bolometer-based uncooled focal plane array according to an embodiment of the present disclosure.

[0013] Figure 2 Is a cross-sectional view of a focal plane array component according to an embodiment of the present disclosure.

[0014] Figure 3A Shows a plan view of a device die having an infrared detector array and an infrared reference pixel array according to an embodiment of the present disclosure.

[0015] Figure 3B Shows a plan view of a window die according to an embodiment of the present disclosure.

[0016] Figure 3C Respectively show according to an embodiment of the present disclosure Figure 3A And Figure 3B Plan views of the bonded device die and window die.

[0017] Figures 4A to 4B Shows according to an embodiment of the present disclosure for depositing a getter material on a Figure 2 Plan view of a shadow mask of a focal plane array component.

[0018] Figures 5A to 5G Is a cross-sectional view showing a method of manufacturing a focal plane array component according to an embodiment of the present disclosure.

[0019] Figure 6 Shows a simplified flowchart of a method of manufacturing a focal plane array component according to an embodiment of the present disclosure. Detailed Description

[0020] The described embodiments generally relate to focal plane array (FPA) devices. More specifically, embodiments of the present disclosure provide methods and systems that utilize an enhanced area getter architecture for wafer-level vacuum packaging of uncooled FPA structures.

[0021] Figures 1A to 1CA wafer-level vacuum packaging (WLVP) process for a microbolometer-based uncooled focal plane array (FPA) according to an embodiment of the present disclosure is shown. In the illustrated embodiment, solder rings are placed around each die on the FPA wafer, where corresponding sealing rings are located on a mating window wafer. The FPA wafer and the window wafer can be aligned and bonded in a vacuum environment. After wafer bonding, slots are sawed in the window wafer to obtain access to the probe pads on the FPA wafer, enabling post-bonding wafer-level radiation testing of the vacuum-packaged FPA. Wafer-level vacuum packaging can provide a relatively small-size, low-weight, and low-cost solution for packaging uncooled FPAs.

[0022] Modern microbolometer-based uncooled infrared (IR) imaging FPAs can thermally isolate the microbolometer pixels from the environment to maximize the temperature change of the microbolometer pixels caused by the infrared scene flux incident on the pixels. A temperature-dependent resistance sensor can detect the temperature change caused by the scene through a change in resistance. The temperature-dependent resistance transducer can be made of, but not limited to, vanadium oxide (VOx) or amorphous silicon (a-Si). A microbolometer pixel array processed by a readout integrated circuit (ROIC) chip allows the microbolometer-based uncooled IR imaging FPA to image the scene. Thermal isolation of the microbolometer pixels can be achieved through relatively long, low-thermal-conductivity legs that electrically connect the microbolometer transducer to the underlying ROIC. To achieve relatively high sensitivity, the microbolometer pixel array can be vacuum packaged to reduce or eliminate heat conduction caused by gas molecules in the package. The package vacuum is maintained at less than 10 mTorr to reduce or eliminate the effect of gas heat conduction in the package.

[0023] To maintain a package vacuum of less than 10 mTorr in a wafer-level vacuum packaged uncooled FPA, a getter material can be deposited on the inner surface of the window wafer within the vacuum packaging region. However, since the region of the silicon window wafer that is open to the scene aperture must be transparent to the incident scene radiation, the available area for getter deposition on the inner surface may be limited. In some embodiments of the present disclosure, an enhanced getter area architecture is provided. The enhanced getter area architecture can utilize the presence of cavities etched within the window to increase the getter area, thereby increasing the getter adsorption capacity.

[0024] Figure 2A cross-sectional view of a focal plane array (FPA) component according to an embodiment of the present disclosure. The FPA component 200 may include a window die 220 and a device die 208. The window die 220 may be bonded to the device die 208 through solder joints 215. The device die 208 may include an infrared detector pixel array 218 disposed on a first surface 207 of the device die 208 and an optically blind infrared pixel array 216 disposed on the first surface 207. The device die 208 may further include solder ring metallization 214. The solder joints 215 may be formed on the solder ring metallization 214. The device die 208 may include bond pads 206 disposed on the first surface 207 of the device die 208. The bond pads 206 may be used to form a connection with a semiconductor package. The bond pads 206 may be used to form a connection with a semiconductor package that interfaces with external camera electronics that drive the operation of the FPA component 200 and collect the electrical output from the pixels in the FPA, and the electrical output is used to form an infrared image of a scene.

[0025] The window die 220 may include a carrier die 224 and a silicon-on-insulator die 226. In some embodiments, the thickness of the carrier die 224 may be, for example, 600 μm, while the thickness of the silicon-on-insulator die 226 may be, for example, 200 μm. The silicon-on-insulator die 226 may include a single-crystalline silicon layer 225 disposed on a buried oxide layer 222. In some embodiments, the thickness of the buried oxide layer 222 may be, for example, 1 μm to 2 μm. The buried oxide layer 222 may be bonded to a bonding side surface of the carrier die 224. The window die 220 may include a recess 202. The recess 202 may be formed by etching the silicon-on-insulator die 226, wherein the etching also removes the buried oxide layer 222. The silicon-on-insulator die 226 may include solder ring metallization 212. The solder joints 215 may be connected to the solder ring metallization 212.

[0026] A cavity 209 can be formed adjacent to the recess 202 and located between the device die 208 and the window die 220. The cavity 209 and the recess 202 can be in a vacuum environment. The getter material can be formed on the bonding side surface of the carrier die 224 in the region 210a, on the die wall surface in the region 210b, and on the second side surface of the silicon-on-insulator die 226 in the region 210c. In this way, since the die wall surface is used to form the getter material, the getter material surface area can be increased or maximized within the cavity 209 and the recess 202. By adjusting the thickness of the silicon-on-insulator die 226, the recess 202 can be made deeper or shallower. When permitted by the optical aperture, the recess depth can be increased, thereby increasing the available getter area on the die wall surface in the region 210b. In some embodiments, the perimeter of the recess 202 is reduced and thus the size of the recess 202 is reduced so that the getter can be formed on all sides of the recess 202. In this way, the volume of the recess 202 is reduced while additional getter material can be realized in the volume defined by the recess 202. Thus, embodiments of the present invention utilize the getter material to not only form an optical blocking structure above the infrared pixel array 216, but also to form an increased amount of getter material and an increased amount of getter area in a vacuum environment by depositing the getter material on the die wall surface in the region 210b and / or on the bonding side surface of the carrier die 224 in the region 210a. It should be noted that embodiments of the present invention reduce the perimeter of the recess 202, thereby reducing the volume corresponding to the recess 202, which is generally undesirable because such a reduction in volume reduces the ratio of volume to getter surface area. However, since the getter material is formed on the die wall surface in the region 210b, the ratio of volume to getter surface area can still be maintained or increased despite the reduction in volume. As will be apparent to those skilled in the art, the amount of getter material that can be formed on the bonding side surface of the carrier die 224 in the region 210a will be limited by the optical aperture required to receive infrared radiation passing through the carrier die 224 to the infrared detector pixel array 218. Those of ordinary skill in the art will recognize many variations, modifications, and alternatives.

[0027] As Figure 2As shown, the height of the cavity 209 measured along the z-direction can be much smaller than the height of the recess 202 also measured along the z-direction. As described above, the height of the recess 202 can be related to the thickness of the silicon-on-insulator die 226, e.g., 200 μm. While the height of the cavity 209 can be related to the thickness of the solder ring metallization 212, the solder joint 215, and the solder ring metallization 214, and this height can be on the order of about 10 μm. Thus, embodiments of the present invention help to block light that would otherwise reach the infrared pixel array 216, because positioning the getter material on the region 210c closer to the infrared pixel array 216 results in more effective light blocking performance. At the same time, the height of the recess 202 is independent of the height of the cavity 209, allowing for a larger volume for a given surface area, which is desirable for achieving a low-pressure (e.g., 10 mTorr) environment.

[0028] A first anti-reflection (AR) coating 204 can be formed on the planar side of the carrier die 224. A second AR coating 211 can be formed on the bonding side surface of the carrier die 224. The carrier die 224 can be transparent to infrared radiation so that infrared radiation can pass through the carrier die 224 and impinge on the infrared detector pixel array 218. These AR coatings can be formed in regions on both the planar side and the bonding side of the carrier die 224 that are open to the collection aperture for the scene flux incident on the infrared detector pixel array 218. In some embodiments, the anti-reflection layer can be a deposited AR coating, e.g., a multi-layer dielectric stack. In various embodiments, the AR layer can be formed by a high spatial frequency anti-reflection grating etched into the carrier die surface.

[0029] Figure 3A A plan view of a device die having an infrared detector array and an infrared reference pixel array in accordance with embodiments of the present disclosure is shown. The device die 302 can include bonding pads 304, solder ring metallizations 306, an infrared pixel array 308, and an infrared detector pixel array 310, which can also be referred to as a blind reference bolometer pixel array. As will be apparent to those skilled in the art, the infrared pixel array 308 includes the same detectors as those in the detector of the infrared detector pixel array 310, and the infrared pixel array 308 will not be exposed to the incident radiation and will provide a reference output (e.g., a resistance value), which can be utilized during the calibration of the infrared detector pixel array 310 as well as during the operation of the infrared detector pixel array 310.

[0030] Figure 3BShows a plan view of a window die in accordance with an embodiment of the present disclosure. The window die 322 may include a solder ring metallization 324, a cavity edge 320, an AR layer region 328, and a deposited getter region 326.

[0031] Figure 3C Respectively show a Figure 3A and Figure 3B plan view of a bonded device die and a window die in accordance with an embodiment of the present disclosure. Figure 3C The views in Figure 3C are seen through the planar side of the carrier die. The bonded device die 302, window die 322, bond pads 304, solder ring metallization 306, solder ring metallization 324, infrared pixel array 308, infrared detector pixel array 310, AR layer region 328, and getter region 326 are shown. In Figure 3C the solder ring metallization on the device die 302 is aligned with the corresponding solder ring metallization on the window die 322 to form a hermetically sealed FPA package. Figure 3C Also shown is a plan view of the getter region 326 where the getter material is formed at locations on the surface of the silicon-on-insulator die 226 that do not form recesses, on the surface of the carrier die in the recess region, and on the die wall surfaces of the recesses. Figure 3C Also shown is the presence of the infrared pixel array 308 formed on the device die 302, which may also be referred to as an optically blind reference pixel. As previously mentioned, the present disclosure discloses the use of an enhanced area getter architecture to serve as a blocking structure optically upstream of the optically blind infrared pixel array 216. Although not shown in the Figure 3C due to the planar view shown, the getter material is formed on the die wall surfaces that extend into the plane of the figure in region 210b at the cavity edge 320.

[0032] Figures 4A to 4B Shows a plan view of a shadow mask for depositing getter material onto a Figure 2 focal plane array assembly in accordance with an embodiment of the present disclosure. Figure 4A Shows a plan view of a wafer shadow mask 402. Figure 4B Shows a close-up of a die-level shadow mask having open areas 404 where mask material (such as metal) is absent and shadow areas 406 where mask material (such as metal) is present. Although some embodiments of the present invention are described in connection with using a shadow mask during getter deposition, other getter deposition processes are also included within the scope of the present invention, including the use of photolithography and lift-off processes. Those of ordinary skill in the art will recognize many variations, modifications, and alternatives.

[0033] Figures 5A to 5Gis a cross-sectional view showing a method of manufacturing a focal plane array component according to an embodiment of the present disclosure. As Figure 5A shown, a carrier wafer 504 can be bonded to a silicon-on-insulator wafer 506 to form a window wafer 502. The carrier wafer may include a planar side 503 and a bonding side 505. The silicon-on-insulator wafer 506 may include a first side 507 and a second side 509, and have a buried oxide layer 508 adjacent to the first side 507. As Figure 5A shown, the first side 507 of the silicon-on-insulator wafer 506 is bonded to the bonding side 505 of the carrier wafer 504.

[0034] Figure 5B shows the formation of a solder ring metallide 510 on the second side 509 of the silicon-on-insulator wafer 506. Figure 5C shows the formation of a recess 512 in the silicon-on-insulator wafer 506. The recess is formed by etching a recess in the second side 509 of the silicon-on-insulator wafer 506. In some embodiments, the etching process is performed by a dry etching followed by a wet etching, during which the buried oxide layer 508 is removed to expose a portion of the bonding side 505 of the carrier wafer 504.

[0035] Figure 5D shows the formation of an anti-reflection (AR) layer 514 on the planar side 503 of the carrier wafer 504. Figure 5E shows the formation of an AR layer 516 on the bonding side 505 of the carrier wafer 504. These AR layers are formed on both the planar side 503 and the bonding side 505 and are open and serve as regions for the collection aperture of the scene flux incident on the Figure 2 shown infrared detector pixel array 218. In some embodiments, the AR layer may be a coating, while in other embodiments, the AR layer may be a high spatial frequency anti-reflection grating etched into the planar side 503 and / or the bonding side 505 of the carrier wafer 504.

[0036] Figure 5F shows the formation of getter regions on the bonding side 505 of the carrier die wafer 504 in region 518a, on the die wall surface in region 518b, and on the second side 509 of the silicon-on-insulator wafer 506 in region 518c. As previously described, the getter is formed by evaporating the getter material using a shadow mask. In some embodiments, the getter material may include, for example but not limited to, titanium, or an alloy of aluminum, zirconium, titanium, vanadium, and / or iron.

[0037] Figure 5GIllustrated is the formation of an FPA assembly by bonding a device wafer 522 to a window wafer 502 and dicing the FPA assembly 500 into units. The device wafer 522 may include an infrared detector pixel array 528, an optically blind infrared pixel array 526, and solder ring metallizations 534. Bonding of the device wafer 522 to the window wafer 502 may be achieved by forming solder joints 520.

[0038] Figure 6 A simplified flowchart of a method of manufacturing a focal plane array (FPA) assembly according to an embodiment of the present disclosure is shown. As Figure 6 shown, the method of manufacturing an FPA assembly includes: providing a carrier wafer (610) having a bonding side and a planar side opposite the bonding side. The method further includes: providing a silicon-on-insulator wafer (612) having a first side and a second side opposite the second side. The method further includes: bonding the first side of the silicon-on-insulator wafer to the bonding side of the carrier wafer (614).

[0039] Additionally, the method includes: forming a plurality of seal ring metallizations (616) on the second side of the silicon-on-insulator wafer. The method further includes: etching recesses in the second side of the silicon-on-insulator wafer to expose a portion of the bonding side of the carrier wafer and form a plurality of recess walls (618). Further, the method includes: forming a first anti-reflection (AR) coating (620) on a first portion of the planar side of the carrier wafer. Further, the method includes: forming a second AR coating (622) on a second portion of the bonding side of the carrier wafer. In some embodiments, the second AR coating is optional, for example, in a low-cost implementation where the cavity-side AR coating is eliminated, and in an even lower-cost implementation where both the planar-side AR coating and the cavity-side AR coating are eliminated. Further, the method includes: depositing a getter material (624) on a third portion of the bonding side of the carrier wafer, on the plurality of recess walls, and on a fourth portion of the second side of the silicon-on-insulator wafer, and bonding a device wafer to the silicon-on-insulator wafer (626), for example, bonding to the second side of the silicon-on-insulator wafer.

[0040] It should be understood that Figure 6 the specific steps shown provide a particular method of manufacturing an FPA assembly according to an embodiment of the present disclosure. According to alternative embodiments, other step sequences may also be performed. For example, alternative embodiments of the present disclosure may perform the steps outlined above in a different order. Additionally, Figure 6 each of the steps shown in may include multiple sub-steps, which may be performed in various orders suitable for each step. Additionally, depending on the specific application, additional steps may be added or removed. Those of ordinary skill in the art will recognize many variations, modifications, and alternatives.

[0041] Various examples of the present disclosure are provided below. As used below, any reference to a series of examples should be understood as a separate reference to each of these examples (e.g., "Examples 1 to 4" should be understood as "Example 1, Example 2, Example 3, or Example 4").

[0042] Example 1 is a focal plane array (FPA) component, comprising: a device die having a first device surface, an infrared detector array disposed on the first device surface, and an infrared reference pixel array disposed on the first device surface; a window die bonded to the device die, wherein the window die includes a recess and includes: a first die surface covering the infrared detector array; a second die surface covering the infrared reference pixel array; and a die wall surface joining the first die surface and the second die surface, wherein the die wall surface forms a perimeter of the recess; and a getter material disposed on at least one of the die wall surface or the first die surface.

[0043] Example 2 is the FPA component of Example 1, wherein the recess extends into the window die in a first direction, and the first die surface overlaps the infrared detector array in a plane orthogonal to the first direction.

[0044] Example 3 is the FPA component of Examples 1 to 2, wherein the getter material is disposed on a part of the second die surface.

[0045] Example 4 is the FPA component of Examples 1 to 3, wherein the second die surface overlaps the infrared reference pixel array in a plane orthogonal to the first direction.

[0046] Example 5 is the FPA component of Example 1, wherein the perimeter of the recess is defined by four die wall surfaces, and the getter material is disposed on the four die wall surfaces.

[0047] Example 6 is the FPA component of Example 1, further comprising a sealing ring disposed between the device die and the window die and surrounding the recess.

[0048] Example 7 is the FPA component of Examples 1 and 6, wherein the window die, the device die, and the sealing ring form a sealed cavity overlapping the infrared detector array.

[0049] Example 8 is the FPA component of Examples 1 and 6, wherein the sealing ring includes a solder ring metalization and a solder joint.

[0050] Example 9 is the FPA component of Example 1, wherein the infrared reference pixel array is disposed outside the perimeter of the recess.

[0051] Example 10 is the FPA component of Example 1, wherein the getter material includes titanium.

[0052] Example 11 is the FPA component of Example 1, where the getter material is non-optically transmissive.

[0053] Example 12 is the FPA component of Example 1, where the getter material forms an optical barrier structure for the infrared reference pixel array.

[0054] Example 13 is the FPA component of Example 1, where the pixel elements of the infrared reference pixel array are configured the same as the pixel elements of the infrared detector array.

[0055] Example 14 is the FPA component of Example 1, where the pixel elements of the infrared detector array include microbolometer detector pixel elements.

[0056] Example 15 is a method of manufacturing a focal plane array (FPA) component, the method comprising: providing a carrier wafer having a bonding side and a planar side opposite the bonding side; providing a silicon-on-insulator wafer having a first side and a second side opposite the first side; providing a device wafer having a plurality of solder joints; bonding the first side of the silicon-on-insulator wafer to the bonding side of the carrier wafer; forming a plurality of seal ring metalizations on the second side of the silicon-on-insulator wafer; etching recesses in the second side of the silicon-on-insulator wafer to expose a portion of the bonding side of the carrier wafer and form a plurality of recess walls; forming a first anti-reflection coating on a first portion of the planar side of the carrier wafer; forming a second anti-reflection coating on a second portion of the bonding side of the carrier wafer; depositing a getter material on a third portion of the bonding side of the carrier wafer, on the plurality of recess walls, and on a fourth portion of the second side of the silicon-on-insulator wafer; and bonding the device wafer to the second side of the silicon-on-insulator wafer.

[0057] Example 16 is the method of manufacturing an FPA component of Example 15, where etching the recesses in the second side of the silicon-on-insulator wafer is performed by carrying out a dry etching followed by a wet etching.

[0058] Example 17 is the method of manufacturing an FPA component of Example 15, where the device wafer includes an infrared detector pixel array and an infrared reference pixel.

[0059] Example 18 is the method of manufacturing an FPA component of Example 15 and Example 17, where the infrared reference pixel is configured the same as the pixel elements of the infrared detector pixel array.

[0060] Example 19 is the method of manufacturing an FPA component of Example 15, where depositing the getter material is performed using a shadow mask.

[0061] Example 20 is the method of manufacturing an FPA component according to Example 15, where a first portion of the bonding side of the carrier wafer is disposed inside the plurality of recess walls.

[0062] Example 21 is a method of manufacturing an FPA component of Example 15, wherein a fourth portion of the second side of the silicon-on-insulator wafer is disposed outside of the plurality of recess walls.

[0063] Example 22 is a method of manufacturing an FPA component of Example 15, wherein bonding the device wafer to the silicon-on-insulator wafer is performed by attaching a plurality of solder joints to a plurality of seal ring metallizations on the second side of the silicon-on-insulator wafer.

[0064] Example 23 is a method of manufacturing an FPA component of Example 15, wherein depositing the getter material is performed after forming the first anti-reflection coating.

[0065] Those of ordinary skill in the art will understand that other modifications to the devices and methods of the present disclosure may be made without departing from the scope of the present disclosure to implement various applications of the method and system of an enhanced area getter architecture for wafer-level vacuum packaging of uncooled focal plane arrays.

[0066] The examples and embodiments described herein are for illustrative purposes only. Various modifications or changes to these examples and embodiments will be apparent to those skilled in the art. These will be included within the spirit and scope of this application, as well as the scope of the appended claims.

Claims

1. A focal plane array (FPA) assembly, comprising: A device die having a first device surface, an infrared detector array disposed on the first device surface, and an infrared reference pixel array disposed on the first device surface; A window die bonded to the device die, wherein the window die includes a recess and includes: A first die surface covering the infrared detector array; A second die surface covering the infrared reference pixel array; and A die wall surface joining the first die surface and the second die surface, wherein the die wall surface forms a perimeter of the recess; and A getter material disposed on at least one of the die wall surface or the first die surface.

2. The FPA component according to claim 1, wherein The recess extends into the window die in a first direction, and the first die surface overlaps the infrared detector array in a plane orthogonal to the first direction.

3. The FPA component according to claim 2, wherein, The getter material is disposed on a portion of the second die surface.

4. The FPA component according to claim 3, wherein, The second die surface overlaps the infrared reference pixel array in the plane orthogonal to the first direction.

5. The FPA component according to claim 1, wherein, The perimeter of the recess is defined by four die wall surfaces, and the getter material is disposed on the four die wall surfaces.

6. The FPA assembly according to claim 1, further comprising a sealing ring disposed between the device die and the window die and surrounding the recess.

7. The FPA component according to claim 6, wherein, The window die, the device die, and the sealing ring form a sealed cavity overlapping the infrared detector array.

8. The FPA component according to claim 6, wherein, The sealing ring includes a solder ring metallization and a solder joint.

9. The FPA component according to claim 1, wherein, The infrared reference pixel array is disposed outside the perimeter of the recess.

10. The FPA component according to claim 1, wherein, The getter material includes titanium.

11. The FPA component according to claim 1, wherein, The getter material is non-optically transmissive.

12. The FPA component according to claim 1, wherein, The getter material forms an optical blocking structure for the infrared reference pixel array.

13. The FPA component according to claim 1, wherein, The pixel elements of the infrared reference pixel array are configured to be the same as the pixel elements of the infrared detector array.

14. The FPA component according to claim 1, wherein, The pixel elements of the infrared detector array include microbolometer detector pixel elements.

15. A method of manufacturing a focal plane array (FPA) assembly, the method comprising: Providing a carrier wafer having a bonding side and a planar side opposite the bonding side; Providing a silicon-on-insulator wafer having a first side and a second side opposite the first side; Providing a device wafer having a plurality of solder joints; Bonding the first side of the silicon-on-insulator wafer to the bonding side of the carrier wafer; Forming a plurality of sealing ring metalizations on the second side of the silicon-on-insulator wafer; Etching a recess in the second side of the silicon-on-insulator wafer to expose a portion of the bonding side of the carrier wafer and form a plurality of recess walls; Forming a first anti-reflection coating on a first portion of the planar side of the carrier wafer; Forming a second anti-reflection coating on a second portion of the bonding side of the carrier wafer; Depositing a getter material on a third portion of the bonding side of the carrier wafer, on the plurality of recess walls, and on a fourth portion of the second side of the silicon-on-insulator wafer; And Bond the device wafer to the second side of the silicon-on-insulator wafer.

16. The method according to claim 15, wherein, Etching the recesses in the second side of the silicon-on-insulator wafer is performed by carrying out dry etching followed by wet etching.

17. The method according to claim 15, wherein, The device wafer includes an infrared detector pixel array and infrared reference pixels.

18. The method according to claim 17, wherein, The infrared reference pixels are configured identically to the pixel elements of the infrared detector pixel array.

19. The method according to claim 15, wherein Depositing the getter material is performed using a shadow mask.

20. The method according to claim 15, wherein The first portion of the bonding side of the carrier wafer is disposed inside the walls of the plurality of recesses.

21. The method according to claim 15, wherein, The fourth portion of the second side of the silicon-on-insulator wafer is disposed outside the walls of the plurality of recesses.

22. The method according to claim 15, wherein Bonding the device wafer to the silicon-on-insulator wafer is performed by attaching the plurality of solder joints to the plurality of seal ring metallizations on the second side of the silicon-on-insulator wafer.

23. The method according to claim 15, wherein, Depositing the getter material is performed after forming the first anti-reflection coating.

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