Apparatus, system, and method for injecting manufactured errors into machine inspection architecture

Abstract

An exemplary system includes and / or represents an agent and a machine inspection architecture. In one example, a machine check architecture includes and / or represents at least one circuit configured to report an error via at least one reporting register. In this example, the machine check architecture further includes and / or represents at least one error injection register configured to cause the circuitry to inject at least one manufactured error report into the report register in response to a write operation performed by the proxy on at least one bit of the error injection register. Various other devices, systems, and methods are also disclosed.

Description

Background Art

[0001] Machine check architectures are often used to report errors to an operating system running on a processor. For example, a system-on-chip (SoC) includes and / or represents various processors and a machine check architecture that detects errors and / or reports errors to one or more processors. In this example, a user and / or administrator of the SoC may want and / or need to test the impact of one or more errors on its firmware, software, and / or the streams running on the processor. Unfortunately, as the number of error detectors included in the machine check architecture expands and / or increases, such testing may be impractical, infeasible, and / or non-scalable. Accordingly, the present disclosure identifies and addresses the need for additional and improved devices, systems, and methods for injecting manufactured errors into a machine check architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The drawings illustrate multiple exemplary embodiments and are part of the specification. Together with the following description, these drawings demonstrate and explain various principles of the present disclosure.

[0003] Figure 1 is a block diagram of a portion of an exemplary computing device capable of injecting manufactured errors into a machine check architecture in accordance with one or more embodiments of the present disclosure.

[0004] Figure 2 is a block diagram of an exemplary machine check architecture that supports and / or facilitates injecting manufactured errors into a machine check architecture in accordance with one or more embodiments of the present disclosure.

[0005] Figure 3 is a block diagram of an exemplary computing device capable of injecting manufactured errors into a machine check architecture in accordance with one or more embodiments of the present disclosure.

[0006] Figure 4 is a block diagram of an exemplary computing device capable of injecting manufactured errors into a machine check architecture in accordance with one or more embodiments of the present disclosure.

[0007] Figure 5 is a block diagram of an exemplary computing device capable of injecting manufactured errors into a machine check architecture in accordance with one or more embodiments of the present disclosure.

[0008] Figure 6 is a block diagram of an exemplary computing device capable of injecting manufactured errors into a machine check architecture in accordance with one or more embodiments of the present disclosure.

[0009] Figure 7 is a block diagram of an exemplary embodiment of a computing system involving facilitating injecting manufactured errors into a machine check architecture in accordance with one or more variations of the present disclosure.

[0010] Figure 8 is a flowchart of an exemplary method for injecting manufactured errors into a machine check architecture according to one or more specific implementations of the present disclosure.

[0011] In all the figures, the same reference numerals and descriptions indicate like but not necessarily identical elements. While the exemplary specific implementations described herein are susceptible to various modifications and alternative forms, specific specific implementations have been shown by way of example in the figures and will be described in detail herein. However, the exemplary specific implementations described herein are not intended to be limited to the particular forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims. Detailed Description

[0012] The present disclosure describes various devices, systems, and methods for injecting manufactured errors into a machine check architecture. In some examples, a SoC implements a machine check architecture with an error detector that is modified to inject manufactured errors for testing and / or verification purposes. Unfortunately, some configurations of the machine check architecture require custom logic components for all of its modified error detectors. In certain specific implementations, such custom logic components are not scalable because a SoC may include and / or implement thousands of error detectors that utilize the machine check architecture for error reporting.

[0013] To address this issue, the SoC may provide and / or implement registers that are accessible by a privileged out-of-band agent. When a certain portion of the register is written, the SoC hardware (e.g., a hardware block and / or circuit in the machine check architecture) purposefully causes manufactured errors to be injected into the logging pipeline of the machine check architecture. The SoC hardware may select and / or customize which errors are to be manufactured and / or injected into the logging pipeline of the machine check architecture to suit a particular purpose and / or test a certain function. By using the SoC hardware to select and / or customize such errors for manufacturing and / or injection, the user and / or administrator of the SoC may deploy, create, and / or establish a robust platform for testing and / or verifying their software and / or firmware against errors. Alternatively, the SoC hardware may write the manufactured errors directly into a register in the machine check architecture without having to push the errors along the logging pipeline.

[0014] In some examples, a system includes and / or represents an agent and a machine check architecture. In one example, the machine check architecture includes and / or represents at least one circuit configured to report an error via at least one reporting register. In this example, the machine check architecture also includes and / or represents at least one error injection register configured to cause the circuit to inject at least one fabricated error report into the reporting register in response to a write operation performed by the agent on at least one bit of the error injection register.

[0015] In some examples, the circuit includes and / or represents multiple circuits, and the error injection register includes and / or represents multiple error rejection registers. In one example, the machine check architecture includes and / or represents a pipeline configured to carry an error report from the circuit to the reporting register. In this example, the error injection register is configured to cause the circuit to inject a fabricated error report into the pipeline for transmission to the reporting register.

[0016] In some examples, the circuit includes and / or represents one or more lines configured to convey another fabricated error report from an external source to the reporting register via a pipeline. In one example, the reporting register includes and / or represents a first reporting register and a second reporting register. In this example, the first reporting register is configured to receive a first copy of the fabricated error report via a first channel of the pipeline and store the first copy of the fabricated error report for access by an in-band processor. Additionally or alternatively, the second reporting register is configured to receive a second copy of the fabricated error report and / or store the second copy of the fabricated error report for access by an out-of-band controller via a second channel of the pipeline.

[0017] In some examples, the agent includes and / or represents software or firmware running on a processor having access to the error injection register. In one example, the system also includes and / or represents an integrated circuit including the processor and the machine check architecture. Additionally or alternatively, the agent includes and / or represents an out-of-band controller having access to the error injection register.

[0018] In some examples, the system also includes and / or represents a first integrated circuit including an out-of-band controller and a second integrated circuit including the machine check architecture. In one example, the out-of-band controller includes and / or represents a baseboard management controller external to the second integrated circuit.

[0019] In some examples, the circuit includes and / or represents a table configured to store multiple error entries and map bits of the error injection register to specific error entries included in the error entries. In such examples, the circuit is configured to generate a fabricated error report for injection based at least in part on the mapping of the bits to the specific error entries.

[0020] In some examples, the error injection register is further configured to cause the circuit to inject another manufactured error report into the report register in response to another write operation performed by an agent on at least one other bit of the error injection register. In one example, the system further includes and / or represents an out-of-band controller that is configured to perform a specific action in response to a specific error identified in the manufactured error report injected into the report register. For example, the specific action includes and / or represents triggering an interruption to notify at least one other circuit of the specific error.

[0021] In some examples, the at least one other circuit includes and / or represents a processor disposed on an integrated circuit equipped with a machine check architecture. In such an example, the at least one other circuit further includes and / or represents a baseboard management controller external to the integrated circuit including the machine check architecture.

[0022] In some examples, the machine check architecture includes and / or represents at least one circuit configured to report an error to the report register and a pipeline configured to carry the error report from the circuit to the report register. In such an example, the machine check architecture includes and / or represents at least one error injection register configured to cause the circuit to inject at least one manufactured error report into the report register via the pipeline in response to a write operation performed by an external source on at least one bit of the error injection register.

[0023] In some examples, a method includes and / or represents configuring at least one error injection register of a circuit in a machine check architecture. In such examples, the method further includes and / or represents detecting a write operation performed on at least one bit of the error injection register. In one example, the method further includes and / or represents injecting at least one manufactured error report into at least one report register in the machine check architecture in response to the write operation.

[0024] Reference will be made below to Figures 1 to 7 Provide a detailed description of exemplary devices, systems, and / or corresponding embodiments for injecting manufactured errors into a machine check architecture. Will be combined with Figure 8 Provide a detailed description of an exemplary method for injecting manufactured errors into a machine check architecture.

[0025] Figure 1 An exemplary computing device 100 that facilitates and / or supports injecting manufactured errors into a machine check architecture is shown. As Figure 1As shown, the exemplary computing device 100 includes and / or represents a machine check architecture 102 and an agent 104. In some examples, the machine check architecture 102 and the agent 104 are electrically and / or communicatively coupled to the machine check architecture 102. In one example, the machine check architecture 102 includes and / or represents a plurality of circuits 108(1)-(N) and at least one reporting register 114. In this example, the circuits 108(1)-(N) respectively include and / or represent error detectors 110(1)-(N) and error injection registers 116(1)-(N). In certain embodiments, the error detectors 110(1)-(N) respectively detect errors occurring in the circuits 108(1)-(N) and / or report the errors to the agent 104, one or more in-band processors, and / or one or more out-of-band controllers via the reporting register 114.

[0026] In some examples, the machine check architecture 102 may include and / or represent a circuit, device, and / or hardware mechanism that detects errors and / or reports errors to another circuit, device, and / or hardware mechanism. For example, a SoC may include and / or implement the machine check architecture 102 as well as various processors and / or central processing unit (CPU) cores. In this example, the machine check architecture 102 is configured and / or programmed to monitor hardware errors occurring in the circuits 108(1)-(N), the processors or CPU cores implemented on the SoC, and / or other features or components of the SoC.

[0027] In some examples, the circuits 108(1)-(N) include and / or represent hardware blocks and / or libraries of the machine check architecture 102. In one example, the hardware blocks and / or libraries include and / or represent a memory controller and / or a CPU core. Additionally or alternatively, the hardware blocks and / or libraries include and / or represent control registers and / or model-specific registers for checking, detecting, and / or recording various hardware and / or machine errors. Examples of such errors include, but are not limited to, memory or cache errors, buffer errors, translation errors, parity errors, system bus errors, error-correcting code (ECC) failures, error detection and correction (EDAC) failures, communication errors, input / output (I / O) errors, portions of one or more of the above, combinations or variations of one or more of the above, and / or any other detectable errors. The circuits 108(1)-(N) may be configured and / or programmed to generate and / or issue a manufactured error report indicating any of these errors in response to one or more bits being written to and / or modified in the error injection registers 116(1)-(N).

[0028] In some examples, agent 104 includes and / or represents a hardware-implemented device and / or circuitry capable of executing firmware, an operating system, and / or user applications. Additionally or alternatively, agent 104 includes and / or represents software and / or firmware running on a hardware-implemented device and / or circuitry. In one example, agent 104 may include and / or represent software and / or firmware running on an in-band processor implemented on a SoC equipped with machine check architecture 102. In another example, agent 104 may include and / or represent an out-of-band controller that interfaces and / or communicates with a SoC equipped with machine check architecture 102. Additionally or alternatively, agent 104 may include and / or represent software and / or firmware running on such an out-of-band controller.

[0029] In some examples, error injection registers 116(1)-(N) respectively cause and / or direct circuits 108(1)-(N) to inject and / or insert one or more manufactured error reports into report register 114. In one example, in response to a write operation performed by agent 104 on one or more of error injection registers 116(1)-(N), the injection and / or insertion of a manufactured error report occurs. For example, agent 104 writes and / or modifies one or more bits of error injection register 116(1). In response to this write and / or modification of such bits, error injection register 116(1) may cause and / or direct error detector 110(1) and / or circuit 108(1) to inject and / or insert a manufactured error report into report register 114. The manufactured error report may correspond to, represent, and / or reflect an emulated error associated with the bits affected by the write operation.

[0030] In some examples, agent 104 and / or another out-of-band component may obtain, receive, and / or retrieve a manufactured error report from report register 114. In such examples, agent 104 and / or another out-of-band component may process and / or consume the manufactured error report to test whether all relevant features and / or components of machine check architecture 102 are working and / or operating as expected. In one example, agent 104 and / or another out-of-band component may notify a user of computing device 100 of any features and / or components of machine check architecture 102 that are identified as not working and / or operating as expected, at least in part based on the test. Additionally or alternatively, agent 104 and / or another out-of-band component may perform one or more remedial actions to address and / or fix any features and / or components of machine check architecture 102 that are identified as not working and / or operating as expected, at least in part based on the test.

[0031] Figure 2An exemplary embodiment of a machine check architecture 102 that facilitates and / or supports injecting manufacturing errors is shown. In some examples, the machine check architecture 102 may include and / or represent certain components and / or features that perform and / or provide functions similar and / or identical to those described above in connection with Figure 1 the functions described. As Figure 2 shown, the exemplary machine check architecture 102 includes and / or represents a pipeline 212 that carries, transfers, and / or conveys error reports 220 from circuits 108(1)-(N) to a report register 216.

[0032] In some examples, error injection registers 116(1)-(N) may respectively cause and / or direct circuits 108(1)-(N) to inject manufactured error reports into the pipeline 212 for transmission to one or more of the report registers 216. In one example, circuits 108(1)-(N) respectively include and / or represent tables 210(1)-(N). In this example, tables 210(1)-(N) may each store a plurality of error entries and / or map one or more bits of the error injection registers 116(1)-(N) to those error entries respectively.

[0033] For example, if an agent 104 writes to at least one bit of the error injection register 116(1), the circuit 108(1) may refer to the table 210(1) to identify which error to manufacture and / or report to the report register 216. In this example, the mapping may indicate and / or specify the error corresponding and / or associated with this bit of the error injection register 116(1). Continuing with this example, the error detector 110(1) and / or the circuit 108(1) may generate a manufactured error report 226 at least in part based on the mapping of this bit of the table 210(1) to a specific error entry. Additionally or alternatively, the error detector 110(1) and / or the circuit 108(1) may then inject and / or insert the manufactured error report 226 into the pipeline 212 for transmission to the report register 216.

[0034] Similarly, if agent 104 writes to another bit of error injection register 116(1), circuit 108(1) may refer to table 210(1) to identify which other error(s) to fabricate and / or report to reporting register 216. In this example, the mapping may indicate and / or specify the other error(s) corresponding to and / or associated with this other bit of error injection register 116(1). Continuing with this example, error detector 110(1) and / or circuit 108(1) may generate another fabricated error report based at least in part on the mapping of this other bit of table 210(1) to this other specific error entry. Additionally or alternatively, error detector 110(1) and / or circuit 108(1) may then inject and / or insert the other fabricated error report specifying the other error into pipeline 212 for transmission to reporting register 216.

[0035] In some examples, error injection registers 116(1)-(N) and / or tables 210(1)-(N) may be configurable and / or programmable to facilitate testing and / or verifying specific functions of machine check architecture 102. For example, agent 104 and / or another feature of computing device 100 may configure and / or program error injection register 116(1) and / or table 210(1) to implement a specific mapping between the bits of error injection register 116(1) and specific errors. In this example, agent 104 and / or another feature of computing device 100 may dynamically and / or as needed reconfigure and / or reprogram error injection register 116(1) and / or table 210(1) to test and / or verify specific functions of the machine check architecture.

[0036] Figure 3 Another exemplary implementation of machine check architecture 102 that facilitates and / or supports injecting fabricated errors is shown. In some examples, machine check architecture 102 may include and / or represent certain components and / or features that perform and / or provide functions similar and / or identical to those described above in connection with Figure 1 and Figure 2 either. As Figure 3 shown, exemplary machine check architecture 102 also includes and / or represents one or more in-band reporting registers 316 and / or out-of-band reporting registers 318.

[0037] In some examples, the pipeline 212 of the machine check architecture 102 includes and / or represents a unified channel 312, a fork 314, a single channel 322, and / or a single channel 324. In this example, the unified channel 312 carries and / or transfers error reports 220 and / or fabricated error reports 326 to both the in-band reporting register 316 and the out-of-band reporting register 318. In one example, the single channel 322 may electrically and / or communicatively couple the fork 314 to the in-band reporting register 316. Additionally or alternatively, the single channel 324 may electrically and / or communicatively couple the fork 314 to the out-of-band reporting register 318.

[0038] In some examples, the unified channel 312 is electrically and / or communicatively coupled to the fork 314. In such an example, the unified channel 312 feeds and / or delivers error reports 220 and / or fabricated error reports 326 to the fork 314, which duplicates and / or copies the error reports 220 and / or fabricated error reports 326. For example, the fork 314 splits and / or divides the unified channel 312 into the single channel 322 and the single channel 324. In this example, the single channel 322 carries and / or transfers a copy of the error reports 220 and / or fabricated error reports 326 to the in-band reporting register 316, and the single channel 324 carries and / or transfers another copy of the error reports 220 and / or fabricated error reports 326 to the out-of-band reporting register 318.

[0039] In some examples, the error detectors 110(1)-(N) respectively monitor and / or detect certain errors in and / or via the circuits 108(1)-(N). In such an example, one or more of the error detectors 110(1)-(N) generate and / or issue error reports 220 in response to detecting such errors. In one example, the error detectors 110(1)-(N) may send and / or transfer error reports 220 and / or fabricated error reports 326 to both the in-band reporting register 316 and the out-of-band reporting register 318 via the pipeline 112. For example, the error reports 220 and / or fabricated error reports 326 may traverse and / or travel from one or more of the circuits 108(1)-(N) to the fork 314 via the unified channel 312. In this example, the fork 314 may duplicate and / or copy the error reports 220 and / or fabricated error reports 326 for transfer to both the in-band reporting register 316 and the out-of-band reporting register 318. Accordingly, a copy of the error reports 220 and / or fabricated error reports 326 may traverse and / or travel from the fork 314 to the in-band reporting register 316 via the single channel 322, and another copy of the error reports 220 and / or fabricated error reports 326 may traverse and / or travel from the fork 314 to the out-of-band reporting register 318 via the single channel 324.

[0040] In some examples, the in - band report register 316 receives a copy of the error report 220 and / or the manufactured error report 326, and stores the copy of the error report 220 and / or the manufactured error report 326 for access by the agent 104 and / or the in - band processor. Additionally or alternatively, the out - of - band report register 318 receives another copy of the error report 220 and / or the manufactured error report 326, and stores the copy of the error report 220 and / or the manufactured error report 326 for access by the agent 104 and / or the out - of - band processor.

[0041] Figure 4 An exemplary implementation of the computing device 100 that facilitates and / or supports injecting manufactured errors into the machine - check architecture is shown. In some examples, the computing device 100 may include and / or represent certain components and / or features that perform and / or provide functions similar and / or identical to those described in connection with Figures 1 to 3 any of the above. In one example, the computing device 100 includes and / or represents the machine - check architecture 102, the in - band processor 404, the out - of - band controller 406, and / or the external source 414. In this example, the machine - check architecture 102 may be electrically and / or communicatively coupled to the in - band processor 404, the out - of - band controller 406, and / or the external source 414.

[0042] In some examples, the agent 104 may include and / or represent the in - band processor 404 that implements and / or executes the operating system 408. In one example, the operating system 408 may cause and / or direct the in - band processor 404 to obtain, receive, and / or retrieve a copy of the manufactured error report 326 from the in - band report register 316. Additionally or alternatively, the agent 104 may include and / or represent software and / or firmware running on the in - band processor 404. In this example, the in - band processor 404 has and / or maintains access to one or more in - band report registers 316. In certain implementations, the in - band processor 404 and / or the operating system 408 processes and / or consumes the copy of the manufactured error report 326 to test whether all relevant features and / or components of the machine - check architecture 102 are working and / or functioning as expected.

[0043] Additionally or alternatively, agent 104 may include and / or represent an out-of-band controller 406 that implements and / or executes firmware 410. In one example, firmware 410 may cause and / or direct the out-of-band controller 406 to obtain, receive, and / or retrieve a copy of the manufactured error report 326 from the out-of-band reporting register 318. In this example, the out-of-band controller 406 has and / or maintains access to one or more out-of-band reporting registers 318. In certain embodiments, the out-of-band controller 406 and / or firmware 410 processes and / or consumes the copy of the manufactured error report 326 to test whether all relevant features and / or components of the machine check architecture 102 are working and / or functioning as expected.

[0044] In some examples, the in-band processor 404 may include and / or represent a hardware-implemented device and / or circuit capable of executing firmware, an operating system, and / or user applications. For example, the in-band processor 404 may include and / or represent a graphics processing unit (GPU) and / or a CPU. In this example, the in-band processor 404 may include and / or represent one of several processors (e.g., several x86 processors) implemented and / or disposed on a system-on-chip (SoC). Additional examples of the in-band processor 404 include, but are not limited to, parallel acceleration processors, tensor cores, microprocessors, microcontrollers, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), integrated circuits, chiplets, portions of one or more of the foregoing, variations or combinations of one or more of the foregoing, and / or any other suitable in-band processor.

[0045] The in-band processor 404 may implement and / or be configured with any of a variety of different architectures and / or microarchitectures. For example, the in-band processor 404 may implement and / or be configured as a reduced instruction set computer (RISC) architecture. In another example, the in-band processor 404 may implement and / or be configured as a complex instruction set computer (CISC) architecture. Additional examples of such architectures and / or microarchitectures include, but are not limited to, 16-bit computer architectures, 32-bit computer architectures, 64-bit computer architectures, x86 computer architectures, advanced RISC machines (ARM) architectures, microprocessors without interlocked pipeline stages (MIPS) architectures, scalable processor architectures (SPARC), load-store architectures, portions of one or more of the foregoing, combinations or variations of one or more of the foregoing, and / or any other suitable architecture or microarchitecture.

[0046] In some examples, the out-of-band controller 406 may include and / or represent a hardware-implemented device and / or circuitry capable of controlling and / or modifying certain hardware features and / or components on an integrated circuit (e.g., an SoC implementing various CPU cores). In one example, the out-of-band controller 406 may include and / or represent a device and / or circuitry on-board (e.g., on-chip) and / or internal to an SoC implementing the in-band processor 404. For example, the out-of-band controller 406 may include and / or represent a system management unit implemented on-board and / or internal to the SoC. In another example, the out-of-band controller 406 may include and / or represent a baseboard management controller implemented outside (e.g., off-chip) and / or external to an SoC implementing the in-band processor 404. Additional examples of the out-of-band controller 406 include, but are not limited to, a microprocessor, a microcontroller, an FPGA, an ASIC, an integrated circuit, a die, a portion of one or more of the foregoing, a variant or combination of one or more of the foregoing, and / or any other suitable out-of-band controller.

[0047] In some examples, the term “out-of-band” may refer to any component, circuitry, and / or process dedicated to and / or supporting a control plane (e.g., control data and / or firmware), a management plane, and / or data regarding an underlying device (e.g., an SoC). In contrast, the term “in-band” may refer to any component, circuitry, and / or process dedicated to and / or supporting a user plane (e.g., user data and / or user applications) running on and / or implemented by a processor (e.g., a CPU core of an SoC). In one example, the in-band workload of an SoC may include and / or represent computational tasks performed for and / or in conjunction with user applications running on the processor, and the out-of-band workload of an SoC may include and / or represent computational tasks performed for any other purpose than being utilized and / or consumed by such user applications.

[0048] In some examples, the computing device 100 and / or the machine check architecture 102 is configured and / or equipped with one or more lines capable of transferring a manufactured error report from an external source 414 to one or more of the in-band report register 316 and / or the out-of-band report register 318 via a pipeline 212. Examples of the external source 414 include, but are not limited to, the agent 104, the in-band processor 404, the out-of-band controller 406, a portion of one or more of the foregoing, a variant or combination of one or more of the foregoing, and / or any other suitable external source 414. Thus, although not necessarily shown in this manner, the external source 414 may be the same as one of the devices that obtains, receives, and / or retrieves a manufactured error report from a report register of the machine check architecture 102. Figure 4 In that which follows, the external source 414 may be the same as one of the devices that obtains, receives, and / or retrieves a manufactured error report from a report register of the machine check architecture 102.

[0049] Figure 5Illustrates an exemplary embodiment of a computing device 100 that facilitates and / or supports injecting manufactured errors into a machine check architecture. In some examples, the computing device 100 may include and / or represent certain components and / or features that perform and / or provide functions similar and / or identical to those described above in connection with Figures 1 to 4 any of them. In one example, the computing device 100 includes and / or represents integrated circuits 502 and / or 504 communicatively coupled to each other. In this example, the integrated circuit 502 includes and / or represents a machine check architecture 102 and / or an in-band processor 404, and the integrated circuit 504 includes and / or represents an out-of-band controller 406. Thus, the integrated circuit 504 is off-chip and / or external to the integrated circuit 502. However, the integrated circuits 502 and 504 may be mounted and / or applied to the same circuit board.

[0050] In some examples, the integrated circuit 502 includes and / or represents a SoC having a number of CPU cores and a machine check architecture 102. In one example, the in-band processor 404 is on-chip and / or internal to the SoC, and the out-of-band controller 406 is off-chip and / or external to the SoC. In this example, the in-band processor 404 is able to access a copy of the manufactured error report 326 stored in the in-band report register 316, but is restricted from accessing a copy of the manufactured error report 326 stored in the out-of-band report register 318. For example, the in-band processor 404 may implement and / or execute an operating system 408 that obtains, receives, and / or retrieves a copy of the manufactured error report 326 from the in-band report register 316. Additionally or alternatively, the out-of-band controller 406 is able to access a copy of the manufactured error report 326 stored in the out-of-band report register 318, but is restricted from accessing a copy of the manufactured error report 326 stored in the in-band report register 316.

[0051] In some examples, the in-band processor 404 and the out-of-band controller 406 may make error logging decisions independently of each other. For example, the in-band processor 404 may clear a certain flag (e.g., a status flag) in the in-band report register 316 that remains set in the out-of-band report register 318. Alternatively, the out-of-band controller 406 may clear a certain flag (e.g., a status flag) in the out-of-band report register 318 that remains set in the in-band report register 316. Either way, this flag mismatch across the in-band report register 316 and the out-of-band report register 318 may result in the in-band report register 316 and the out-of-band report register 318 logging and / or ignoring different errors from the same error report. Thus, the in-band processor 404 and the out-of-band controller 406 may have independent control and / or programmability over their respective registers in the machine check architecture 102.

[0052] Figure 6 Another exemplary embodiment of computing device 100 that facilitates and / or supports out-of-band delivery of error reports is shown. In some examples, computing device 100 may include and / or represent certain components and / or features that perform and / or provide functions similar and / or identical to those described above in connection with Figures 1 to 5 any of the above. As Figure 6 shown, exemplary computing device 100 includes and / or represents integrated circuit 502 and / or integrated circuit 504 communicatively coupled to each other. In one example, integrated circuit 502 includes and / or represents machine check architecture 102, in-band processor 404, and / or out-of-band interface 604. In this example, integrated circuit 504 includes and / or represents out-of-band controller 406 communicatively coupled to out-of-band interface 604, which facilitates access to a copy of manufactured error report 326 stored in out-of-band report register 318 for out-of-band controller 406.

[0053] In some examples, out-of-band interface 604 may include and / or represent a system management unit that obtains, receives, and / or retrieves a copy of manufactured error report 326 from out-of-band report register 318. Additionally or alternatively, out-of-band controller 406 may include and / or represent a baseboard management controller that interfaces and / or communicates with the system management unit. In one example, the baseboard management controller obtains, receives, and / or retrieves a copy of manufactured error report 326 from the system management unit.

[0054] In some examples, out-of-band controller 406 and / or out-of-band interface 604 may direct and / or instruct machine check architecture 102 to perform one or more specific actions in response to a specific error identified and / or included in manufactured error report 326. For example, out-of-band controller 406 and / or out-of-band interface 604 may be programmed and / or configured to initiate and / or trigger a specific action in response to a specific error in out-of-band report register 318. In one example, the specific action may include and / or represent triggering an interruption that notifies out-of-band controller 406 of the specific error. For example, out-of-band interface 604 may be programmed and / or configured to generate an interruption that notifies out-of-band controller 406 of the specific error.

[0055] Similarly, the in-band processor 404 and / or the operating system 408 may direct and / or instruct the machine check architecture 102 to perform one or more specific actions in response to specific errors identified and / or included in the manufactured error report 326. For example, the in-band processor 404 and / or the operating system 408 may program and / or configure the in-band reporting register 316 to initiate and / or trigger a specific action in response to a specific error. In one example, the specific action may include and / or represent triggering an interruption that notifies the in-band processor 404 and / or the operating system 408 of the specific error. For example, the machine check architecture 102 and / or the in-band reporting register 316 may be programmed and / or configured to generate an interruption that notifies the in-band processor 404 and / or the operating system 408 of the specific error.

[0056] Figure 7 Illustrates an exemplary implementation 700 involving a computing system 702. In some examples, the computing system 702 may include and / or represent certain components and / or features that perform and / or provide functions similar and / or identical to those described above in connection with Figures 1 to 6 any one of. As Figure 7 shown in the exemplary implementation 700 of, the computing system 702 includes and / or represents a SoC 706 equipped with a machine check architecture 102 and / or a system management unit 708.

[0057] In some examples, the computing system 702 further includes and / or represents a baseboard management controller 710 electrically and / or communicatively coupled to the system management unit 708. In one example, the system management unit 708 obtains, receives, and / or retrieves a copy of the error report from the out-of-band register in the machine check architecture 102. In this example, the baseboard management controller 710 then obtains, receives, and / or retrieves a copy of the error report from the system management unit 708 for processing and / or facilitating decision-making.

[0058] In some examples, the various devices and / or systems described in connection with Figures 1 to 7 may include and / or represent not necessarily Figures 1 to 7One or more additional circuits, components, and / or features shown and / or marked therein. For example, computing device 100 may also include and / or represent additional analog and / or digital circuits, on-board logic components, transistors, resistors, capacitors, diodes, inductors, switches, registers, flip-flops, connections, traces, buses, semiconductor (e.g., silicon) devices and / or structures, processing devices, storage devices, circuit boards, packages, substrates, enclosures, combinations or variations of one or more of the foregoing, and / or any other suitable components that facilitate and / or support injecting manufacturing errors into the machine check architecture. In certain specific implementations, one or more of these additional circuits, components, devices, and / or features may be inserted and / or applied between any of the existing circuits, components, and / or devices shown in Figures 1 to 7 therein. Thus, the electrical and / or communication couplings described with reference to Figures 1 to 7 may be direct connections without intermediate components, devices, and / or nodes, or indirect connections with one or more intermediate components, devices, and / or nodes.

[0059] In some examples, as used herein, the phrase "for coupling" and / or the term "coupled" may refer to direct connection and / or indirect connection. For example, a direct coupling between two components may constitute and / or represent a coupling in which the two components are directly connected to each other through a single node that provides electrical continuity from one of the two components to the other. In other words, a direct coupling may exclude and / or omit any additional components between the two components.

[0060] Additionally or alternatively, an indirect coupling between two components may constitute and / or represent a coupling in which the two components are indirectly connected to each other through multiple nodes that do not provide electrical continuity from one of the two components to the other. In other words, an indirect coupling may include and / or incorporate at least one additional component between the two components.

[0061] Figure 8 is a flowchart of an exemplary method 800 for injecting manufacturing errors into the machine check architecture. In one example, Figure 8 the steps shown therein may be performed and / or implemented during the manufacturing, assembly, configuration, and / or operation of a computing device and / or system. Additionally or alternatively, Figure 8 the steps shown therein may also incorporate and / or involve various sub-steps and / or variations consistent with the description provided above in connection with Figures 1 to 7 thereof.

[0062] As Figure 8As shown, the exemplary method 800 includes and / or involves a step (810) of configuring at least one error injection register of a circuit in a machine check architecture. Step 810 can be performed in various ways, including any of the ways described above in connection with Figures 1 to 7 any of those ways described. For example, a portion of a computing device can configure and / or instantiate at least one error injection register of a circuit in a machine check architecture. In one example, the machine check architecture and / or circuit of a computing device can set and / or clear certain bits of an error injection register to indicate and / or reflect a certain state (e.g., a state in which no manufactured errors are pending).

[0063] The exemplary method 800 further includes and / or involves a step (820) of detecting a write operation performed on at least one bit of an error injection register. Step 820 can be performed in various ways, including any of the ways described above in connection with Figures 1 to 7 any of those ways described. For example, a computing device can monitor and / or check any write operations performed on an error register. In one example, when monitoring and / or checking such write operations, an error detector of a machine check architecture can detect a write operation performed on at least one bit of an error injection register.

[0064] The exemplary method 800 further includes and / or involves a step (830) of injecting at least one manufactured error report into at least one report register in a machine check architecture in response to the write operation. Step 830 can be performed in various ways, including any of the ways described above in connection with Figures 1 to 7 any of those ways described. For example, a computing device can inject and / or insert at least one manufactured error report into at least one report register in a machine check architecture in response to the write operation. In one example, an error detector of a machine check architecture can generate at least one manufactured error report and then input it into a pipeline of the machine check architecture, which carries the manufactured error report to the report register.

[0065] Although the foregoing disclosure has set forth various specific implementations using specific block diagrams, flowcharts, and examples, each block diagram component, flowchart step, operation, and / or component described and / or shown herein can be implemented individually and / or jointly using various hardware, software, or firmware (or any combination thereof) configurations. Additionally, any disclosure of components contained within other components should be considered exemplary in nature, as many other architectures can be implemented to achieve the same functionality. Furthermore, the various steps, events, and / or features performed by such components should be considered exemplary in nature, as many alternatives and / or variations can be implemented within the scope of this disclosure to achieve the same functionality.

[0066] The order of process parameters and steps described and / or illustrated herein is given by way of example only and may vary as needed. For example, although the steps illustrated and / or described herein are shown or discussed in a particular order, these steps need not necessarily be performed in the order illustrated or discussed. The various exemplary methods described and / or illustrated herein may also omit one or more of the steps described or illustrated herein, or include additional steps other than those disclosed.

[0067] The foregoing description has been provided so that others skilled in the art may best utilize the various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or limited to any precise form. Many modifications and variations are possible without departing from the spirit and scope of the disclosure. The exemplary embodiments disclosed herein should be considered illustrative rather than restrictive in all respects. When determining the scope of the disclosure, reference should be made to the appended claims and their equivalents.

[0068] Unless otherwise indicated, the terms "connected to" and "coupled to" (and their derivatives) as used in the specification and claims will be deemed to allow both direct and indirect (i.e., via other elements or components) connections. Additionally, the term "a" or "an" as used in the specification and claims will be deemed to mean "at least one". Finally, for convenience, the terms "comprising" and "having" (and their derivatives) as used in the specification and claims may be interchanged with the word "including" and have the same meaning.

Claims

1. A system, the system comprising: An agent; And A machine check architecture, the machine check architecture comprising: At least one circuit configured to report an error via at least one report register; And At least one error injection register configured to cause the circuit to inject at least one fabricated error report into the report register in response to a write operation performed by the agent on at least one bit of the error injection register.

2. The system according to claim 1, wherein: The circuit includes a plurality of circuits; and The error injection register includes a plurality of error rejection registers.

3. The system according to claim 1, wherein the machine check architecture includes a pipeline configured to carry the error report from the circuit to the report register; and The error injection register is configured to cause the circuit to inject the fabricated error report into the pipeline for transmission to the report register.

4. The system according to claim 3, wherein the circuit includes one or more lines configured to transmit another fabricated error report from an external source to the report register via the pipeline.

5. The system according to claim 3, wherein the report register includes: A first report register configured to: Receive a first copy of the fabricated error report via a first channel of the pipeline; And Store the first copy of the fabricated error report for access by an in-band processor; And A second report register configured to: Receive a second copy of the fabricated error report via a second channel of the pipeline; And Store the second copy of the fabricated error report for access by an out-of-band controller.

6. The system according to claim 1, wherein the agent includes software or firmware running on a processor having access to the error injection register.

7. The system according to claim 6, further comprising an integrated circuit including the processor and the machine check architecture.

8. The system according to claim 1, wherein the agent includes an out-of-band controller having access to the error injection register.

9. The system according to claim 8, the system further comprising: A first integrated circuit including the out-of-band controller; And A second integrated circuit including the machine check architecture.

10. The system according to claim 9, wherein the out-of-band controller includes a baseboard management controller external to the second integrated circuit.

11. The system according to claim 1, wherein the circuit: Includes a table configured to: Store a plurality of error entries; and Map the bits of the error injection register to specific error entries included in the error entries; and Is configured to generate the fabricated error report for injection at least in part based on the mapping of the bits to the specific error entries.

12. The system according to claim 1, wherein the error injection register is further configured to cause the circuit to inject another fabricated error report into the report register in response to another write operation performed by the agent on at least one other bit of the error injection register.

13. The system according to claim 1, further comprising an out-of-band controller configured to perform a specific action in response to a specific error identified in the fabricated error report injected into the report register.

14. The system according to claim 13, wherein the specific action includes triggering an interruption to notify at least one other circuit of the specific error.

15. The system according to claim 14, wherein the other circuit includes at least one of the following: a processor disposed on an integrated circuit including the machine check architecture; or a baseboard management controller external to the integrated circuit including the machine check architecture.

16. A machine check architecture, the machine check architecture comprising: at least one circuit configured to report an error to a report register; a pipeline configured to carry the error report from the circuit to the report register; and at least one error injection register configured to cause the circuit to inject at least one fabricated error report into the report register via the pipeline in response to a write operation performed by an external source on at least one bit of the error injection register.

17. The machine check architecture according to claim 16, wherein: the circuit includes a plurality of circuits; and the error injection register includes a plurality of error rejection registers.

18. The machine check architecture according to claim 16, wherein the circuit includes one or more lines configured to transfer another fabricated error report from the external source to the report register via the pipeline.

19. The machine check architecture according to claim 16, wherein the report register includes: a first report register configured to: receive a first copy of the fabricated error report via a first channel of the pipeline; and store the first copy of the fabricated error report for access by an in-band processor; and a second report register configured to: receive a second copy of the fabricated error report via a second channel of the pipeline; and store the second copy of the fabricated error report for access by an out-of-band controller.

20. A method, the method comprising: configuring at least one error injection register of a circuit in a machine check architecture; detecting a write operation performed on at least one bit of the error injection register; and in response to the write operation, injecting at least one fabricated error report into at least one report register in the machine check architecture.

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