Evaluating health of unitary component carrier

Abstract

There is described a monolithic component carrier (100) comprising: a stack (101) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (102); wherein at least one electrically conductive layer structure (104) comprises a sub-portion (150), i) wherein the sub-portion (150) is electrically separated or can be electrically separated from the remainder of the electrically conductive layer structure (104); ii) wherein the sub-portion (150) comprises a region (155) that deteriorates over time; iii) wherein the sub-portion (150) comprises two ends, and iv) wherein each of the ends is electrically connected to a respective connection region (140) exposed on one of the main surfaces of the at least one electrically insulating layer structure (102). Furthermore, a package, an electronic panel and a method for assessing the health of a monolithic component carrier (100) are described.

Description

Technical Field

[0001] The present invention relates to a monolithic component carrier having a stack, the stack having an electrically conductive layer structure with specific sub - parts. The present invention also relates to a package and an electronic panel correspondingly including the monolithic component carrier. In addition, the present invention relates to a method for inspecting the health of a monolithic component carrier, and in particular, the present invention relates to a method for inspecting the health of a monolithic component carrier using a test device.

[0002] Accordingly, the present invention may relate to the technical field of component carriers such as printed circuit boards and IC substrates, especially in terms of testing the health status of monolithic component carriers. Background Art

[0003] In situations where the product functions of component carriers equipped with one or more electronic components are growing continuously, such electronic components are becoming increasingly miniaturized, and the number of electronic components to be mounted on component carriers such as printed circuit boards is increasing, more and more powerful array - like components or packages having several electronic components are being adopted. The array - like components or packages have a plurality of contact parts or connection parts, and the pitch between these contact parts is getting smaller and smaller. Removing the heat generated by such electronic components and their component carriers during operation has become an increasingly serious problem. At the same time, the component carrier should be mechanically robust and electrically and magnetically reliable so as to be operable even under severe conditions.

[0004] In particular, the health monitoring of component carriers such as printed circuit boards and IC substrates has received increasing attention. Generally, component carrier products do not include any active / passive health monitoring features. The investigations and research and development carried out in this field are also very limited, such that there may generally be no suitable health monitoring for component carrier (products), especially regarding the prediction of the remaining useful life (RUL). Summary of the Invention

[0005] It may be desirable to evaluate the health status of a monolithic component carrier in an efficient and reliable manner.

[0006] Component carriers, packages, electronic panels, and methods are provided.

[0007] According to a first aspect of the present invention, a monolithic component carrier is described. The monolithic component carrier includes a stack (in particular, including a plurality of layer structures). The stack includes at least one electrically conductive layer structure (for example, a region and / or a volume part of metal traces) and at least one electrically insulating layer structure (for example, a resin layer). Here, at least one electrically conductive layer structure includes sub - parts.

[0008] i) The sub - part is electrically separated from or can be electrically separated from the rest of the electrically conductive layer structure;

[0009] ii) The sub - part includes a region / zone that deteriorates over time,

[0010] iii) The sub - part includes two ends (e.g., with respect to a corresponding loop defined by the sub - part of the electrically conductive layer structure or with respect to a thickness extension), and

[0011] iv) Each of the ends is electrically connected to a respective connection region that is located on (in particular, on the same) one of the main surfaces of at least one electrically insulating layer structure (exposed).

[0012] According to a second aspect of the invention, a package is described, wherein the package includes: i) a monolithic component carrier as described above, and ii) a test device, wherein the test device is electrically connected to and / or can be electrically connected to the (exposed) connection regions.

[0013] According to a third aspect of the invention, an electronic panel is described, the electronic panel including a stack that includes at least one electrically conductive layer structure and at least one electrically insulating layer structure, and the stack is configured to be subsequently monomerized into a plurality of monolithic component carriers (in particular, monomerized into a plurality of identical monolithic component carriers), each of the plurality of monolithic component carriers being configured as the monolithic component carrier as described above.

[0014] According to a fourth aspect of the invention, a method for evaluating the health of a monolithic component carrier (in particular, the monolithic component carrier as described above) is described, the monolithic component carrier including a stack that includes at least one electrically conductive layer structure and at least one electrically insulating layer structure, wherein a sub - part of at least one electrically conductive layer structure includes a region and / or zone that deteriorates over time, wherein the sub - part includes two ends, and wherein each of the ends is connected to a respective connection region provided on one of the main surfaces of at least one electrically insulating layer structure. The method includes:

[0015] i) Providing a test device and connecting the test device to the respective (exposed) connection regions (in particular, by connecting the test probes of the device and the respective exposed connection regions);

[0016] ii) Measuring an electrical value (parameter) associated with the sub - part; and

[0017] iii) Evaluating the health of the monolithic component carrier based on the measured electrical value.

[0018] According to a fifth aspect of the present invention, a computer-readable medium is described, in which a computer program for evaluating the health status of a monolithic component carrier is stored, and the computer program is adapted to implement or control the method as described above when executed by one or more processors.

[0019] According to a sixth aspect of the present invention, a program element for evaluating the health status of a monolithic component carrier is described, and the (computer) program element is adapted to implement or control the method as described above when executed by one or more processors.

[0020] In the context of this document, the term "component carrier" may in particular refer to any support structure capable of accommodating one or more components thereon and / or therein to provide mechanical support and / or electrical connection. In other words, the component carrier can be configured as a mechanical and / or electronic carrier for components. In particular, the component carrier can be one of a printed circuit board, an organic interposer, and an IC (integrated circuit) substrate. The component carrier can also be a hybrid board that combines different component carriers of the above types of component carriers.

[0021] In the context of this document, the term "monolithic component carrier" may in particular refer to a component carrier (see definition above), where the main manufacturing steps for the shaping of the component carrier, in particular all manufacturing steps, have been completed. For example, a monolithic component carrier may be regarded as the final product of component carrier manufacturing, in particular a product ready to be shipped to a customer or a product that has already been shipped to a customer. A monolithic component carrier may be a discrete component carrier that is not interconnected with other component carriers, as may occur during component carrier manufacturing. For example, a monolithic component carrier may be a component carrier after monolithization / cutting of a component carrier panel. Thus, a monolithic component carrier may be, for example, a component carrier on which appropriate components have been mounted on one or more (main) surfaces. Thus, a monolithic component carrier may already be suitable for installation in a final seating / position. In an example, a monolithic component carrier has a single structure and a single function within the carrier itself that does not repeat like a (regular, patterned) series of electrically conductive layer structures that are identical to each other, such that the parts of the carrier may allow for subsequent monolithization of well-functioning sub-carriers. In a further example, a monolithic component carrier may have an outer peripheral surface that does not expose electrically conductive parts, with the ultimate exception of an electrically conductive structure (preferably located on one of the two main surfaces of the component carrier) that is configured to allow for electrical connection of connector devices and / or components assembled on the outer peripheral part of the component carrier (if the monolithic component carrier is, for example, an interposer or can be connected to a motherboard, then additional PCBs or IC substrates may also be connected). In a further example, a monolithic component carrier may have an external planar profile that follows the external planar extension of the electrically conductive layer structure, with the ultimate exception of areas suitable for the assembly / strengthening of the component carrier.

[0022] In the context of this document, the term "sub-part" may in particular refer to a part of an electrically conductive layer structure (e.g., a patterned copper surface) that may be defined as being (electrically) separated from the rest of the electrically conductive layer structure. In an example, the sub-part extends on a common plane (e.g., the main surface of a monolithic component carrier). In another example, the sub-part extends at the same vertical position (with respect to the stack thickness direction) as the rest of the electrically conductive layer structure. In another example, the sub-part may be located on the outer peripheral part of the component carrier (with respect to its position on the main extension). Additionally and / or alternatively, the sub-part may be located on the central part of the component carrier (with respect to its position on the main extension).

[0023] In the context of this document, the term "peripheral part" may refer to a local position of a component carrier or an electronic panel, which is close to the edges of the main surface and the sidewalls of the component carrier or the electronic panel. For example, the shortest distance from the peripheral part to the edges of the main surface and the sidewalls (on the main surface) may be 40%, particularly 20%, more particularly 10% shorter than the distance from the same position to the center of the entire area of the main surface of the component carrier or the electronic panel.

[0024] In the context of this document, the term "central part" may refer to a local position of a component carrier or an electronic panel, which is close to the center of the entire area of the component carrier or the electronic panel. For example, the shortest distance from the central part to the center of the entire area (on the main surface) may be 40%, particularly 20%, more particularly 10% shorter than the distance from the same position to the edges of the main surface and the sidewalls of the component carrier or the electronic panel.

[0025] In the context of this document, the term "separated or separable" may particularly refer to the relationship between the sub - part defined above and the rest of the electrically conductive layer structure. In an example, the sub - part may be separated by being electrically isolated from the rest of the corresponding electrically conductive layer structure. In another example, the sub - part may be part of the same (electrically conductive) layer structure (the sub - part has been manufactured in the same processing step and with the same materials / parameters), but is separated by patterning such that the sub - part and the rest of the electrically conductive layer structure are segmented. In another example, the sub - part may be an additional conductive part that at least partially overlaps the rest of the corresponding electrically conductive layer structure along the thickness direction of the stack. In another example, the electrically conductive layer structure may be separable to allow the sub - part to be separated from the rest of the electrically conductive layer structure when a current is provided through the two ends of the sub - part, for example, by using a suitable diode to block the current leading to the rest of the electrically conductive layer structure.

[0026] In the context of this document, the term "region that degrades over time (or as time progresses)" can particularly refer to a part (region, section, volume part) of a sub - part that can be regarded as being particularly prone to degradation; in other words: having a higher risk of degradation / corrosion than other regions / zones of the monolithic component carrier. The remaining useful life (RUL) of a "region that degrades over time" may be (significantly) shorter than that of other regions / zones of the monolithic component carrier. Examples of such a "region that degrades over time" can be regions with a small width (of traces) or high - density patterning. Another example can be a region of the sub - part that is in contact / joined / welded to other regions (e.g., at an interface), which eventually has characteristics of separation, such as different materials or different shapes or is manufactured in different process steps, or the region includes different specific surface features, such as roughness, surface tension, the presence of additives, etc.

[0027] The term "degradation" can particularly refer in the context to a reduction in the area of a region of a sub - part, for example, a reduction in the current - passing area and / or the contact / joining / welding area between the sub - part and another region. In particular, degradation may affect the electrical value (measured by a test device) of the current path. In an example, degradation may be caused by a chemical reaction with the environment, for example, due to oxidation by air. In another example, degradation may be caused by long - term power use, for example, use for more than a month, particularly use for more than a year. Degradation can lead to a change in the cross - sectional area (or zone), for example, a reduction in the cross - sectional area (or zone).

[0028] The term "connection region" can refer in the context to an electrically conductive region (such as a pad, terminal, etc.) that is electrically connected to the sub - part to be tested. Thus, via the connection region, the sub - part can be electrically contacted even if the sub - part may be (completely) embedded in the stack. According to an additional or alternative embodiment, the connection region can be formed by a (non - continuous) electrically conductive layer structure. In another example, the connection region can be electrically connected to the sub - part by additional (test - related) interconnects such as vias. In a specific example, the connection region has a square shape, aiming to, for example, use as much of the available component carrier surface as possible; more specifically, the square test area of the connection region can be 1 mm * 1 mm (or smaller). In the present invention, the provision of other shapes is not excluded in any case, such as circular, rectangular, or irregular shapes. According to an alternative or additional embodiment of the present invention, the shape of the connection region can have different shapes and / or different dimensions and / or different materials / colors / roughnesses, that is, in order to clearly distinguish the connection region provided for test reasons from other regions provided for other functions on the same side of the component carrier.

[0029] In an embodiment, the surface of the stack / component carrier may include a plurality of exposed connection areas, which are preferably arranged in an array. Thus, a large number of electrically conductive interconnects (arrangement structures) can be tested (individually) from the same component carrier side, even if at least some of the electrically conductive interconnects may be buried in the stack.

[0030] According to an exemplary embodiment, the present invention may be based on the concept that the health status of a monolithic component carrier can be evaluated in an effective and reliable manner by a sub - portion of the electrically conductive layer structure (of the component carrier stack), which sub - portion includes an area that deteriorates over time; this sub - portion is electrically connected to the exposed connection areas to obtain an electrical value (such as resistance) that indicates the health status of the sub - portion (especially the area that deteriorates over time).

[0031] For example, the measurement of the electrical value of a sub - portion (e.g., a single via) may be sufficient to reliably evaluate the health status of a monolithic component carrier and allow prediction of the remaining useful life, especially in critical applications (such as power PCBs in critical infrastructure). Based on the described health status assessment, planned maintenance of critical infrastructure can be enabled. The health status assessment can be achieved through a simple electronic design, has low space requirements, and can be applied to any standard component carrier without the need for new processes.

[0032] Surprisingly, the measured electrical value, such as resistance, of an appropriate sub - portion of the electrically conductive layer structure can be reliably correlated with the health status of the sub - portion having an area that deteriorates over time, such as a via interconnect. Thus, for example, when damage propagates in a via (e.g., crack propagation), the available electrical conduction cross - section decreases and the total resistance of the via feature increases (see Figure 3 ).

[0033] As long as this relationship (e.g., the so - called damage curve) can be described as a specific characteristic, the electrical value can be used as a measure of the health status. If the geometry of the sub - portion is defined in an appropriate manner (e.g., the via feature has a diameter that is not greater than or even slightly less than the functional vias in the component carrier) and the position of the sub - portion in the component carrier, the sub - portion can be regarded as representative of the health status of the complete monolithic component carrier.

[0034] During the operation of the component carrier, especially if the component carrier is applied in applications with a long service life, sub - portion testing allows identification of the health status of the component carrier and even evaluation of the remaining useful life of the component carrier (e.g., based on the physical principles of failures of copper interconnects and / or simulation of component carrier life prediction).

[0035] For the entire electronic system, such an assessment can allow for defining / adjusting appropriate maintenance strategies and avoiding unexpected failures and costly downtimes of critical infrastructure.

[0036] Exemplary Embodiment

[0037] In an embodiment, one or more exposed connection areas are configured to be tested by a four-wire test (FWT) function. This can provide the advantage that established measuring devices can be used to determine electrical values, in particular the resistance of (individual) electrically conductive interconnects, in a reliable and efficient manner.

[0038] A four-wire test can be performed using a current measuring device and a voltage measuring device to indirectly determine the resistance based on the current and voltage. The name FWT is explained by the two wires used by the current measuring device and the other two wires used by the voltage measuring device. In particular, each device contacts two different areas corresponding to the two ends (e.g., top and bottom) of the connection element (via) to be tested; otherwise, a short circuit might be formed if two wires were connected to a single connection area.

[0039] Thus, by using known test devices connected to the connection areas in a monolithic component carrier, the areas of the separable or separable sub-parts of the electrically conductive layer structure connected to areas that deteriorate over time allow for reliable and easily implementable health monitoring of the component carrier without additional and / or more complex and / or costly solutions and / or devices.

[0040] In an example, there are four exposed connection areas at the main surface, and each connection area is physically contacted by one of four wires respectively. Using the architecture of the monolithic component carrier as described above, each wire can electrically contact the corresponding end of the sub-part to be tested (via the connection area).

[0041] In another embodiment, each of the ends is electrically connected to a corresponding connection area exposed on one main surface of the stack (in particular on the same main surface). This can provide the advantage of more accurate measurement results using the measuring device. In addition, it may be easier to electrically connect the test device, in particular the wires of the four-wire test device, in a reliable manner.

[0042] In an example, the electrically insulating layer structure connecting the ends of the sub-part corresponds to the outer layer (at the main surface) of the stack. In another example, the connection area can be located on one main surface of an inner layer of the stack. For example, this is the case for a test device that is at least partially embedded in the monolithic component carrier.

[0043] In another embodiment, the sub - part includes at least one test electrical conduction interconnect extending along the thickness direction (stacking direction, vertical direction z) of the stack. Thus, a firm, easily manufacturable and effective connection to the connection area can be achieved.

[0044] The term "test electrical conduction interconnect" can, in context, denote an electrical conduction structure suitable for connecting at least two electrical conduction (layer) structures (in a component carrier stack). In a preferred example, the electrical conduction interconnect can be a vertical electrical conduction interconnect, such as a blind via in a stack of component carriers. The test electrical conduction interconnect can be provided on the active area of the component carrier, where the electrical conduction structure and / or one or more components can be connected or connectable to each other via the electrical conduction interconnect. The test electrical conduction interconnect can be suitable for performing electrical tests on electrical parameters (such as voltage, current, resistance), in particular via one or more leads and / or connection elements of a measuring device. In an example, the degradation area can be the connection area / zone between a sub - part of the electrical conduction layer structure and the test electrical conduction interconnect.

[0045] In another embodiment, at least one of the test electrical conduction interconnects includes two opposite ends (in particular, the two ends correspond to the two ends of the sub - part). In particular, the first end is electrically connected to one of the at least two exposed connection areas, and / or the second end is electrically connected to the other of the at least two corresponding connection areas. Thus, a particularly effective electrical contact can be achieved. Additionally, this can have the advantage that the electrical value of the entire test electrical conduction interconnect can be reliably measured, since a test device, such as a four - wire test device, can be connected or connectable at the two opposite ends.

[0046] In an example, the sub - part includes a test electrical conduction interconnect having two ends. These can be directly connected (through the thickness direction of the stack) to the exposed connection areas. In another example, the test electrical conduction interconnect can be a separate structure that can be electrically connected to the two ends of the sub - part. For example, the test electrical conduction interconnect can thus connect the (embedded) sub - part to the exposed connection areas.

[0047] In another embodiment, the stack includes at least two electrical conduction layer structures and at least two sub - parts respectively corresponding to the two electrical conduction layer structures. In particular, the sub - parts are connected to each other via the at least one test electrical conduction interconnect, and / or each of the sub - parts is connected and / or integrated with a corresponding exposed connection area. Such an architecture can enable an efficient and design - flexible interconnect between the sub - parts for reliable electrical testing, especially in the well - known process of manufacturing component carriers formed by stacked layer structures.

[0048] In an example, the sub - parts may be at different vertical levels along the thickness direction of the stack. In another example, the sub - parts may be arranged at the same vertical level. In an example, the degradation region may be the connection region / zone between a sub - part of the electrically conductive layer structure and the test electrically conductive interconnect.

[0049] In another embodiment, the component carrier includes: a plurality of electrically conductive interconnects in the stack, the electrically conductive interconnects being electrically connected to at least one electrically conductive layer structure. In particular, at least one of the test electrically conductive interconnects has the same mechanical / chemical characteristics, and / or, in terms of depth, at least one of the test electrically conductive interconnects has the same position as at least one of the plurality of electrically conductive interconnects.

[0050] When a specific architecture is provided, the quality of the electrically conductive interconnects in a monolithic component carrier can be evaluated in an effective, accurate, and reliable manner by testing the test electrically conductive interconnects provided in a dedicated test area, without affecting the function or mechanical integrity of the electrically conductive interconnects and / or the electrically conductive structure and / or one or more of the components.

[0051] In particular, due to the fact that the test electrically conductive interconnects have common characteristics relative to the (active) electrically conductive interconnects, a sub - part can be constructed in / on the monolithic component carrier that is adjacent to other elements and has the same / similar characteristics as other elements, and this sub - part is determined to be the part that is more sensitive / more affected by degradation over time; in this way, the health of the monolithic component carrier can be evaluated, and specific areas / components can be inspected intensively.

[0052] The term "electrically conductive interconnect" may, in context, refer to an electrically conductive interconnect provided as a test electrically conductive interconnect in different regions of the component carrier, which includes characteristics equivalent to those of the test electrically conductive interconnect. In an example, the electrically conductive interconnects may be arranged at equivalent / similar vertical (along z) positions in the stack (as the test electrically conductive interconnects). In another example, the electrically conductive interconnects include mechanical / electrical / chemical characteristics equivalent / similar to those of one or more test electrically conductive interconnects and / or equivalent / similar geometric structures. In a preferred embodiment, all the mentioned parameters may be equivalent / similar.

[0053] Multiple electrically conductive interconnects may be arranged in a stack. In an example, at least two electrically conductive interconnects may be arranged side by side (at least partially) at the same vertical level in the stack. Thus, the electrically conductive interconnects may be electrically connected to each other, for example, through an electrically conductive layer structure of the stack. In an example, lower ends of at least two electrically conductive interconnects are electrically connected through a continuous electrically conductive layer structure of the stack, while upper ends may be electrically connected through a discontinuous electrically conductive layer structure.

[0054] In another embodiment, (electronic) components (such as active or passive components, particularly semiconductor elements) are provided on or embedded in the stack. In particular, at least one of the test electrically conductive interconnects is connected to the component.

[0055] When a particular architecture is provided, the quality of the electrically conductive interconnects in a monolithic component carrier and the quality of their interaction (i.e., connection) with the components can be evaluated in an efficient, accurate, and reliable manner through test electrically conductive interconnects connected to the surface of the components, without affecting the function or mechanical integrity of the electrically conductive interconnects and / or the electrically conductive structure and / or one or more of the components.

[0056] In an example, the degradation region may be the connection region / zone between the component and the test electrically conductive interconnect.

[0057] In an example, further embodiments of this concept may include an actual component or package, where a sub - part may include a monolithic solder interconnect between the component and a carrier board, and where parts of the sub - part are located in the mold or RDL, while parts of the structure are located at the component carrier. If such features are placed in a stress - critical region, such as at the corner of the mold, then this may allow monitoring the health of the component carrier / mold interconnect.

[0058] In another embodiment, the monolithic component carrier further includes a plurality of additional components (active or passive) and a plurality of electrically conductive interconnects connected to the additional components, where the components have regions of the same mechanical / chemical characteristics, and / or, in terms of depth, the components have the same position as a corresponding one of the plurality of additional components. The quality of the plurality of electrically conductive interconnects in the monolithic component carrier and their interaction (i.e., connection) with the corresponding plurality of additional components can be evaluated in an effective, accurate, and reliable manner.

[0059] Thus, since the interface between the test electrical conduction interconnect and the component has common characteristics with the (active) electrical conduction interconnect of the (active) component, a sub - part can be constructed in / on the monolithic component carrier, which is close to other components and has the same / similar characteristics as other components. The sub - part is determined to be the part that is more sensitive / more affected by degradation over time; in this way, the health of the monolithic component carrier can be evaluated, and specific areas / components can be inspected intensively.

[0060] In another embodiment, one end, especially each end, of the sub - part and / or the test electrical conduction interconnect is connected to two or more corresponding connection areas. This design can be particularly suitable for four - wire testing.

[0061] In another embodiment, multiple electrical conduction interconnects and / or test electrical conduction interconnects are constructed as at least one of blind vias, through - holes, plated through - holes, interconnects between component carriers, wires, nanowires, sputtered materials, solder materials, and electrically conductive adhesives. The advantage of this can be that multiple different electrical conduction interconnects can be tested using the same (resistance) test method.

[0062] In an example, the stack of the component carrier is formed by stacking multiple layers, for example, by laminating (insulating layer structure) and plating (conductive layer structure). In another example, the stack is formed by multiple sub - stacks, and the sub - stacks are interconnected, for example, by electrically conductive adhesives.

[0063] In another embodiment, multiple sub - parts and / or test electrical conduction interconnects are provided. The advantage of this can be that electrical values related to different parts of the component carrier or the electronic panel are measured, so as to evaluate the health of the monolithic component carrier in an accurate and reliable manner.

[0064] In another embodiment, the test electrical conduction interconnects are arranged at different positions with respect to the stacking direction (z) of the stack, especially one on top of the other. The advantage of this can be that multiple electrical conduction interconnects can be (individually) tested, especially if the electrical conduction interconnects are buried deep in the stack or (partially) exposed on the surface and are independent. For example, in the case of many layers or even multiple sub - stacks, it may be challenging to reliably test all the (interesting) electrical conduction interconnects. However, the described method can achieve such testing in different layers.

[0065] In another embodiment, the connection between at least one end of the two ends of the sub - part and / or the test electrical conduction interconnect and the corresponding connection area includes at least one via interconnect. Therefore, the established component carrier (manufacturing) technology can be directly applied.

[0066] In another embodiment, connection regions (in particular connection regions exposed with respect to the stack) are repeatedly provided on the main surface of the electrically insulating layer structure (in particular on the main surface of the stack), thereby forming an array, in particular an array along one or more linear directions. This can provide the advantage of optimizing the area for the test region. Preferably, the repetition of the connection regions also corresponds to the repetition of the electrically conductive interconnects for testing, each electrically conductive interconnect for testing preferably having two ends connected to a respective connection region, resulting in a more reliable health assessment due to the statistical use of the (electrical) measurements taken on all of the plurality of electrically conductive interconnects for testing.

[0067] In another embodiment, the test device is mounted on or integrated into the component carrier. This can provide the advantage that a highly versatile component carrier can be provided in a compact manner.

[0068] In another embodiment, the test device of the encapsulation includes a four-wire test device (see above). Thus, the simple setup of the four-wire test device can reliably measure electrical values.

[0069] In a further embodiment of the electronic panel, the stack is configured to include a pattern portion and / or more than one pattern portion having repetitive features (such as components, electrically conductive layer structures, recesses, etc.), the patterns defining a plurality of monolithic component carriers, and the pattern portion is configured to be subsequently monomerized into a plurality of monolithic component carriers and / or subsequently divided into sub-pattern portions. This can bring the advantage of using reliable PCB and / or IC substrate manufacturing processes, so that the amount of scrapped parts remains low.

[0070] In another embodiment, the electrical value corresponds to or is associated with the resistance value of the current passing through the sub-part, in particular the resistance value of the current passing through the connection between the test device and one or more exposed connection regions. Thus, the resistance can be measured in a practical and reliable manner to obtain information related to the health state of the monolithic component carrier.

[0071] In another embodiment, the test device is separated from / separable from the monolithic component carrier, and measurements are made through the connection between the test device and the exposed connection region. For example, the test device can be an independent test device provided automatically or manually to the monolithic component carrier to be tested. This method can be particularly flexible. In other words, a precise and highly reliable test device can be used to test the health of the monolithic component carrier, but due to its cost and / or burden, the monolithic component carrier can be constructed to allow temporary contact and then the carrier can be tested temporarily.

[0072] In another embodiment, the test device is mounted on or integrated into the monolithic component carrier such that the measurement is carried out via a fixed connection between the test device and the exposed connection area. This method can be particularly practical because the test device can already be integrated into the monolithic component carrier and thus be ready at any time when needed. This embodiment can also allow for the integration of inexpensive but compact test devices, for example, balancing the (electrical) measurement accuracy with the compactness of the solution and eliminating the need for external entity connections (also preferably preventing oxidation defects due to the connection of the test device).

[0073] In another embodiment, the measurement of the electrical value of the sub - part is carried out according to a time schedule. Thus, the health of the monolithic component carrier can be monitored in a particularly reliable manner. The time schedule can, for example, include the test performance at specific time steps; for example, after a specific period of time, the next electrical value measurement should be performed. This results in a preferred possibility to evaluate the deterioration trend of the sub - part and thus the trend of the health of the monolithic component carrier, allowing a specific evaluation that is not limited to single and / or instantaneous measurements.

[0074] In another embodiment, the measurement of the electrical value of the sub - part is carried out by receiving an input command, for example, manually or automatically by a (human) operator. The advantage of this is to ensure the correct execution of the (electrical) measurement.

[0075] In another embodiment, the assessment of the health of the monolithic component carrier is carried out by combining the measured electrical value with a damage curve, in particular using stored values that define the damage curve. Such a damage curve can be a suitable method for quickly and effectively evaluating the health status based on the measured electrical value. For example, the damage curve can be a graph showing the correlation between the resistance and the health status to be monitored, for example, showing the current part of the electrical interconnection. Thus, the measured resistance can indicate the health status, for example, indicating the remaining part of the electrical interconnection. Figure 3 Exemplary embodiments of the damage curve are described.

[0076] In another embodiment, the assessment of the health of the monolithic component carrier includes an assessment of the remaining time for the monolithic component carrier to meet specific threshold conditions (for example, ensuring a minimum current passing value). The advantage of this can be that the health status obtained based on the electrical value measurement can be directly used for the quality assessment and planning of component carrier replacement.

[0077] In an example, one possibility to implement resistance measurement is to provide connection areas (e.g., measurement pads) on the outer layer of the component carrier, which can be manually measured in a four-wire manner after a defined period of time or a defined workload. Another option is to directly connect the measurement electronics (e.g., SMT-mounted) to the four wires of each sub-part (e.g., via). This will allow not only discrete measurement intervals but also real-time monitoring of the sub-parts.

[0078] According to an exemplary embodiment, a single-via-based health monitoring that can be implemented into the component carrier design is described. The health assessment of the component carrier can be performed by measuring the resistance of a single via feature in a four-wire method. The resistance is related to a known resistance and a damage curve of the realized via diameter. This allows the remaining useful life of the component carrier to be evaluated, thereby optimizing the maintenance plan of critical component carriers.

[0079] According to an exemplary embodiment, a health monitoring system for a PCB and a substrate based on monitoring the resistance of a characteristic component of a monolithic electronic component carrier is described, where the characteristic component is such as a laser via or a plated-through hole. Measuring a single via in a four-wire setup can allow the influence of the measurement setup to be ignored, obtaining only the resistance of the via, or more generally only the characteristic. The change in the resistance of a single via is directly related to the change in the via condition. For example, an increase in the via resistance indicates a deterioration in the via health and represents additional damage introduced into the via material as the board's service life progresses, such additional damage being caused, for example, by thermo-mechanical stress. If these vias are placed in specific and carefully chosen areas of the board and the resistance monitoring is performed routinely over a period of time, either manually through external measurements or automatically through, for example, SMT-mounted measurement electronics, then the health state of the vias can serve as an indicator of the health state of the entire component carrier. Thus, the remaining useful service life can be evaluated / assessed. The resistance of each (relevant) single via in the component carrier can be measured in a four-wire setup. For example, a multilayer board can include multiple monolithic via specimens at different layers of the board, such that the health monitoring of each layer in the PCB can be performed.

[0080] In an embodiment, the component carrier is formed in a plate shape. This contributes to a compact design, where the component carrier still provides a large base for mounting components thereon. Additionally, especially wafers, as an example of embedded electronic components, can be conveniently embedded into a thin board such as a printed circuit board due to their small thickness.

[0081] In an embodiment, the component carrier is configured as one of a printed circuit board, a substrate (especially an IC substrate), and an interposer.

[0082] In the context of the present application, the term "printed circuit board" (PCB) may specifically denote a board-shaped component carrier formed by laminating a plurality of electrically conductive layer structures and a plurality of electrically insulating layer structures, such as a board-shaped component carrier formed by applying pressure and / or by providing heat energy. As a preferred material for PCB technology, the electrically conductive layer structures are made of copper, while the electrically insulating layer structures may include resin and / or glass fibers, i.e., so-called prepregs or FR4 materials. The various electrically conductive layer structures can be connected to one another in a desired manner by forming holes through the laminate, for example by laser drilling or mechanical drilling of holes through the laminate, and by partially or completely filling these holes with an electrically conductive material (in particular copper) to form vias or any other through-hole connections. The filled holes either connect the entire stack (through-hole connections extend through multiple layers or the entire stack), or the filled holes either connect at least two electrically conductive layers, called vias. Similarly, optical interconnects can be formed through the individual layers of the stack in order to receive an electro-optical circuit board (EOCB). In addition to one or more components that may be embedded in the printed circuit board, the printed circuit board is generally configured to accommodate one or more components on one or two opposite surfaces of the board-shaped printed circuit board. They can be connected to the respective main surfaces by soldering. The dielectric portion of the PCB may consist of a resin with reinforcing fibers (such as glass fibers).

[0083] In the context of the present application, the term "substrate" may specifically denote a small component carrier. In the case of a PCB, the substrate may be a relatively small component carrier on which one or more components can be mounted, and the substrate can act as a connection medium between one or more chips and another PCB. For example, the substrate may have substantially the same dimensions as the components to be mounted thereon (such as in the case of a chip scale package (CSP)). In another embodiment, the substrate may be substantially larger than the allocated components (such as in the case of a flip chip ball grid array (FCBGA) configuration). More specifically, the substrate can be understood as a carrier for electrical connections or electrical networks, and a component carrier comparable to a printed circuit board (PCB), but with a considerably high density of laterally and / or vertically arranged connections. For example, lateral connections are, for example, conductive paths, while vertical connections can be, for example, drilled holes. These lateral and / or vertical connections are arranged within the substrate and can be used to provide electrical, thermal, and / or mechanical connections between accommodated components or non-accommodated components (such as bare lenses), in particular IC chips, and the printed circuit board or an intermediate printed circuit board. Thus, the term "substrate" also includes "IC substrate". The dielectric portion of the substrate may consist of a resin with reinforcing particles (such as reinforcing spheres, in particular glass spheres).

[0084] The substrate or the interposer may comprise or consist of the following: at least one layer of glass, silicon (Si) and / or photoimageable or dry-etchable organic materials such as epoxy build-up materials (such as epoxy build-up films) or polymer compounds (which may or may not include photosensitive and / or thermosensitive molecules) such as polyimide, polybenzoxazole.

[0085] In an embodiment, at least one electrically insulating layer structure may comprise at least one of the following: resins or polymers such as epoxy resin, cyanate resin, benzocyclobutene resin, bismaleimide-triazine resin, polystyrene derivatives (e.g., based on polyphenylene ether, PPE), polyimide (PI), polyamide (PA), liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE) and / or combinations thereof. Reinforcing structures such as meshes, fibers, spheres or other kinds of filler particles, for example made of glass (multi-layer glass) may also be used to form a composite material. A semi-cured resin combined with a reinforcing agent, e.g., fibers impregnated with the above resins, is called a prepreg. These prepregs are usually named after their properties, e.g., FR4 or FR5, which describe their flame retardant properties. While prepregs, especially FR4, are usually preferred for rigid PCBs, other materials may also be used, especially epoxy build-up materials (such as build-up films) or photoimageable dielectric materials. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymer and / or cyanate resin may be preferred. In addition to these polymers, low-temperature co-fired ceramics (LTCC) or other low, very low or ultra-low DK materials may be applied as electrically insulating structures in component carriers.

[0086] In an embodiment, at least one electrically conductive layer structure comprises at least one of the following: copper, aluminum, nickel, silver, gold, palladium, tungsten, magnesium, carbon, (specially doped) silicon, titanium and platinum. While copper is usually the preferred material, other materials or their coated versions are also possible, especially those coated with superconducting materials or conductive polymers, e.g., graphene or poly(3,4-ethylenedioxythiophene) (PEDOT).

[0087] At least one additional component can be embedded and / or surface-mounted on the stack. The component and / or at least one additional component can be selected from one of the following: non-conductive inlays, conductive inlays (such as metal inlays, preferably including copper or aluminum), heat transfer units (such as heat pipes), light guiding elements (such as optical waveguides or light conductor connections), electronic components or combinations thereof. The inlay can be, for example, a metal block, with or without an insulating material coating (IMS inlay), which can be embedded or surface-mounted to facilitate heat dissipation. Suitable materials are defined according to their thermal conductivity, which should be at least 2 W / mK. These materials are generally based on but not limited to metals, metal oxides and / or ceramics, such as copper, aluminum oxide (Al2O3) or aluminum nitride (AlN). To increase the heat exchange capacity, other geometries that increase the surface area are also often used. In addition, the component can be an active electronic component (implementing at least one pn junction), a passive electronic component, such as a resistor, inductor or capacitor, an electronic chip, a storage device (such as DRAM or other data memories), a filter, an integrated circuit (such as a field programmable gate array (FPGA), programmable array logic (PAL), generic array logic (GAL) and complex programmable logic device (CPLD)), a signal processing component, a power management component (such as a field effect transistor (FET), metal oxide semiconductor field effect transistor (MOSFET), complementary metal oxide semiconductor (CMOS), junction field effect transistor (JFET) or insulated gate field effect transistor (IGFET)), all of which are based on semiconductor materials, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), indium phosphide (InP) and / or any other suitable inorganic compound), an optoelectronic interface element, a light emitting diode, an optocoupler, a voltage converter (such as a DC / DC converter or an AC / DC converter), a cryptographic component, a transmitter and / or a receiver, an electromechanical transducer, a sensor, an actuator, a microelectromechanical system (MEMS), a microprocessor, a capacitor, a resistor, an inductor, a battery, a switch, a camera, an antenna, a logic chip and an energy harvesting device. However, other components can be embedded in the component carrier. For example, a magnetic element can be used as a component. Such a magnetic element can be a permanent magnetic element (such as a ferromagnetic element, an antiferromagnetic element, a multiferroic element or a ferrimagnetic element, such as a ferrite core), or it can also be a paramagnetic element. However, the component can also be an IC substrate, an interposer or another component carrier, for example in a board-in-board configuration. The component can be surface-mounted on the component carrier and / or can be embedded inside the component carrier. In addition, other components can also be used, especially components that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment.

[0088] In an embodiment, the component carrier is a laminated component carrier. In such an embodiment, the component carrier is a compound of a multi-layer structure, and the multi-layer structure is stacked and joined together by applying pressure and / or heat.

[0089] After processing the inner layer structure of the component carrier, one or more additional electrically insulating layer structures and / or electrically conductive layer structures can be symmetrically or asymmetrically applied (in particular by lamination) to one major surface or two opposite major surfaces of the processed layer structure. In other words, stacking can continue until the desired number of layers is obtained.

[0090] After completion of the formation of the stack of the electrically insulating layer structure and the electrically conductive layer structure, the obtained layer structure or component carrier can be surface-treated.

[0091] In particular, with respect to surface treatment, an electrically insulating solder resist can be applied to one major surface or two opposite major surfaces of the layer stack or the component carrier. For example, such a solder resist can be formed over the entire major surface and the solder resist layer can subsequently be patterned in order to expose one or more electrically conductive surface portions, which are used to couple the component carrier to an electronic periphery. Surface portions of the component carrier that remain covered by the solder resist, in particular surface portions containing copper, can be effectively protected against oxidation or corrosion.

[0092] With respect to surface treatment, a surface treatment can also be selectively applied to the exposed electrically conductive surface portions of the component carrier. Such a surface treatment can be an electrically conductive covering material on the exposed electrically conductive layer structure (such as pads, conductive tracks, etc., in particular including or consisting of copper) on the surface of the component carrier. If such an exposed electrically conductive layer structure is not protected, the exposed electrically conductive component carrier material (in particular copper) may oxidize, reducing the reliability of the component carrier. A surface treatment can then be formed, for example, as an interface between a surface-mounted component and the component carrier. The surface treatment has the function of protecting the exposed electrically conductive layer structure (in particular the copper circuit) and the function of enabling a connection process to one or more components, for example by soldering. Examples of suitable materials for the surface treatment are organic solderability preservatives (OSP), electroless nickel immersion gold (ENIG), electroless nickel immersion palladium gold (ENIPIG), electroless nickel immersion palladium gold (ENEPIG), gold (in particular hard gold), electroless tin (electroless tin and electroplated tin), nickel gold, nickel palladium, etc. Surface treatment can also be carried out using nickel-free materials, in particular for high-speed applications. Examples are ISIG (immersion silver immersion gold) and EPAG (electroless palladium autocatalytic gold). Description of the Drawings

[0093] The aspects defined above and further aspects of the present invention will become apparent from the following examples of embodiments to be described, and these examples are set forth with reference to the embodiments.

[0094] Figure 1 A sub - part of an electrical conduction layer structure in a stack of component carriers according to an exemplary embodiment of the present invention is shown.

[0095] Figure 2 A monolithic component carrier having a sub - part of an electrical conduction layer structure according to an exemplary embodiment of the present invention is shown.

[0096] Figure 3 A damage curve according to an exemplary embodiment of the present invention is shown.

[0097] Figure 4 A test device according to an exemplary embodiment of the present invention is shown.

[0098] Figure 5 A cross - section of a monolithic component carrier having embedded components according to an exemplary embodiment of the present invention is shown.

[0099] Figure 6 A top view of an exposed connection area at a main surface of a monolithic component carrier according to an exemplary embodiment of the present invention is shown. Detailed Description

[0100] The illustrations in the figures are schematic. It should be noted that in different figures, similar or identical elements or features are provided with the same reference numerals or with reference numerals that differ only in the first digit from the corresponding reference numerals. To avoid unnecessary repetition, elements or features that have been described in a previous embodiment will not be described again later in the specification.

[0101] Furthermore, spatial relative terms such as "front" and "back", "upper" and "lower", "left" and "right", etc. are used to describe the relationship of elements shown in the figures to one or more other elements. Thus, the spatial relative terms can be applied to orientations different from the orientation depicted in the figures when in use. Obviously, all these spatial relative terms refer to the orientation shown in the figures, and are for convenience of description only and are not necessarily restrictive.

[0102] Figure 1Shows a cross-sectional view of a monolithic component carrier 100 according to an exemplary embodiment of the present invention. The component carrier 100 includes a stacked assembly 101, which includes electrically conductive layer structures 130, 131, an electrically insulating layer structure 102, and a surface treatment (in particular a solder resist) 103. The lower electrically insulating layer structure 102 can also be implemented as an embedded component 180. One of the electrically conductive layer structures 130, 131 includes a sub-part 150, wherein the sub-part 150 is electrically separated or can be electrically separated from the rest of the electrically conductive layer structure. The sub-part 150 includes a region 155 that deteriorates over time, which in this example is part of a via interconnect. In an embodiment, the region 155 that deteriorates over time can also be connected to a test electrical interconnect 125, which can also be configured as a via.

[0103] The sub-part 150 and / or the test electrical interconnect 125 includes two ends, and in this example, each of the ends is electrically connected via the electrically conductive layer structures 130 and 131 to a corresponding connection region 140 exposed on the same main surface of the electrically insulating layer structure 102. The main surface is also located at the upper outer main surface of the stacked assembly 101.

[0104] In a specific example, the test electrical conductive interconnect 125 can be provided with the same mechanical / chemical characteristics as at least one of the plurality of electrical conductive interconnects 120, 121, and / or, in terms of depth, the test electrical conductive interconnect 125 can be provided at the same position as at least one of the plurality of electrical conductive interconnects 120, 121. The test electrical conductive interconnect 125 can be configured as a blind via, which is formed, for example, by laser drilling, and this manufacturing method produces a tapered shape. The upper part of the test electrical conductive interconnect 125 can be referred to as the "first end". The lower part of the test electrical conductive interconnect 125 is opposite to the first end and is referred to as the "second end". The second end can be embedded in the stacked assembly 101 and can be (electrically) connected to the component 180.

[0105] In a preferred example, the electrical conduction interconnects 120, 121 and the test electrical conduction interconnect 125, as well as the electrical conduction layer structures 130, 131, may comprise at least one metal, particularly may comprise copper or a copper alloy. In addition, the electrical conduction interconnects 120, 121 and the test electrical conduction interconnect 125, as well as the electrical conduction layers 130, 131, may comprise a surface treatment, particularly may comprise gold. In a further example, the electrical conduction interconnects 120, 121 and the test electrical conduction interconnect 125 may be indented below the surface when exposed on the main surface. Alternatively, the electrical conduction interconnects 120, 121 and the test electrical conduction interconnect 125 may be flush with the main surface when exposed on the main surface.

[0106] In Figure 1 FIGS. schematically show measurement devices 160, 170, i.e., measurement devices for four-wire testing, the measurement devices 160, 170 comprising four connection wires that are moved to contact (directly) exposed connection areas 140 connected to three electrical conduction interconnects 120, 121, 125, so as to test the test electrical conduction interconnect 125. In particular, there are a first wire and a second wire of a current measurement device (e.g., an ammeter / current meter) 160 that are respectively connected to the exposed connection area and another exposed connection area, and a third wire and a fourth wire of a voltage measurement device (e.g., a voltmeter) 170 that are respectively connected to the said another exposed connection area and another exposed connection area.

[0107] Due to the fact that the test electrical conduction interconnect 125 has a first end aligned with the main surface of the component carrier and / or a first end exposed to the main surface of the component carrier, one corresponding one of both the current measurement device 160 and the voltage measurement device 170 is directly connected to this first end. On the other hand, since the second end of the test electrical conduction interconnect 125 is embedded in the monolithic component carrier 100, the connection of the corresponding other wires of the current measurement device 160 and the voltage measurement device 170 to the second end and the connection to one of the other two electrical conduction interconnects 120, 121 are provided through electrical connection parts. Preferably, each of the other two electrical conduction interconnects 120, 121 has an end that is exposed to the same (single) main surface of the component carrier as the main surface where the first end of the test electrical conduction interconnect 125 is exposed, so that all the surfaces required for connecting the wires of the measurement devices 160, 170 are exposed on the same area of the monolithic component carrier 100, thereby providing electrical connection to the two ends of the test electrical conduction interconnect 125.

[0108] Figure 2FIG. 0 shows a monolithic component carrier 100 with a sub - portion 150 having an electrically conductive layer structure 104 according to an exemplary embodiment of the present invention. The outer main surface of the monolithic component carrier 100 includes a patterned (discontinuous) electrically conductive layer structure 104. A sub - portion 150 of the electrically conductive layer structure 104, such as an important via - interconnect (measurement via) to be monitored, includes a corresponding region 155 that deteriorates over time. As shown in the detailed view, such a sub - portion 150 can be electrically connected at the end of the sub - portion to a connection region 140 exposed at the outer main surface of the component carrier.

[0109] In this specific example, the exposed connection regions are configured as pads with the following functions: U - pad (voltage - drop measurement) 141, U + pad (voltage - drop measurement) 142, current - source pad 143, current - consumption pad 144. In a preferred example, the U + pad 142 and the current - source pad 143 can be connected to the first end of an important via - interconnect, such as a test electrical - conduction interconnect 125. Additionally, the U - pad 141 and the current - consumption pad 144 can be connected to the second end of an important via - interconnect, such as a test electrical - conduction interconnect 125. In a further example, the sub - portion can be located in the central portion and / or the peripheral portion of the monolithic component carrier 100. Although Figure 2 the architecture has been described as an example for the component carrier 100, this architecture can also be applied to packages and / or electronic panels (see above in the specification).

[0110] Figure 3 FIG. 9 shows a damage curve according to an exemplary embodiment of the present invention. In this example figure, the x - axis shows the resistance (in Mohm), and the y - axis shows the remaining percentage (%) of the via - interconnect (see cross - section). The experimentally determined or simulated damage curve correlates specific electrical values (the electrical values can be measured, for example, using a four - wire test) with the health state of the via - interconnect. In this example, the via - interconnect is the region 155 of the sub - portion 150 that deteriorates over time. As can be seen from the damage curve, an intact via (100%; about 200 Mohm in this example) has a very low resistance. In contrast, a damaged via (e.g., only 50% remaining after deterioration; about 300 Mohm in this example) has a much higher resistance. The more severe the via deterioration (material loss in the cross - section), the higher the resistance value, and correspondingly, the signal - transmission quality will be significantly degraded. Therefore, the electrical values measured regarding the sub - portion 150 can be directly linked to the health condition of the sub - portion 150, and then the health condition of the overall monolithic component carrier 100 can be inferred.

[0111] Figure 4Shows a current measuring device 160 and a voltage measuring device 170 (test device) according to an exemplary embodiment of the present invention. As already described above, the current measuring device 160 includes a first wire 161 and a second wire 162 for making electrical contact with at least one connection area 140. Correspondingly, the voltage measuring device 170 includes a third wire 171 and a fourth wire 172 for making electrical contact with at least one additional connection area 140. The current measuring device 160 and the voltage measuring device 170 can be implemented in a common device, which is configured to perform a four-wire test measurement.

[0112] Figure 5 Shows a further cross-sectional view of a monolithic component carrier 100 having a sub-part 150 in a stack 101 according to a further exemplary embodiment of the present invention. Different from the previous embodiment, the sub-part 150 is completely embedded / buried in the component carrier 100 such that the upper end is not directly connected to the exposed connection area 140 either.

[0113] In this example, three conduction layer structures 130, 130', 130'' are provided at three different vertical component carrier positions above the embedded component 180. In this example, the sub-part 150 is a via interconnect located / clamped between two conduction layer structures 130 and 130' and is electrically connected to said structures via two ends. The sub-part 150 includes a region / portion 155 that deteriorates over time, which is connected to the embedded component 180. The sub-part 150 further includes a test conduction interconnect 125, which is also configured as a via interconnect and is electrically connected to the sub-part 150 via the conduction layer structures 130, 130'. The test conduction interconnect 125 is also electrically connected to a third conduction layer structure 130'' at an exposed connection area 140 located at the outer main surface of the stack 101 / electrical insulation layer structure 102.

[0114] When the exposed connection area 140 is now contacted by the test devices 160, 170, the electrical value indicating the sub-part 150 can be measured. Based on said measurement, the health status of the monolithic component carrier 100 can be evaluated. A further sub-part 150' is directly connected to a corresponding further test conduction interconnect 125' via a further region 155' that deteriorates over time.

[0115] Figure 6A top view of an external main surface on a monolithic component carrier 100 according to an exemplary embodiment of the present invention is shown. In this example, the exposed connection regions 140 and 140' are connected to the first end, and the exposed connection regions 140'' and 140''' are connected to the second end. The four said exposed regions 140, 140', 140'', 140''' preferably have an array layout 145 on the main surface area of the monolithic component carrier 100. Preferably, each exposed region includes a quadrilateral connection region. Each element (connection region, additional connection region, other connection region) in the array 145 may have similar / same mechanical / chemical characteristics. Although Figure 6 the architecture has been described as an example for the component carrier 100, this architecture can also be applied to packages and / or electronic panels (see above in the specification).

[0116] By connecting the first and second wires of the current measuring device 160 and the third and fourth wires of the voltage measuring device 170 to each of the connection regions 140 respectively, each of the current measuring device 160 and the voltage measuring device 170 can be electrically connected to two ends, and at least one electrical value can be obtained.

[0117] Reference Numeral

[0118] 100 Component carrier

[0119] 101 Stack

[0120] 102 Electrical insulation layer structure

[0121] 103 Surface treatment part

[0122] 104 Electrical conduction layer structure

[0123] 120 Electrical conduction interconnect

[0124] 121 Additional electrical conduction interconnect

[0125] 125 Test electrical conduction interconnect

[0126] 130 Electrical conduction layer structure

[0127] 131 Electrical conduction layer structure

[0128] 140 Exposed connection region

[0129] 141 to 144 Pads

[0130] 145 Array

[0131] 150 Sub - part

[0132] 155 Region deteriorating over time

[0133] 160 Current measuring device

[0134] 161 First wire

[0135] 162 Second wire

[0136] 170 Voltage measuring device

[0137] 171 Third wire

[0138] 172 Fourth wire

[0139] 180 Component

Claims

1. A monolithic component carrier (100), the monolithic component carrier (100) comprising: A stack (101), the stack (101) having at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (102); Wherein at least one of the electrically conductive layer structures (104) includes a sub - portion (150), Wherein the sub - portion (150) is electrically separated from or can be electrically separated from the remainder of the electrically conductive layer structure (104), Wherein the sub - portion (150) includes a region (155) that deteriorates over time, Wherein the sub - portion (150) includes two ends, and Wherein each of the ends is electrically connected to a respective connection region (140) located on one of the major surfaces of at least one of the electrically insulating layer structures (102).

2. The monolithic component carrier (100) according to claim 1, wherein, The sub - portion (150) includes at least one test electrical conduction interconnect (125) extending along the thickness direction (z) of the stack (101).

3. The monolithic component carrier (100) according to claim 2, wherein, The component carrier (100) includes: A plurality of electrical conduction interconnects (120, 121) located in the stack (101), the electrical conduction interconnects (120, 121) being electrically connected to at least one electrically conductive layer structure (104), wherein at least one of the test electrical conduction interconnects (125) has the same mechanical / chemical characteristics as at least one of the plurality of electrical conduction interconnects (120, 121), and / or, in terms of depth, at least one of the test electrical conduction interconnects (125) has the same position as at least one of the plurality of electrical conduction interconnects (120, 121).

4. The monolithic component carrier according to claim 2 or 3, Among them, A component (180) is disposed on or embedded in the stack (101), Wherein at least one of the test electrical conduction interconnects (125) is connected to the component (180).

5. The monolithic component carrier (100) according to claim 4, the monolithic component carrier (100) further comprising: A plurality of additional components and a plurality of electrical conduction interconnects (120, 121) connected to the additional components, Wherein the component (180) has a region: the region of the component (180) has the same mechanical / chemical characteristics as a corresponding one of the plurality of additional components, and / or, in terms of depth, the region of the component (180) has the same position as a corresponding one of the plurality of additional components.

6. The monolithic component carrier (100) according to any one of claims 1 to 5, wherein, The connection between the test electrical conduction interconnect (125) and / or at least one of the two ends of the sub - portion (150) and the respective connection regions (140, 141) includes at least one via interconnect.

7. An encapsulation, the encapsulation comprising test devices (160, 170) and a monolithic component carrier (100) according to any one of claims 1 to 6, wherein, The test devices (160, 170) are electrically connected to the connection areas (140, 141) and / or are capable of being electrically connected to the connection areas (140, 141).

8. The package according to claim 7, wherein The test devices (160, 170) comprise four-wire test devices.

9. An electronic panel, the electronic panel comprising a stack, the stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure, and the stack being configured to subsequently be monomerized into a plurality of monolithic component carriers (100), each of the plurality of monolithic component carriers (100) being configured as a monolithic component carrier (100) according to any one of claims 1 to 6.

10. A method for evaluating the health status of a monolithic component carrier (100), the monolithic component carrier (100) comprising a stack (101), the stack (101) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (102), wherein, A sub-part (150) of at least one of the electrically conductive layer structures (104) comprises an area (155) that deteriorates over time, wherein the sub-part (150) comprises two ends, and wherein each of the ends is connected to a respective connection area (140, 141) provided on one of the main surfaces of at least one of the electrically insulating layer structures (102), the method comprising: providing test devices (160, 170) and connecting the test devices (160, 170) to the respective connection areas (140, 141); measuring an electrical value associated with the sub-part (150); and evaluating the health of the monolithic component carrier (100) based on the measured electrical value.

11. The method according to claim 10, Among them, The electrical value corresponds to or is associated with the resistance value of the current passing through the sub-part (150).

12. The method according to claim 10 or 11, Among them, The measurement of the electrical value of the sub-part (150) is carried out according to a time schedule.

13. The method according to any one of claims 10 to 12, Among them, The evaluation of the health of the monolithic component carrier (100) is carried out by combining the measured electrical value with a damage curve.

14. A computer-readable medium having stored therein a computer program for evaluating the health of a monolithic component carrier, the computer program being adapted to implement or control the method according to any one of claims 10 to 13 when executed by one or more processors.

15. A program element for evaluating the health of a monolithic component carrier, the program element being adapted to implement or control the method according to any one of claims 10 to 13 when executed by one or more processors.

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