Memory device having hierarchy of 2-transistor memory cells and charge storage structure having multiple portions

Abstract

Some embodiments include devices and methods of using the devices. One of the devices includes a first conductive structure, a second conductive structure, a conductive portion coupled to one of the conductive structures, and a memory cell. The memory cells include different semiconductor portions positioned on different levels of the device and separated from each other by dielectric portions. A first semiconductor portion is coupled to the first and second conductive structures. A second semiconductor portion is coupled to the first conductive structure. The memory cell includes a charge storage structure coupled to the second semiconductor portion. The charge storage structure includes a plurality of portions. Portions of the conductive portion are positioned between portions of the charge storage structure and separated from the charge storage structure by a dielectric material.

Description

[0001] Priority Application

[0002] This application claims the benefit of priority of U.S. Provisional Application No. 63 / 429,800, filed on Dec. 2, 2022, which is incorporated herein by reference in its entirety. BACKGROUND OF THE DISCLOSURE

[0003] Memory devices are widely used to store information in computers and many other electronic products. Memory devices are typically classified into two types: volatile memory devices and non-volatile memory devices. Memory devices generally have numerous memory cells for storing information. In volatile memory devices, the information stored in the memory cells is lost when power supply to the memory device is disconnected. In non-volatile memory devices, the information stored in the memory cells remains retained even when power supply to the memory device is disconnected.

[0004] The description herein relates to volatile memory devices. Most conventional volatile memory devices store information in the form of charge in capacitor structures included in memory cells. As the requirements for device storage density increase, many conventional techniques provide ways to reduce the size of memory cells in order to increase the device storage density for a given device area. However, if the memory cell size is reduced to a certain dimension, physical limitations and manufacturing constraints pose challenges to such conventional techniques. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A block diagram of an apparatus in the form of a memory device including volatile memory cells, in accordance with some embodiments described herein.

[0006] Figure 2 A schematic diagram of a portion of a memory device including a memory array of 2-transistor (2T) memory cells, in accordance with some embodiments described herein.

[0007] Figure 3 A memory device including example voltages used during a read operation of the memory device, in accordance with some embodiments described herein. Figure 2 of the memory device.

[0008] Figure 4 A memory device including example voltages used during a write operation of the memory device, in accordance with some embodiments described herein. Figure 2 of the memory device.

[0009] Figure 5 A memory device including a separate driver coupled to an access line associated with a memory cell, in accordance with some embodiments described herein. Figure 2 of the memory device.

[0010] Figures 6A to 7F Showing different views of the structure of a memory device including memory cells having multiple levels according to some embodiments described herein Figures 2 to 5 of the memory device.

[0011] Figure 8 Showing according to some embodiments described herein Figures 2 to 7F variations of the memory cell structure of the memory device. Detailed Description

[0012] The memory device described herein includes volatile memory cells, where each of the memory cells may include two transistors (2T) and a charge storage structure, and the charge storage structure may form a memory element of the memory cell to store information.

[0013] The described memory device includes levels stacked one above the other on a substrate (e.g., a semiconductor substrate) of the memory device. Each level has memory cells and associated access lines (e.g., word lines).

[0014] The access lines may be configured to include separate conductive regions (e.g., conductive strips) having a length extending horizontally across the memory cells in the respective levels. The access lines in a level are used to control the transistors of the memory cells in that level. The conductive regions of the access lines may be configured such that the two transistors in a memory cell can be controlled by the same signal provided through the access line. Alternatively, separate signals (e.g., two different signals from two different drivers) may be used to separately control the transistors in a memory cell.

[0015] The described memory device includes data lines (e.g., bit lines), which may include conductive structures extending through the levels (e.g., extending vertically). Memory cells of different levels may share the conductive structures of the data lines (e.g., vertical data lines).

[0016] In addition to the conductive structures of the data lines, the described memory device also includes common conductive structures. The common conductive structures may also extend through the levels (e.g., extending vertically). Memory cells associated with different access lines (e.g., word lines) may share the common conductive structures. Alternatively, memory cells associated with different access lines may be coupled to different common conductive structures. Different voltages may be applied to the common conductive structures during read and write operations of the memory device. Alternatively, the common conductive structures may also be part of the ground connection (e.g., a ground plane) of the memory device.

[0017] Improvements and benefits of the described memory devices include increased device area efficiency, reduced capacitive coupling between adjacent data lines, reduced total capacitance associated with the data lines, and more choices of materials for the transistors. Additionally, the hierarchical structure of the described memory devices can also improve (e.g., reduce) the cost per bit of the memory devices. Other improvements and benefits of the described memory devices and their variants are discussed below with reference to Figures 1 to 8 discussed.

[0018] Figure 1 FIG. 6 shows a block diagram of an apparatus in the form of a memory device 100 including volatile memory cells according to some embodiments described herein. The memory device 100 includes a memory array 101 that may contain memory cells 102. The memory device 100 may include a volatile memory device such that the memory cells 102 may be volatile memory cells. Examples of the memory device 100 include dynamic random access memory (DRAM) devices. Information stored in the memory cells 102 of the memory device 100 is lost (e.g., invalidated) when power supply (e.g., supply voltage Vcc) is disconnected from the memory device 100. Hereinafter, the supply voltage Vcc is referred to as representing some voltage levels; however, they are not limited to the supply voltage (e.g., Vcc) of the memory device (e.g., memory device 100). For example, if the memory device (e.g., memory device 100) has an internal voltage generator ( Figure 1 not shown in FIG. 6) that generates an internal voltage based on the supply voltage Vcc, then this internal voltage may be used instead of the supply voltage Vcc.

[0019] In the physical structure of the memory device 100, each of the memory cells 102 may include transistors (e.g., two transistors) vertically formed in different tiers (e.g., stacked on different layers) above a substrate (e.g., semiconductor substrate) of the memory device 100. The memory device 100 may also include multiple tiers (e.g., multiple hierarchies) of memory cells, where the memory cells of one tier (e.g., one hierarchy) may be formed (e.g., stacked) above additional memory cells of another tier (e.g., another hierarchy). The structure of the memory array 101 including the memory cells 102 may include the structure of the memory array and the memory cells described below with reference to Figures 2 to 8 described.

[0020] As Figure 1 shown in FIG. 6, the memory device 100 may include access lines 104 (e.g., “word lines”) and data lines (e.g., bit lines) 105. The memory device 100 may use signals on the access lines 104 (e.g., word line signals) to access the memory cells 102 and use the data lines 105 to provide information (e.g., data) stored in (e.g., written to) or read from (e.g., sensed from) the memory cells 102.

[0021] The memory device 100 may include an address register 106 for receiving address information ADDR (such as row address signals and column address signals) on a line 107 (such as an address line). The memory device 100 may include a row access circuit system 108 (such as an X decoder) and a column address circuit system 109 (such as a Y decoder) operable to decode the address information ADDR from the address register 106. Based on the decoded address information, the memory device 100 may determine which memory cells 102 are to be accessed during a memory operation. The memory device 100 may perform a write operation to store information in the memory cells 102 and perform a read operation to read (such as sense) the information (such as previously stored information) in the memory cells 102. The memory device 100 may also perform an operation (such as a refresh operation) to refresh the information value stored in the memory cells 102 (such as to keep the information value valid). Each of the memory cells 102 may be configured to store information that can represent at most one bit (such as a single bit having binary 0 (“0”) or binary 1 (“1”)) or more than one bit (such as multiple bits having a combination of at least two binary bits).

[0022] The memory device 100 may receive supply voltages, including a supply voltage Vcc and a supply voltage Vss on lines 130 and 132, respectively. The supply voltage Vss may operate at a ground potential (such as having a value of about 0 volts). The supply voltage Vcc may include an external voltage supplied to the memory device 100 from an external power source such as a battery or an alternating current / direct current (AC-DC) converter circuit system.

[0023] As Figure 1 shown, the memory device 100 may include a memory control unit 118, which includes circuitry (such as hardware components) for controlling the memory operations (such as read and write operations) of the memory device 100 based on control signals on a line (such as a control line) 120. Examples of signals on the line 120 include a row access strobe signal RAS*, a column access strobe signal CAS*, a write enable signal WE*, a chip select signal CS*, a clock signal CK, and a clock enable signal CKE. These signals may be part of the signals provided to a DRAM device.

[0024] As Figure 1As shown, the memory device 100 may include lines (e.g., global data lines) 112 that can carry signals DQ0 to DQN. During a read operation, the value (e.g., "0" or "1") of the information provided to the lines 112 (read from the memory cells 102), in the form of signals DQ0 to DQN, may be based on the value of the signal on the data line 105. During a write operation, the value of the information provided to the data line 105 (for storage in the memory cells 102), e.g., "0" or "1", may be based on the values of the signals DQ0 to DQN on the lines 112.

[0025] The memory device 100 may include sense circuitry 103, selection circuitry 115, and input / output (I / O) circuitry 116. The column access circuitry 109 may selectively activate signals on lines (e.g., select lines) based on the address signal ADDR. The selection circuitry 115 may respond to the signal on the line 114 to select the signal on the data line 105. The signal on the data line 105 may represent the value of the information stored in the memory cells 102 (e.g., during a write operation) or the information read (e.g., sensed) from the memory cells 102 (e.g., during a read operation).

[0026] The I / O circuitry 116 may be operable to provide the information read from the memory cells 102 to the lines 112 (e.g., during a read operation) and to provide the information from the lines 112 (e.g., provided by an external device) to the data line 105 for storage in the memory cells 102 (e.g., during a write operation). The lines 112 may include nodes within the memory device 100 or pins (or solder balls) on a package in which the memory device 100 may reside. Other devices external to the memory device 100 (e.g., a hardware memory controller or a hardware processor) may communicate with the memory device 100 via the lines 107, 112, and 120.

[0027] The memory device 100 may include other components that are not shown in Figure 1 to avoid obscuring the example embodiments described herein. At least a portion of the memory device 100 (e.g., a portion of the memory array 101) may include structures and operations similar or identical to any of the memory devices described below with reference to Figures 2 to 2 8C.

[0028] Figure 2 A schematic diagram showing a portion of a memory device 200 including a memory array 201 according to some embodiments described herein. The memory device 200 may correspond to Figure 1 the memory device 100. For example, the memory array 201 may form Figure 1 a portion of the memory array 101 of Figure 2As shown, the memory device 200 may include memory cells 210 to 215, which are volatile memory cells (e.g., DRAM cells). For simplicity, similar or identical elements between memory cells 210 to 215 are given the same reference numerals.

[0029] Each of memory cells 210 to 215 may include two transistors T1 and T2. Thus, each of memory cells 210 to 215 may be referred to as a 2T memory cell (e.g., 2T gain cell). Each of transistors T1 and T2 may include a field effect transistor (FET). As an example, transistor T1 may be a p-channel FET (PFET), and transistor T2 may be an n-channel FET (NFET). A portion of transistor T1 may include the structure of a p-channel metal oxide semiconductor (PMOS) transistor. Thus, transistor T1 may include operations similar to those of a PMOS transistor. A portion of transistor T2 may include an n-channel metal oxide semiconductor (NMOS). Thus, transistor T2 may include operations similar to those of an NMOS transistor.

[0030] Transistor T1 of the memory device 200 may include a charge storage-based structure (e.g., based on a floating gate). As Figure 2 shown, each of memory cells 210 to 215 may include a charge storage structure 202, which may include the floating gate of transistor T1. The charge storage structure 202 may form the memory element of the corresponding memory cell among memory cells 210 to 215. The charge storage structure 202 may store charge. The information value (e.g., "0" or "1") stored in a particular memory cell among memory cells 210 to 215 may be based on the amount of charge in the charge storage structure 202 of this particular memory cell. For example, the information value stored in a particular memory cell among memory cells 210 to 215 may be "0" or "1" (if each memory cell is configured as a single-bit memory cell) or "00", "01", "10", or "11" (or other multi-bit values) (if each memory cell is configured as a multi-bit memory cell).

[0031] As Figure 2As shown, the transistor T2 of a particular memory cell in memory cells 210 to 215 (e.g., the channel region of transistor T2) can be electrically coupled to (e.g., directly coupled to (in contact with)) the charge storage structure 202 of this particular memory cell. Thus, a circuit path (e.g., a current path) can be directly formed between the transistor T2 of a particular memory cell and the charge storage structure 202 of this particular memory cell during the operation of memory device 200 (e.g., a write operation). During a write operation of memory device 200, a circuit path (e.g., a current path) can be formed between the corresponding data line (e.g., data line 221 or 222) and the charge storage structure 202 of a particular memory cell through the transistor T2 of the particular memory cell (e.g., through the channel region of transistor T2).

[0032] Memory cells 210 to 215 can be arranged into memory cell groups 2010 and 2011. Figure 2 Two memory cell groups (e.g., 2010 and 2011) are shown as an example. However, memory device 200 can include more than two memory cell groups. Memory cell groups 2010 and 2011 can include the same number of memory cells. For example, memory cell group 2010 can include memory cells 210, 212, and 214, and memory cell group 2011 can include memory cells 211, 213, and 215. Figure 2 Three memory cells of each of memory cell groups 2010 and 2011 are shown as an example. The number of memory cells in memory cell groups 2010 and 2011 can be different from 3.

[0033] Memory device 200 can perform a write operation to store information in memory cells 210 to 215 and perform a read operation to read (e.g., sense) information from memory cells 210 to 215. Memory device 200 can be configured to operate as a DRAM device. However, different from some conventional DRAM devices that store information in a structure of a container such as a capacitor, memory device 200 can store information in the form of charge in charge storage structure 202, which can be a floating gate structure. As mentioned above, charge storage structure 202 can be the floating gate of transistor T1. During the operation of memory device 200 (e.g., a read or write operation), an access line (e.g., a single access line) and a data line (e.g., a single data line) can be used to access a selected memory cell (e.g., a target memory cell).

[0034] As Figure 2As shown, the memory device 200 may include access lines (e.g., word lines) 241, 242, and 243 that can carry corresponding signals (e.g., word line signals) WL1, WL2, and WLn. The access lines 241, 242, and 243 can be used to access both memory cell groups 2010 and 2011. In the physical structure of the memory device 200, each of the access lines 241, 242, and 243 can be configured as at least one conductive wire (one conductive wire or multiple conductive wires, where the multiple conductive wires can be electrically coupled to each other (e.g., shorted)) (formed by the at least one conductive wire).

[0035] The access lines 241, 242, and 243 can be selectively activated (e.g., one at a time) during the operation of the memory device 200 (e.g., read or write operation) to access a selected memory cell (or several selected memory cells) among memory cells 210 to 215. The selected memory cell can be referred to as the target memory cell. In a read operation, information can be read from a selected memory cell (or several selected memory cells). In a write operation, information can be stored in a selected memory cell (or several selected memory cells).

[0036] As Figure 2 shown, transistors T1 and T2 can have gates 251 and 252 respectively. The gate of each of transistors T1 and T2 (e.g., gate 251 or 252) can be part of a corresponding access line (e.g., a corresponding word line). As Figure 2 shown, the gate of each of transistors T1 and T2 of memory cell 210 (e.g., gate 251 or 252) can be part of access line 241. The gate of each of transistors T1 and T2 of memory cell 211 (e.g., gate 251 or 252) can be part of access line 241. For example, in the physical structure of the memory device 200, four different portions of the conductive material forming access line 241 (e.g., four different portions of a continuous metal or polysilicon sheet) can form four gates, which include gates 251 and 252 of the corresponding transistors T1 and T2 of memory cell 210 and gates 251 and 252 of the corresponding transistors T1 and T2 of memory cell 211.

[0037] The gate (e.g., gate 251 or 252) of each of the transistors T1 and T2 of the memory cell 212 can be part of the access line 242. The gate (e.g., gate 251 or 252) of each of the transistors T1 and T2 of the memory cell 213 can be part of the access line 242. For example, in the physical structure of the memory device 200, four different portions of the conductive material forming the access line 242 (e.g., four different portions of a continuous metal or polysilicon sheet) can form four gates, which include the gates 251 and 252 of the respective transistors T1 and T2 of the memory cell 212 and the gates 251 and 252 of the respective transistors T1 and T2 of the memory cell 213.

[0038] The gate (e.g., gate 251 or 252) of each of the transistors T1 and T2 of the memory cell 214 can be part of the access line 243. The gate (e.g., gate 251 or 252) of each of the transistors T1 and T2 of the memory cell 215 can be part of the access line 243. For example, in the physical structure of the memory device 200, four different portions of the conductive material forming the access line 243 (e.g., four different portions of a continuous metal or polysilicon sheet) can form four gates, which include the gates 251 and 252 of the respective transistors T1 and T2 of the memory cell 214 and the gates 251 and 252 of the respective transistors T1 and T2 of the memory cell 215.

[0039] In this description, the material can include a single material or a combination of multiple materials. The conductive material can include a single conductive material or a combination of multiple conductive materials.

[0040] The memory device 200 can include data lines (e.g., bit lines) 221 and 222 that can carry respective signals (e.g., bit line signals) BL1 and BL2. During a read operation, the memory device 200 can use the data line 221 to obtain information read (e.g., sensed) from a selected memory cell of the memory cell group 2010 and use the data line 222 to read information from a selected memory cell of the memory cell group 2011. During a write operation, the memory device 200 can use the data line 221 to provide information to be stored in a selected memory cell of the memory cell group 2010 and use the data line 222 to provide information to be stored in a selected memory cell of the memory cell group 2011.

[0041] The memory device 200 may include a connection 297 coupled to memory cells 210 to 215. The connection 297 may include different conductive portions, where each conductive portion may be configured as a conductive wire (e.g., a wire (or layer) of conductive material) or alternatively, a conductive plate (e.g., a layer of conductive material). The connection 297 may be coupled to a voltage (e.g., a non-ground voltage) during operation (e.g., a read or write operation) of the memory device 200. Alternatively, the connection 297 may be coupled to ground or may be part of the ground connection of the memory device 200.

[0042] As Figure 2 shown, different portions of the connection 297 may be shared by memory cells associated with different access lines (e.g., word lines). For example, a portion of the connection 297 may be shared by memory cells 210, 212, and 214 respectively associated with access lines 241, 242, and 243. In another example, another portion of the connection 297 may be shared by memory cells 211, 213, and 215 respectively associated with access lines 241, 242, and 243.

[0043] Alternatively, memory cells associated with different access lines may themselves have portions of the connection 297. For example, memory cells 210 and 211 associated with access line 241 may be coupled to a portion of the connection 297 that is not shared by memory cells (e.g., memory cells 212, 213, 214, and 215) associated with other access lines (e.g., access lines 242 and 243) ( Figure 2 not shown). In another example, memory cells 212 and 213 associated with access line 242 may be coupled to a portion of the connection 297 that is not shared by memory cells (e.g., memory cells 210, 211, 214, and 215) associated with other access lines (e.g., access lines 241 and 243) ( Figure 2 not shown). In another example, memory cells 214 and 215 associated with access line 243 may be coupled to a portion of the connection 297 that is not shared by memory cells (e.g., memory cells 210, 211, 212, and 213) associated with other access lines (e.g., access lines 241 and 242) ( Figure 2 not shown). Thus, the memory cells associated with access lines 241, 242, and 243 may be coupled to separate portions of the connection 297 (e.g., three separate portions, Figure 2 not shown). As Figure 2 shown or as described in the above examples, sharing portions of the connection 297 may reduce the capacitance (e.g., plate capacitance) of the conductive structure forming the connection 297 (or portions of the connection 297).

[0044] As Figure 2As shown, the transistor T1 (e.g., the channel region of transistor T1) of a particular memory cell among memory cells 210 to 215 can be electrically coupled to (e.g., directly coupled to) a portion of connection 297 and electrically coupled to (e.g., directly coupled to) a corresponding data line (e.g., data line 221 or 222). Thus, a circuit path (e.g., a current path) can be formed between the corresponding data line (e.g., data line 221 or 222) and a portion of connection 297 through the transistor T1 of the selected memory cell during an operation (e.g., a read operation) performed on the selected memory cell. During a read operation, a voltage (e.g., a non-ground voltage) can be applied to the portion of connection 297 coupled to the selected memory cell or, alternatively, it can be coupled to ground.

[0045] Memory device 200 can include a read path (e.g., a circuit path). Information read from a selected memory cell during a read operation can be obtained through the read path coupled to the selected memory cell. In memory cell group 2010, the read path of a particular memory cell (e.g., memory cell 210, 212, or 214) can include a current path (e.g., a read current path) through the channel region of transistor T1 of this particular memory cell, data line 221, and a portion of connection 297 coupled to the memory cells (e.g., memory cells 210, 212, and 214) in memory cell group 2010. In memory cell group 2011, the read path of a particular memory cell (e.g., memory cell 211, 213, or 215) can include a current path (e.g., a read current path) through the channel region of transistor T1 of this particular memory cell, data line 222, and a portion of connection 297 coupled to the memory cells (e.g., memory cells 211, 213, and 215) in memory cell group 2011. In an example where transistor T1 is a PFET (e.g., a PMOS), the current in the read path (e.g., during a read operation) can include hole conduction (e.g., hole conduction in the direction from data line 221 through the channel region (e.g., a p-channel region) of transistor T1 to a portion of connection 297). Since transistor T1 can be used in the read path to read information from the corresponding memory cell during a read operation, transistor T1 can be referred to as a read transistor and the channel region of transistor T1 can be referred to as a read channel region.

[0046] The memory device 200 may include a write path (e.g., a circuit path). Information stored in a selected memory cell during a write operation may be provided to the selected memory cell through the write path coupled to the selected memory cell. In the memory cell group 2010, the write path of a particular memory cell may include the transistor T2 of this particular memory cell (e.g., may include a write current path through the channel region of the transistor T2) and the data line 221. In the memory cell group 2011, the write path of a particular memory cell (e.g., memory cells 211, 213, or 215) may include the transistor T2 of this particular memory cell (e.g., may include a write current path through the channel region of the transistor T2) and the data line 222. In an example where the transistor T2 is an NFET (e.g., NMOS), the current in the write path (e.g., during a write operation) may include electron conduction through the channel region (e.g., n-channel region) of the transistor T2 (e.g., electron conduction in the direction from the data line 221 to the charge storage structure 202). Since the transistor T2 may be used in the write path to store information in the corresponding memory cell during a write operation, the transistor T2 may be referred to as a write transistor and the channel region of the transistor T2 may be referred to as a write channel region.

[0047] Each of the transistors T1 and T2 may have a threshold voltage (Vt). The transistor T1 has a threshold voltage Vt1. The transistor T2 has a threshold voltage Vt2. The values of the threshold voltages Vt1 and Vt2 may be different (unequal values). For example, the value of the threshold voltage Vt2 may be greater than the value of the threshold voltage Vt1. The difference between the values of the threshold voltages Vt1 and Vt2 allows information stored in the charge storage structure 202 in the transistor T1 on the read path to be read (e.g., sensed) during a read operation without affecting (e.g., turning on) the transistor T2 on the write path (e.g., the path through the transistor T2). This may prevent charge leakage from the charge storage structure 202 through the transistor T2 of the write path (e.g., during a read operation).

[0048] In the structure of the memory device 200, the transistors T1 and T2 may be formed (e.g., designed) such that the threshold voltage Vt1 of the transistor T1 may be less than 0 volts (e.g., Vt1 < 0V), regardless of the value of the information stored in the charge storage structure 202 of the transistor T1 (e.g., "0" or "1"), and Vt1 < Vt2. When information with a "0" value is stored in the charge storage structure 202, the charge storage structure 202 may be in the state "0". When information with a "1" value is stored in the charge storage structure 202, the charge storage structure 202 may be in the state "1". Thus, in this structure, the relationship between the values of the threshold voltages Vt1 and Vt2 may be expressed as follows: Vt1 in state "0" < Vt1 in state "1" < 0V, and Vt2 = 0V (or alternatively, Vt2 > 0V).

[0049] In an alternative structure of the memory device 200, the transistors T1 and T2 may be formed (e.g., designed) such that Vt1 of state "0" < Vt1 of state "1", where Vt1 of state "0" < 0V (or alternatively, Vt1 of state "0" = 0V), Vt1 of state "1" > 0V, and Vt1 < Vt2.

[0050] In another alternative structure, the transistors T1 and T2 may be formed (e.g., designed) such that Vt1 of state "0" < Vt1 of state "1", where Vt1 of state "0" = 0V (or alternatively, Vt1 of state "0" > 0V), and Vt1 < Vt2.

[0051] During a read operation of the memory device 200, only one memory cell of the same memory cell group may be selected one by one to read information from the selected memory cell. For example, the memory cells 210, 212, and 214 of the memory cell group 2010 may be selected one by one during the read operation to read information from the selected memory cell (e.g., one of the memory cells 210, 212, and 214 in this example). In another example, the memory cells 211, 213, and 215 of the memory cell group 2011 may be selected one by one during the read operation to read information from the selected memory cell (e.g., one of the memory cells 211, 213, and 215 in this example).

[0052] During the read operation, the memory cells of different memory cell groups (e.g., memory cell groups 2010 and 2011) sharing the same access line (e.g., access lines 241, 242, or 243) may be selected concurrently (or alternatively may be selected sequentially). For example, the memory cells 210 and 211 may be selected concurrently during the read operation to read (e.g., concurrently read) information from the memory cells 210 and 211. The memory cells 212 and 213 may be selected concurrently during the read operation to read (e.g., concurrently read) information from the memory cells 212 and 213. The memory cells 214 and 215 may be selected concurrently during the read operation to read (e.g., concurrently read) information from the memory cells 214 and 215.

[0053] During a read operation, the information value read from a selected memory cell of memory cell group 2010 can be determined based on the value of a current detected (e.g., sensed) from a read path (described above) that includes data line 221, transistor T1 of the selected memory cell (e.g., memory cell 210, 212, or 214), and a portion of connection 297 coupled to the selected memory cell. During a read operation, the information value read from a selected memory cell of memory cell group 2011 can be determined based on the value of a current detected (e.g., sensed) from a read path that includes data line 222, transistor T1 of the selected memory cell (e.g., memory cell 211, 213, or 215), and a portion of connection 297 coupled to the selected memory cell.

[0054] Memory device 200 can include detection circuitry (not shown) that can operate during a read operation to detect (e.g., sense) a current (e.g., current I1 (not shown)) on a read path that includes data line 221 and to detect a current (e.g., current I2 (not shown)) on a read path that includes data line 222. The value of the detected current can be based on the information value stored in the selected memory cell. For example, depending on the information value stored in the selected memory cell of memory cell group 2010, the value of the current detected on data line 221 (e.g., the value of current I1) can be 0 or greater than 0. Similarly, depending on the information value stored in the selected memory cell of memory cell group 2011, the value of the current detected on data line 222 (e.g., the value of current I2) can be 0 or greater than 0. Memory device 200 can include circuitry (not shown) for translating the value of the detected current into the information value stored in the selected memory cell (e.g., “0”, “1”, or a combination of multi-bit values).

[0055] During a write operation of memory device 200, only one memory cell of the same memory cell group can be selected at a time to store information in the selected memory cell. For example, memory cells 210, 212, and 214 of memory cell group 2010 can be selected one at a time during a write operation to store information in a selected memory cell (e.g., one of memory cells 210, 212, and 214 in this example). In another example, memory cells 211, 213, and 215 of memory cell group 2011 can be selected one at a time during a write operation to store information in a selected memory cell (e.g., one of memory cells 211, 213, and 215 in this example).

[0056] During a write operation, memory cells in different groups of memory cells (such as memory cell groups 2010 and 2011) that share the same access line (such as access lines 241, 242, or 243) can be concurrently selected. For example, memory cells 210 and 211 can be concurrently selected during a write operation to store information (such as concurrently store) in memory cells 210 and 211. Memory cells 212 and 213 can be concurrently selected during a write operation to store information (such as concurrently store) in memory cells 212 and 213. Memory cells 214 and 215 can be concurrently selected during a write operation to store information (such as concurrently store) in memory cells 214 and 215.

[0057] During a write operation, the information stored in the selected memory cells of memory cell group 2010 can be provided through the write path (described above) of transistor T2 that includes data line 221 and the selected memory cell (such as memory cell 210, 212, or 214). During a write operation, the information stored in the selected memory cells of memory cell group 2011 can be provided through the write path (described above) of transistor T2 that includes data line 222 and the selected memory cell (such as memory cell 211, 213, or 215). As described above, the information value (such as a binary value) stored in a specific memory cell among memory cells 210 to 215 can be based on the amount of charge in the charge storage structure 202 of this specific memory cell.

[0058] In a write operation, the amount of charge in the charge storage structure 202 of the selected memory cell can be changed (to reflect the information value stored in the selected memory cell) by applying a voltage to the write path that includes transistor T2 of this specific memory cell and the data line (such as data line 221 or 222) coupled to this specific memory cell. For example, if the information in the selected memory cells stored in memory cells 210, 212, and 214 has a value (such as "0"), a voltage having a value (such as 0V) can be applied to data line 221 (such as providing 0V to signal BL1). In another example, if the information in the selected memory cells stored in memory cells 210, 212, and 214 has another value (such as "1"), a voltage having another value (such as a positive voltage) can be applied to data line 221 (such as providing a positive voltage to signal BL1). Thus, information can be stored (such as directly stored) in the charge storage structure 202 of this specific memory cell by providing the information (such as in the form of a voltage) to the write path of the specific memory cell that includes transistor T2.

[0059] Figure 3Showing example voltages V1, V2, and V3 used during a read operation of a memory device 200 according to some embodiments described herein Figure 2 of the memory device 200. Figure 3 The example assumes that memory cells 210 and 211 are the selected memory cells (e.g., target memory cells) during a read operation to read (e.g., sense) the information stored (e.g., previously stored) in memory cells 210 and 211. Memory cells 212 to 215 are considered unselected memory cells. This means that: in Figure 3 the example, memory cells 212 to 215 are not accessed and the information stored in memory cells 212 to 215 is not read, but the information is read from memory cells 210 and 211. In this example, access line 241 can be referred to as the selected access line (e.g., selected word line), which is the access line associated (e.g., coupled) with the selected memory cells (e.g., memory cells 210 and 211 in this example). In this example, access lines 242 and 243 can be referred to as unselected access lines (e.g., unselected word lines), which are the access lines associated (e.g., coupled) with the unselected memory cells (e.g., memory cells 212, 213, 214, and 215 in this example).

[0060] In Figure 3 it, voltages V1, V2, and V3 can represent different voltages applied to the respective access lines 241, 242, and 243 and data lines 221 and 222 during a read operation of the memory device 200. Voltage V1 can be applied to the selected access line (e.g., access line 241). During a read operation, voltage V2 can be applied to the unselected access lines (e.g., access lines 242 and 243).

[0061] Voltages V1, V2, and V3 can have different values. As an example, voltages V1, V2, and V3 can have values of -1V, 0V, and 0.5V, respectively. The specific values of the voltages used for this description are only example values. Different values can be used. For example, voltage V1 can have a negative value range (e.g., the value of voltage V1 can be from -3V to -1V). Connection 297 can be applied with a voltage or can be coupled to ground.

[0062] In Figure 3In the read operation shown, the voltage V1 may have a value (e.g., a voltage value) to turn on the transistors T1 of each of the memory cells 210 and 211 (the selected memory cells in this example) and turn off (or avoid) the transistors T2 of each of the memory cells 210 and 211. This allows information to be read from the memory cells 210 and 211. The voltage V2 may have a value such that the transistors T1 and T2 of each of the memory cells 212 to 215 (the unselected memory cells in this example) are turned off (e.g., avoided). The voltage V3 may have a value such that a current (e.g., a read current) can be formed on the read paths including the data line 221 and the transistor T1 of the memory cell 210 and the read path including the data line 222 and the transistor T1 of the memory cell 212 (separate read paths). This allows the currents detected on the read paths coupled to the memory cells 210 and 211, respectively (e.g., on the corresponding data lines 221 and 222), to be detected. The detection circuitry (not shown) of the memory device 200 may be operable to translate the value of the detected current (during reading information from the selected memory cell) into the value of the information read from the selected memory cell (e.g., "0", "1", or a combination of multiple-bit values). In Figure 3 this example, the values of the currents detected on the data lines 221 and 222 may be translated into the values of the information read from the memory cells 210 and 211, respectively.

[0063] In Figure 3In the read operation shown, the voltages applied to the respective access lines 241, 242, and 243 may cause the transistors T1 and T2 of each of the memory cells 212 to 215 (except for the transistor T1 of each of the memory cells 210 and 211 (selected memory cells)) to turn off (or remain off). The transistor T1 of the memory cell 210 (selected memory cell) may or may not be turned on, depending on the value of the threshold voltage Vt1 of the transistor T1 of the memory cell 210. The transistor T1 of the memory cell 211 (selected memory cell) may or may not be turned on, depending on the value of the threshold voltage Vt1 of the transistor T1 of the memory cell 211. For example, if the transistor T1 of each of the memory cells (such as 210 to 215) of the memory device 200 is configured (such as constructed) such that the threshold voltage of the transistor T1 is less than 0 (such as Vt1 < -1V) (regardless of the information value (such as state) stored in the corresponding memory cell 210), then in this example, the transistor T1 of the memory cell 210 may be turned on and conduct current on the data line 221 (through the transistor T1 of the memory cell 210). In this example, the transistor T1 of the memory cell 211 may also be turned on and conduct current on the data line 222 (through the transistor T1 of the memory cell 211). The memory device 200 may determine the information values stored in the memory cells 210 and 211 based on the values of the currents on the data lines 221 and 222, respectively. As described above, the memory device 200 may include detection circuitry for measuring the current values on the data lines 221 and 222 during a read operation.

[0064] Figure 4 A memory device 200 showing example voltages V4, V5, V6, and V7 used during a write operation of the memory device 200 according to some embodiments described herein Figure 2 of. Figure 4 The example assumes that the memory cells 210 and 211 are the selected memory cells (such as target memory cells) during a write operation to store information in the memory cells 210 and 211. The memory cells 212 to 215 are considered unselected memory cells. This means that: in Figure 4 the example, the memory cells 212 to 215 are not accessed and information is not stored in the memory cells 212 to 215, but rather the information is stored in the memory cells 210 and 211.

[0065] In Figure 4In [the figure], voltages V4, V5, V6, and V7 may represent different voltages applied to corresponding access lines 241, 242, and 243 and data lines 221 and 222 during a write operation of memory device 200. During the write operation, voltage V4 may be applied to a selected access line (such as access line 241). Voltage V5 may be applied to unselected access lines (such as access lines 242 and 243).

[0066] Voltages V4, V5, V6, and V7 may have different values. As an example, voltages V4 and V5 may have values of 3V and 0V, respectively. These values are example values. Different values may be used. Connection 297 may be applied with a voltage or may be coupled to ground.

[0067] The values of voltages V6 and V7 may be the same or different, depending on the information values (such as "0" or "1") stored in memory cells 210 and 211. For example, if memory cells 210 and 211 will store information with the same value, then the values of voltages V6 and V7 may be the same (such as V6 = V7). As an example, if the information stored in each of memory cells 210 and 211 is "0", then V6 = V7 = 0V. In another example, if the information stored in each of memory cells 210 and 211 is "1", then V6 = V7 = V+ (for example, V+ is a positive voltage (such as from 1V to 3V)).

[0068] In another example, if memory cells 210 and 211 will store information with different values, then the values of voltages V6 and V7 may be different (such as V6 ≠ V7). As an example, if "0" will be stored in memory cell 210, then V6 = 0V, and if "1" will be stored in memory cell 211, then V7 = V+ (for example, V+ is a positive voltage (such as from 1V to 3V)). As another example, if "1" will be stored in memory cell 210, then V6 = V+ (for example, V+ is a positive voltage (such as from 1V to 3V)), and if "0" will be stored in memory cell 211, then V7 = 0V.

[0069] A voltage range of 1V to 3V is used here as an example. Different voltage ranges may be used. In addition, instead of applying 0V (such as V6 = 0V or V7 = 0V) to a specific write data line (such as data line 221 or 222) to store information with the value "0" into a memory cell (such as memory cell 210 or 211) coupled to this specific write data line, a positive voltage (such as V6 > 0V or V7 > 0V) may be applied to this specific data line.

[0070] In Figure 4In the write operation of the memory device 200, the voltage V5 may have a value (e.g., V5 = 0V or V5 < 0V) such that the transistors T1 and T2 of each of the memory cells 212 to 215 (the unselected memory cells in this example) are turned off (e.g., avoided). The voltage V4 may have a value (e.g., V4 > 0V) to turn on the transistor T2 of each of the memory cells 210 and 211 (the selected memory cells in this example) and form a write path between the charge storage structure 202 of the memory cell 210 and the data line 221 and a write path between the charge storage structure 202 of the memory cell 211 and the data line 222. A current (e.g., a write current) may be formed between the charge storage structure 202 of the memory cell 210 (the selected memory cell) and the data line 221. This current may affect (e.g., change) the amount of charge on the charge storage structure 202 of the memory cell 210 to reflect the information value stored in the memory cell 210. A current (e.g., another write current) may be formed between the charge storage structure 202 of the memory cell 211 (the selected memory cell) and the data line 222. This current may affect (e.g., change) the amount of charge on the charge storage structure 202 of the memory cell 211 to reflect the information value stored in the memory cell 211.

[0071] In Figure 4 an example write operation, the value of the voltage V6 may cause the charge storage structure 202 of the memory cell 210 to discharge or charge such that the resulting charge on the charge storage structure 202 of the memory cell 210 (e.g., the charge remaining after the discharge or charge operation) may reflect the information value stored in the memory cell 210. Similarly, in this example, the value of the voltage V7 may cause the charge storage structure 202 of the memory cell 211 to discharge or charge such that the resulting charge on the charge storage structure 202 of the memory cell 211 (e.g., the charge remaining after the discharge or charge operation) may reflect the information value stored in the memory cell 211.

[0072] Figure 5 shows a memory device 200 having a separate access line (e.g., a separate word line) for transistors T1 and T2 of each memory cell according to some embodiments described herein Figure 2 of. Figure 5 The memory device 200 of Figure 2 may be a variant of the memory device 200 of. As Figure 5As shown, the memory device 200 may include access lines (e.g., word lines) 241, 241', 242, 242', 243, and 243' that can carry corresponding signals (e.g., word line signals) WL1, WL1', WL2, WL2', WL3, and WL3'. The access lines 241, 241', 242, 242', 243, and 243' may be electrically separated from each other. Each memory cell may be associated with two access lines (e.g., a read access line and a write access line).

[0073] The access lines 241, 242, and 243 may be read access lines. The access lines 241, 242, and 243 may be used to selectively turn on the corresponding transistors T1 (e.g., read transistors) of a selected memory cell (or selected memory cells) during a read operation to read information from the selected memory cell (or selected memory cells). The access lines 241, 242, and 243 may also be used to turn off the corresponding transistors T1 of a selected memory cell (or selected memory cells) during a write operation performed on a selected memory cell (or selected memory cells).

[0074] The access lines 241', 242', and 243' may be referred to as write access lines. The access lines 241', 242', and 243' may be used to selectively turn on the corresponding transistors T2 (e.g., write transistors) of a selected memory cell (or selected memory cells) during a write operation to store information in the selected memory cell (or selected memory cells). The access lines 241', 242', and 243' may also be used to turn off the corresponding transistors T2 of a selected memory cell (or selected memory cells) during a read operation performed on a selected memory cell (or selected memory cells).

[0075] As Figure 5 shown, each of the gates 251 and 252 of the corresponding transistors T1 and T2 may be electrically coupled to the corresponding access line. In the structure of the memory device 200 (see Figures 6A to 8 ), each of the gates 251 and 252 may be formed by a portion (e.g., a portion of the material) of the corresponding access line among the access lines 241, 241', 242', 242, 243, and 243'. As described above, the access lines (e.g., access lines 241 and 241') associated with a memory cell (e.g., memory cell 210) may be electrically separated from each other. Thus, the gate 251 of the transistor T1 and the gate 252 of the transistor T2 of the memory cell (e.g., memory cell 210) are also electrically separated from each other.

[0076] In Figure 2In the memory device 200, the gates 251 of different transistors T1 of memory cells associated with the same access line (e.g., a read access line) may be formed by different portions of the conductive material forming this access line. The gates 252 of different transistors T2 of memory cells associated with the same access line (e.g., a write access line) may be formed by different portions of the conductive material forming this access line.

[0077] For example, as Figure 2 shown, the gates 251 of the corresponding transistors T1 of memory cells 210 and 211 may be formed by two corresponding portions of a conductive material (or conductive materials) forming the access line 241. The gates 252 of the corresponding transistors T2 of memory cells 210 and 211 may be formed by two corresponding portions of a conductive material (or conductive materials) forming the access line 241'.

[0078] The gates 251 of the corresponding transistors T1 of memory cells 212 and 213 may be formed by two corresponding portions of a conductive material (or conductive materials) forming the access line 242. The gates 252 of the corresponding transistors T2 of memory cells 212 and 213 may be formed by two corresponding portions of a conductive material (or conductive materials) forming the access line 242'.

[0079] The gates 251 of the corresponding transistors T1 of memory cells 214 and 215 may be formed by two corresponding portions of a conductive material (or conductive materials) forming the access line 243. The gates 252 of the corresponding transistors T2 of memory cells 214 and 215 may be formed by two corresponding portions of a conductive material (or conductive materials) forming the access line 243'.

[0080] The access lines 241, 241', 242, 242', 243, and 243' may be used to access both memory cell groups 2010 and 2011. Each of the access lines 241, 241', 242, 242', 243, and 243' may be configured as a conductive line that may be driven (e.g., activated) by a separate driver (described below).

[0081] The memory device 200 may include drivers 231, 231', 232, 232', 233, and 233' respectively coupled to the access lines 241, 241', 242, 242', 243, and 243'. The drivers 231, 232, and 233 may be referred to as read drivers and may be respectively used to selectively drive (e.g., activate) the access lines 241, 242, and 243 during a read operation. The drivers 231', 232', and 233' may be referred to as write drivers and may be respectively used to selectively drive (e.g., activate) the access lines 241', 242', and 243' during a write operation.

[0082] Drivers 231, 231', 232, 232', 233, and 233' can be respectively coupled to access lines 241, 241', 242, 242', 243, and 243'. The drivers can be complementary metal oxide semiconductor (CMOS) drivers or other types of drivers operable to provide (e.g., drive) signals WL1, WL1', WL2, WL2', WL3', and WL3' respectively associated with access lines 241, 241', 242, 242', 243, and 243'. The signals WL1, WL1', WL2, WL2', WL3', and WL3' can be provided (e.g., biased) with different voltages depending on which operation (e.g., read or write operation) the memory device 200 is performing.

[0083] Drivers 231, 231', 232', 232, 233', and 233' can be configured to respectively drive access lines 241, 241', 242, 242', 243, and 243' one at a time during an operation (e.g., read or write operation) of the memory device 200 to access a selected memory cell (or a plurality of selected memory cells) among memory cells 210 to 215. The selected cell(s) can be referred to as the target cell(s). In a read operation, information can be read from a selected memory cell (or a plurality of selected memory cells). In a write operation, information can be stored in a selected memory cell (or a plurality of selected memory cells).

[0084] During an operation (such as a read or write operation performed on a selected memory cell), a driver coupled to an access line (selected access line) associated with the selected memory cell may apply different voltages to the selected access line (the conductive region of the selected access line). For example, during an operation to read information from memory cell 210 (such as a read operation), driver 231 may apply a voltage to line 241 to turn on transistor T1 of memory cell 210, and driver 231' may apply another voltage to line 241' to turn off transistor T2 of memory cell 210. In another example, during an operation to store in memory cell 210 (such as a write operation), driver 231 may apply a voltage to line 241 to turn off transistor T1 of memory cell 210, and driver 231' may apply another voltage to line 241' to turn on transistor T2 of memory cell 210. Separate drivers (such as drivers 231 and 231') that include access lines (such as access lines 241 and 241') associated with a memory cell (such as memory cell 210) may improve the operation of memory device 200. For example, the separate drivers may allow transistors T1 or T2 of a selected memory to be turned off (such as completely turned off) during a particular operation (such as a read or write operation) to improve the control of the current (such as a read current or a write current) associated with the selected memory cell.

[0085] The structure of memory device 200 described above with reference to Figures 2 to 5 is described below with reference to Figures 6A to 8 description.

[0086] For simplicity, the detailed description of the same elements of memory device 200 is not repeated in Figures 6A to 8 description. Figures 6A to 8 Some of the memory cells and associated data lines and access lines of memory device 200 schematically shown in Figure 2 are not shown. Figures 6A to 8 Some of the memory cells and associated data lines and access lines of memory device 200 that are not schematically shown in Figure 2 are also shown. For simplicity and ease of viewing, cross-sectional lines (such as hatching) are omitted from most of the elements shown in Figures 6A to 8 and other figures described herein. Some elements of memory device 200 may be omitted from a particular figure among the figures to avoid obscuring the description of one element (or several elements) described in this particular figure. The dimensions (such as physical structure) of the elements shown in the figures described herein are not drawn to scale.

[0087] Figure 6AShows the structure of a memory device 200 including a substrate 699 and levels 601 and 602 positioned one above the other (e.g., stacked) on the substrate 699, according to some embodiments described herein. Figure 6A Shows two levels 601 and 602 of the memory device 200 as an example. However, the memory device 200 includes a plurality of levels (e.g., up to 100 levels or more than 100 levels).

[0088] Figure 6A The X, Y, and Z directions shown in may represent directions corresponding to the three-dimensional (3D) structure of the memory device 200. For simplicity, Figure 6A Only a portion of the memory device 200 with respect to the X-Z direction is shown. The Z direction (e.g., the vertical direction) is the direction perpendicular to the substrate 699 (e.g., outward from the substrate 699). The Z direction is also perpendicular to the X direction and the Y direction (e.g., extending vertically from the X direction and the Y direction). The X direction and the Y direction are perpendicular to each other. Figure 6B Shows a top view (e.g., X-Y plan view) of the memory device 200 in the X-Y direction along line 6B-6B. Figure 6A The portion labeled " Figure 7A " in is shown in detail in Figure 7A .

[0089] In Figure 6A , the substrate 699 may be a semiconductor substrate (e.g., a silicon-based substrate) or other types of substrates. As shown in Figure 6A , each of the levels 601 and 602 may itself have memory cells (labeled "memory cells"). Thus, the levels 601 and 602 may be referred to as memory cell levels 601 and 602.

[0090] Each of the levels 601 and 602 may itself include access lines associated with the memory cells in the same level. Figure 6A Shows access lines (also referred to as "access lines") associated with signals WL0, WL1, WLi, WLj, and WL. Memory cells in different levels (e.g., levels 601 and 602) may not share access lines. For example, the memory cells in level 601 may not share access lines with the memory cells in level 602. As shown in Figure 6A , each memory cell may be between two corresponding portions (e.g., top and bottom access lines) of the access line and adjacent to (e.g., associated with) them. For example, the memory cell 210 may be associated with two corresponding portions of the access line associated with the signal WL1. In another example, the memory cell 299 may be associated with two corresponding portions of the access line associated with the signal WLi. Figure 2 The memory cell 299 is not schematically shown in.

[0091] As shown inFigure 6A As shown in, the memory device 200 may include data lines (also referred to as "data lines" or data lines BLA, BLB, BLC, BL1, BLD, and BLE) associated with signals BLA, BLB, BLC, BL1, BLD, and BLE. The data line associated with signal BL1 may correspond to Figure 2 data line 221 (associated signal BL1). Each of the data lines may include a conductive structure. For simplicity, Figure 6A only the conductive structures 760, 761, 762, and 763 of the data lines associated with signals BLC, BL1, BLD, and BLE are marked in. As Figure 6A shown in, each of the data lines may have a length extending in the Z direction through the tiers (through tiers 601 and 602), where the Z direction is perpendicular to the substrate 699. As Figure 6A shown in, the Z direction is also the direction from one tier to another (e.g., from one horizontal tier to another). Thus, each of the data lines (and their corresponding conductive structures) of the memory device 200 may have a length in the direction from one tier to another (e.g., from one horizontal tier to another).

[0092] The memory device 200 may include dielectric portions (which include dielectric materials) 795 between adjacent data lines (e.g., adjacent data lines BLC and BL1 and adjacent data lines BLD and BLE). Figure 6A Six data lines BLA, BLB, BLC, BL1, BLD, and BLE are shown as examples. The number of data lines of the memory device 200 may vary.

[0093] As Figure 6A shown in, the memory device 200 may also include conductive lines (e.g., common conductive lines) associated with signals PLT0 and PLT1. Each of these conductive lines may include a corresponding conductive structure, such as conductive structures 796 and 797. Each of the conductive structures 796 and 797 may include a conductive material (e.g., conductive doped polysilicon, metal, or other conductive material). Each of the conductive structures 796 and 797 may be a common conductive structure between adjacent memory cells in the Y direction ( Figure 6A ) for different tiers (e.g., tiers 601 and 602) and between adjacent memory cells in the X direction ( Figure 6B ) for the same tier (e.g., tier 602). Each of the conductive structures 796 and 797 of the corresponding conductive lines (e.g., the conductive lines associated with signal PLT0 or PLT1) may be coupled to connection 297 of the memory device 200 (or may be part of connection 297 of the memory device 200). During operation of the memory device, signals PLT0 and PLT1 may be supplied with a voltage or may be coupled to a ground potential. AsFigure 6A As shown, like data lines BLA, BLB, BLC, BL1, BLD, and BLE, each conductive structure 797 in the conductive lines (associated with signals PLT0 and PLT1) can have a length extending in the Z direction through the layers (through layers 601 and 602).

[0094] Figure 6B Shows a top view (e.g., cross-section) of the structure of memory device 200 along Figure 6A line 6B-6B, which includes Figure 6A a portion of layer 602. For simplicity, Figure 6B only some of the memory cells in layer 602 and some of the other data lines of memory device 200 (e.g., data lines associated with signals BLF, BLG, BLH, BLI, BLJ, BLK, and BLL) are shown in Figure 6B Also shown is Figure 6A a top view of some memory cells of memory device 200 not shown in Figure 6B Also shown is a top view of other conductive lines (e.g., common conductive lines) associated with signals PLT2 and PLT3. Figure 6A (described above) shows a side view of memory device 200 along line 6A-6A. Figure 6B The portion marked as “ Figure 7B ” in Figure 7B is shown in detail in

[0095] In Figure 6B , the access lines associated with signals WL0, WL1, WLi, and WLj are shown in a partially cut-away top view to show some portions of the underlying memory cells underlying these access lines. As Figure 6B shown, each of the access lines associated with signals WL0, WL1, WLi, and WLj can be a separate strip (e.g., a strip of conductive material) having a length in the Y direction, where the Y direction is perpendicular to the direction (e.g., the X direction) from one memory to the next memory in the same layer (e.g., layer 602) in the X direction. The access lines associated with signals WL0, WL1, WLi, and WLj can be separated (electrically separated) from each other in the X direction. As Figure 6B shown, the memory cells in the same layer (e.g., layer 602) can be arranged in the X direction (spaced apart from each other) and in the Y direction (spaced apart from each other). Memory cells in the X direction (e.g., adjacent memory cells) may not share access lines (e.g., may not share word lines). For example, as Figure 6BAs shown, the memory cell 210 (which is adjacent to (e.g., neighboring) the memory cell 299 and is positioned at a distance from the memory cell 299 in the X direction) may not share the access line associated with the signal WL1 with the memory cell 299 in the X direction.

[0096] As Figure 6C shown, each memory cell may be adjacent to two conductive regions (e.g., top and bottom conductive regions) of the access line and between the two conductive regions. For example, the access line associated with the signal WL1 may include a conductive region (e.g., top conductive region) 741T and a conductive region (e.g., bottom conductive region) 741B. The conductive regions 741T and 741B may be part of the access line 241 ( Figure 2 ) of the memory device 200. The conductive regions 741T and 741B are opposite to each other in the Z direction. With respect to the top view (with respect to the Figure 6A Z direction shown), the conductive region 741T may be positioned above (e.g., on top of) the memory cell 210. With respect to the top view (with respect to the Figure 6A Z direction shown), the conductive region 741B may be positioned below (e.g., beneath) the memory cell 210. As Figure 6B shown, each of the conductive regions 741T and 741B may be configured as a strip of conductive material that is electrically separated from neighboring conductive regions of other access lines (e.g., access lines associated with the signals WL0, WLi, and WLj).

[0097] In another example, as Figure 6B shown, the access line associated with the signal WLi may include a conductive region (e.g., top conductive region) 749T and a conductive region (e.g., bottom conductive region) 749B. The conductive regions 749T and 749B may be part of the access line associated with the memory cell 299. As Figure 6B shown, each of the conductive regions 749T and 749B may be configured as a strip of conductive material that is electrically separated from neighboring conductive regions of other access lines (e.g., access lines associated with the signals WL1, WLi, and WLj). The conductive regions 749T and 749B are opposite to each other in the Z direction. With respect to the top view (with respect to the Figure 6A Z direction shown), the conductive region 749T may be positioned above (e.g., on top of) the memory cell 299. With respect to the top view (with respect to the Figure 6A Z direction shown), the conductive region 749B may be positioned below (e.g., beneath) the memory cell 299.

[0098] In Figure 6B the example, the conductive regions 741T and 741B may be electrically coupled to each other through the connection 740. The connection 740 may include a conductive connection (which may include a conductive material (e.g., metal)). As Figure 6BAs shown, each of the other access lines (e.g., the access lines associated with signals WL0, WLi, and WLj) may also include top and bottom conductive regions, where the top and bottom conductive regions may also be electrically coupled to each other through corresponding connections 740.

[0099] Figure 6C Shown Figure 6B is an example of a variant of the memory device 200, where the conductive regions 741T and 741B are electrically separated from each other. Figure 6C The conductive regions 741T and 741B in Figure 5 may be portions of the access lines 241 and 241' in Figure 6C As shown in Figure 2 the conductive regions 741T and 741B of the access lines associated with signals WL1 and WL1' may be coupled to different drivers 231 and 231', respectively. The drivers 231 and 231' are the same as the Figure 6C drivers shown in

[0100] Figure 7A Shown Figure 6A is a side view (e.g., cross-section) of the portion of the memory device 200 labeled " Figure 7A ". Figure 7B Shows a portion of the memory device 200 along Figure 7A line 7B - 7B and Figure 6B a top view of the portion labeled " Figure 7B " in Figure 7C Shows a top view of a portion of the memory device 200 along Figure 7A line 7C - 7C. Figure 7D Shows a 3D view of the charge storage structure 702 of the memory device 200. Figure 7E Shows a 3D view of a portion of the memory device 200 including a conductive portion 797' that is coupled to a conductive structure 797 and extends into the internal region of the charge storage structure 702. Figure 7F Shows the same view as Figure 7E However, for easier viewing of the Figure 7E components shown in Figure 7F the dielectric material (dielectric portion) 715 is omitted and the conductive structure 797 is shown in dashed lines.

[0101] In Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E and Figure 7FIn [reference], the same elements of memory cells 210 and 299 and other elements of memory device 200 are given the same reference numerals. Thus, for simplicity, the description of the elements of memory cells 210 and 299 and Figure 7A other elements in [reference] also refers to Figure 7B , Figure 7C , Figure 7D , Figure 7E and Figure 7F the same elements shown in [reference]. Thus, some of the elements in Figure 7B , Figure 7C , Figure 7D , Figure 7D , Figure 7E and Figure 7F are not described separately.

[0102] Figure 7A show details of the cross-sections of levels 601 and 602 of memory device 200. As shown in Figure 7A , each of levels 601 and 602 may have different tiers (physical tiers) that are vertically positioned (e.g., stacked) on top of each other in the Z direction above substrate 699. For example, level 602 may include tiers 771 to 777. For simplicity, the tiers in level 601 are not labeled.

[0103] Each of the data lines (associated with signals BLC, BL1, BLD, and BLE) may be formed of a conductive structure (e.g., may include a conductive structure). Figure 7A show conductive structures 760, 761, 762, and 763 of the data lines associated with signals BLC, BL1, BLD, and BLE, respectively. Each of conductive structures 760, 761, 762, and 763 may include a conductive material (e.g., conductively doped polysilicon, metal, or other conductive material). As shown in Figure 7A , each of conductive structures 760, 761, 762, and 763 may have a length that extends in the Z direction through the levels (through levels 601 and 602), where the Z direction is perpendicular to substrate 699.

[0104] Conductive structures 760, 761, 762, and 763 may be electrically coupled to some of the elements of the corresponding memory cells in level 602 (e.g., memory cells 210 and 299) (e.g., the read and write channel regions of the corresponding transistors T1 and T2, described below). Each of conductive structures 760, 761, 762, and 763 is electrically separated from the access lines of memory device 200 (e.g., the access lines associated with signals WL1, WLi, and WL) by a corresponding dielectric portion (e.g., dielectric portions 725, 735, 745, and 755).

[0105] For simplicity, Figure 7AThe description describes the components of level 602. Level 601 may have components similar to those of the memory cell 210 (which have similar or the same markings). As Figure 7A shown, the conductive regions 741T and 741B may be located on levels 777 and 771 respectively. The conductive regions 741T and 741B may collectively be part of the access line 241 ( Figure 2 ). For example, the top and bottom conductive regions (or parts)). Alternatively, the conductive regions 741T and 741B may be parts of the access lines 241 and 241' of Figure 5 respectively. Each of the conductive regions 741T and 741B may include a conductive material (such as conductive doped polysilicon, metal, or other conductive materials).

[0106] The conductive region 741T may be electrically separated from the conductive structures 761 of the data line associated with the signal BL1 and the conductive structure 797 of the conductive line (such as a common conductive line) associated with the signal PLT1 through the corresponding dielectric part 725. The conductive region 741B is electrically separated from the conductive structures 761 and 797 through the corresponding dielectric part 735.

[0107] As Figure 7A shown, the memory cell 299 adjacent to the memory cell 210 in the X direction also includes conductive parts 749T and 749B (as parts of the access line associated with the signal WLi) located on levels 777 and 771 respectively, similar to the conductive regions 741T and 741B respectively.

[0108] In the memory device 200, adjacent memory cells in the X direction may not share an access line (such as a word line) or a number of access lines. For example, the memory cells 210 and 299 may not share one or a number of access lines. Therefore, the conductive regions 741T and 749T (which are located on the same level 777) may be electrically separated from each other. For example, the conductive regions 741T and 749T are not formed from the same piece of conductive material (such as not included in the same piece of conductive material). Similarly, the conductive regions 741B and 749B (which are located on the same level 771) may be electrically separated from each other. For example, the conductive regions 741B and 749B are not formed from the same piece of conductive material (such as not included in the same piece of conductive material).

[0109] As Figure 7A shown, the memory device 200 may include different dielectric parts located on different levels in the Z direction to electrically separate the components within the same level (in the Z direction) and to electrically separate the levels from each other. For example, as Figure 7AAs shown, the memory device 200 may include dielectric portions 717, 718, and 719 located on tiers 776, 774, and 772, respectively. The dielectric portions 717, 718, and 719 may electrically isolate the components within level 602 (in the Z direction). The memory device 200 may include a dielectric portion 765 that can electrically isolate the levels from each other (in the Z direction).

[0110] The dielectric portions 717, 718, 719, and 765 may have the same dielectric material or different dielectric materials. Example materials for the dielectric portions 717, 718, 719, and 765 include silicon oxide, silicon nitride, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), or other dielectric materials (e.g., other high-k dielectric materials).

[0111] As Figure 7A shown, the memory device 200 may include a charge storage structure 702 and a material 720 located on tier 775. The material 720 may also be referred to as portion 720. The material 720 is adjacent to (e.g., in contact with) the charge storage structure 702 and is electrically coupled to the charge storage structure 702. The material 720 may also be electrically coupled to a corresponding conductive structure (e.g., conductive structures 761 or 762) of a corresponding data line (e.g., a data line associated with signal BL1 or BLD). As Figure 7A shown, each of the memory cells 210 and 299 of the memory device 200 (and two other memory cells located below the memory cells 210 and 299) may include a transistor T2. The material 720 may form a portion of the channel region (e.g., the write channel region) of the transistor T2 of a corresponding memory cell (e.g., memory cell 210 or 299).

[0112] The material 720 (also referred to as portion 720) of a particular memory cell (e.g., memory cell 210) may form the source (e.g., source terminal), drain (e.g., drain terminal), or the channel region (e.g., the write channel region) between the source and drain of the transistor T2 of this particular memory cell (e.g., memory cell 210). For example, as Figure 7A shown, the source, channel region, and drain of the transistor T2 of the memory cell 210 may be formed of a monolithic same material (or alternatively, a combination of monolithic same materials), such as the material 720. Thus, the source, drain, and channel region of the transistor T2 of the memory cell 210 may be formed of the same material (e.g., material 720) of the same conduction type (e.g., n-type or p-type).

[0113] The material 720 (e.g., the write channel region of transistor T2) of a particular memory cell (e.g., memory cell 210) of the memory device 200 can be part of the write path for this particular memory cell. For example, the material 720 of memory cell 210 can be part of the write path of memory cell 210 that can carry a current (e.g., a write current) during a write operation to store information in memory cell 210. For example, during a write operation, in order to store information in Figure 7A memory cell 210, the material 720 of memory cell 210 can conduct a current (e.g., a write current) between the conductive structure 761 and the charge storage structure 702 of memory cell 210. The direction of the write current can be from the conductive structure 761 of the memory device 200 to the charge storage structure 702. In an example where transistor T2 is an NFET (e.g., an NMOS), the current (e.g., the write current) can include electron conduction of memory cell 210 (e.g., electron conduction in the direction from the conductive structure 761 through the material 720 (the channel region of transistor T2) to the charge storage structure 702).

[0114] The material 720 (portion 720) can include a structure of a semiconductor material (e.g., a piece (e.g., a layer)). In an example where transistor T2 is an NFET (as described above), the material 720 can include an n-type semiconductor material (e.g., n-type silicon).

[0115] In an example, the semiconductor material of portion 720 can include a graded doping region such that the semiconductor material of portion 720 can have different regions (e.g., different silicon regions) with different doping concentrations. One of such regions of the semiconductor material (e.g., the middle region) can be undoped (e.g., undoped silicon or undoped polysilicon).

[0116] In another example, the semiconductor material forming the material 720 can include a piece of oxide material. Examples of the oxide material for the material 720 include a semiconducting oxide material, a transparent conducting oxide material, and other oxide materials.

[0117] As an example, the material 720 can include at least one of the following: tin zinc oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO x , In2O3), tin oxide (SnO2), titanium oxide (TiO x ), zinc oxide nitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z) Indium zinc oxide (In x Zn y O z ) Indium gallium zinc oxide (In x Ga y Zn z O a ) Zirconium indium zinc oxide (Zr x In y Zn z O a ) Hafnium indium zinc oxide (Hf x In y Zn z O a ) Tin indium zinc oxide (Sn x In y Zn z O a ) Aluminum tin indium zinc oxide (Al x Sn y In z Zn a O d ) Silicon indium zinc oxide (Si x In y Zn z O a ) Zinc tin oxide (Zn x Sn y O z ) Aluminum zinc tin oxide (Al x Zn y Sn z O a ) Gallium zinc tin oxide (Ga x Zn y Sn z O a ) Zirconium zinc tin oxide (Zr x Zn y Sn z O a ) Indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP).

[0118] Using the above materials in the memory device 200 provides improvements and benefits to the memory device 200. For example, during a read operation, in order to read information from a selected memory cell (e.g., memory cell 210), the charge from the charge storage structure 702 of the selected memory cell may leak into the transistor T2 of the selected memory cell. Using the above materials for the channel region of the transistor T2 (e.g., material 720) can reduce or prevent this leakage. This improves the accuracy of the information read from the selected memory cell and the retention of the information stored in the memory cells of the memory device (e.g., memory device 200) described herein.

[0119] The above materials are examples of Material 720. However, other materials different from the above materials (e.g., relatively high bandgap materials) can be used.

[0120] As Figure 7A shown, charge storage structure 702 is adjacent to (e.g., in contact with) Material 720 and is electrically coupled to Material 720. Charge storage structure 702 can correspond to Figure 2 the charge storage structure 202 of memory device 200 schematically shown in Figure 7A shown, charge storage structure 702 is electrically separated from the conductive structure 797 of the corresponding conductive line (e.g., the conductive line associated with signal PLT1) by a dielectric portion (dielectric material) 715. Charge storage structure 702 can include a charge storage material (or combination of materials), which can include a sheet (e.g., a layer) of semiconductor material (e.g., polysilicon), a sheet (e.g., a layer) of metal, or a sheet of material (or materials) that can trap charges. The materials of charge storage structure 702 and conductive regions 741T, 741B, 749T, and 749B can be the same or different.

[0121] As Figure 7D shown, charge storage structure 702 can have multiple portions including portions 702A and 702B (e.g., horizontal portions) and a portion (e.g., vertical portion) 702C. Portions 702A, 702B, and 702C can form a U-shaped structure and can have an internal region 702I. Internal region 702I is adjacent to portions 702A, 702B, and 702C (e.g., partially surrounded by portions 702A, 702B, and 702C), such that internal region 702I does not have the material (conductive material) of charge storage structure 702 (e.g., does not have the material of portions 702A, 702B, and 702C).

[0122] As Figure 7D shown, portions 702A and 702B (e.g., the longer portions of the U-shaped structure) can be opposite to each other in the Z direction, which is also perpendicular to the direction from memory cell 210 to memory cell 299 or parallel to the direction from one level (e.g., Figure 7A level 601 in Figure 7A to another level (e.g.,

[0123] As Figure 7A and Figure 7EAs shown, the conductive portion 797' can be adjacent to (e.g., in contact with) the conductive structure 797 and electrically coupled to the conductive structure 797. The conductive portion 797' can comprise a conductive material (e.g., conductively doped polysilicon, metal, or other conductive material). The material of the conductive portion 797' can be the same as or different from the materials of the conductive structures 796 and 797.

[0124] As Figure 7A and Figure 7E shown, the charge storage structure 702 can be separated (electrically separated) from the conductive structures 797 and the conductive portion 797' by the dielectric material 715. The conductive portion 797' can have a length in the X direction, which is also the direction from the conductive structure 797 to the charge storage structure 702. As Figure 7A and Figure 7F shown, a portion of the conductive portion 797' can extend into the inner region 702I and can be located between the portions 702A and 702B. The conductive portion 797' ( Figure 7E ) is separated from the portions 702A, 702B, and 702C by the dielectric portion 715. The dielectric material 715 can comprise silicon dioxide, a high-k dielectric, or other dielectric materials. A high-k dielectric material is a dielectric material having a dielectric constant greater than that of silicon dioxide.

[0125] The structure of the memory cells (e.g., memory cell 210) of the memory device 200, including the U-shaped structure of the charge storage structure 702, can provide sufficient charge storage capacity in the memory cells. Thus, the leakage of the current (e.g., current I OFF ) associated with the transistor T2 (e.g., associated with the portion 720) can be relatively relaxed. Thus, the material of the portion 720 can not be limited to a specific material (e.g., a relatively low current leakage material), but can be selected from the different materials described above, including silicon and polysilicon. This can allow the memory device 200 to have advantages (e.g., more choices of materials for the portions 710 and 720) compared to some memory devices in which the channel regions of the transistors in the memory cells are limited to specific materials (e.g., materials different from silicon and polysilicon).

[0126] The memory device 200 ( Figure 7A ) can comprise a portion 710 on the tier 773. The portion 710 is adjacent to one side (e.g., the bottom side) of the dielectric portion 718 and is separated from the portion 720 and the charge storage structure 702 by the dielectric portion 718. The portion 720 and the charge storage structure 702 are adjacent to the other side (e.g., the top side) of the dielectric portion 718 and are separated from the portion 710 by the dielectric portion 718. The portion 710 can be electrically coupled to the conductive structure 797. The portion 710 can also be electrically coupled to one of the conductive structures 761 and 762 of the corresponding data line (the data line associated with the signal BL1 or BLD). AsFigure 7A As shown, each of memory cells 210 and 299 (and two other memory cells located below memory cells 210 and 299) may include transistor T1. Portion 710 may form a portion of the channel region (e.g., read channel region) of transistor T1 of a corresponding memory cell (e.g., memory cell 210 or 299).

[0127] Portion 710 of a particular memory cell (e.g., memory cell 210) may form the source (e.g., source terminal), drain (e.g., drain terminal), or channel region (e.g., write channel region) between the source and drain of transistor T1 of this particular memory cell (e.g., memory cell 210). For example, as Figure 7A shown, the source, channel region, and drain of transistor T1 of memory cell 210 may be formed of a monolithic same material (or alternatively, a combination of monolithic same materials), such as material 710. Thus, the source, drain, and channel region of transistor T1 of memory cell 210 may be formed of the same material (e.g., the material of portion 710) of the same conduction type (e.g., n-type or p-type).

[0128] Portion 710 may include a semiconductor material. Example materials of portion 710 include silicon, polysilicon (e.g., undoped or doped polysilicon), germanium, silicon-germanium, or other semiconductor materials and semi-conductive oxide materials (oxide semiconductors, such as SnO or other oxide semiconductors).

[0129] In an example, portion 710 may include a graded doping region such that the semiconductor material of portion 710 may have different regions (e.g., different polysilicon regions) with different doping concentrations. One of such regions (e.g., the middle region) of the semiconductor material may be undoped (e.g., undoped silicon or undoped polysilicon).

[0130] The semiconductor material of portion 710 and the semiconductor material of portion 720 (material 720) may have different conduction types (e.g., n-type conductivity and p-type conductivity). Alternatively, the semiconductor material of portion 710 and the semiconductor material of portion 720 (material 720) may have the same conduction type (e.g., n-type conductivity or p-type conductivity).

[0131] Portion 710 (e.g., the read channel region of transistor T1) of a particular memory cell (e.g., memory cell 210) of memory device 200 may be a portion of the read path of this particular memory cell. For example, portion 710 of memory cell 210 may be a portion of the read path of memory cell 210 that may carry a current (e.g., read current) during a read operation to read information from memory cell 210. For example, during a read operation, in order to read from Figure 7ATo read information from memory cell 210 in FIG. 2 , portion 710 of memory cell 210 may conduct current (e.g., a read current) between conductive structure 761 and conductive structure 797 (e.g., a portion of connection 297). The direction of the read current may be from conductive structure 761 through portion 710 to conductive structure 797. In an example in which transistor T1 is a PFET (e.g., a PMOS), the current (e.g., a read current) may include hole conduction of memory cell 210 (e.g., hole conduction in a direction from conductive structure 761 through portion 710 (a channel region of transistor T1) to conductive structure 797).

[0132] In examples where transistor T1 is a PFET and transistor T2 is an NFET, the material forming portion 710 may have a different conductivity type than material 720. For example, portion 710 may include a region of p-type semiconductor material, such as p-type silicon, and material 720 may include a region of n-type semiconductor material, such as n-type gallium phosphide (GaP).

[0133] like Figure 7A , conductive region 741B may be opposite (in the Z direction) to portion 710 of transistor T1 of memory cell 210 and may form the gate of transistor T1 of memory cell 210. Conductive region 741T may be opposite (in the Z direction) to portion 720 of memory cell 210 and charge storage structure 702 and may form the gate of transistor T2 of memory cell 210. Thus, the same signal (e.g., WL1) may be used to control (e.g., turn on or off) structures (e.g., Figure 6B ) in the memory cell 210, wherein the conductive regions 741T and 741B may be electrically coupled (eg, shorted) to each other (eg, by Figure 6B Alternatively, different signals (e.g. Figure 6C Signals WL1 and WL1′ in FIG. 7A and FIG. 7B may be used and provided to conductive regions 741T and 741B separately to control transistors T1 and T2 of memory cell 210 separately.

[0134] like Figure 7A , conductive region 749B may be opposite (in the Z direction) to portion 710 of transistor T1 of memory cell 299 and may form the gate of transistor T1 of memory cell 299. Conductive region 749T may be opposite (in the Z direction) to portion 720 of memory cell 299 and charge storage structure 702 and may form the gate of transistor T1 of memory cell 299. Thus, the same signal (e.g., WLi) may be used to control (e.g., turn on or off) structures (e.g., Figure 6B ) in memory cell 299, wherein conductive regions 749T and 749B may be electrically coupled (eg, shorted) to each other (eg, byFigure 6B Alternatively, different signals (e.g. Figure 6C Signals WLi and WLi′ in FIG. 740 may be used and provided separately to conductive regions 749T and 749B to separately control transistors T1 and T2 of memory cell 299 .

[0135] like Figure 7A , memory cells of memory device 200, such as memory cells 210, 299, and two memory cells (not labeled) positioned below memory cells 210 and 299, have similar or identical structures. Therefore, for simplicity, detailed descriptions of memory cell 299 and other memory cells are omitted.

[0136] In operation, at least a portion of charge storage structure 702 (e.g., portion 702B) can modulate the potential in portion 710 (e.g., the read channel region of transistor T1). This in turn modulates the current in portion 710 (e.g., the read current) and provides several orders of magnitude difference between different states, which can be used to determine the value of information in a memory cell (e.g., memory cell 210).

[0137] The shape of the charge storage structure 702 (eg, a U-shaped structure) and its arrangement with the conductive portion 797' (eg, Figure 7A ) may allow the charge storage structure 702 to have a relatively high storage capacity (e.g., high capacitance). Therefore, the material 720 (e.g., the write channel region of the transistor T2) may not be limited to a specific material, but may be selected from the above-mentioned different materials (e.g., semiconductor materials, semiconductive oxide materials, or other materials that can conduct current). In addition, Figure 7A In the structure of the memory device 200 shown in FIG. 1 , at least a portion (eg, portion 710) of the transistor T1 (eg, the read transistor) may be designed to provide a relatively high current (eg, current I ON ), regardless of the cell retention of the memory cell. This allows a relatively high read signal window for a read operation. In the structure of the memory device 200, the read signal window can be based primarily on the read current in the portion 710 (e.g., the read channel region). This can result in a higher read signal window, a higher speed, or both. The information stored in the charge storage structure 702 is maintained during a read operation of the memory device 200.

[0138] As described above, the structure of memory device 200 may improve footprint (eg, smaller lateral footprint) and cell density (eg, smaller device volume for a given number of memory cells) compared to some conventional memory devices (eg, conventional DRAM devices).

[0139] Figure 8Shows a variant of the memory device 200 including an additional semiconductor portion according to some embodiments described herein. Figure 7A The difference between the memory device 200 in Figure 8 and the memory device 200 of Figure 8 includes the portions 710', 710", 720', 720" and 720'" in Figure 7A and Figure 8 For simplicity, the description of the same elements of the memory device 200 in

[0140] is not repeated. Figure 8 As shown in Figure 8 the portions 710' and 710" can be located on the level 772 and separated from each other by the dielectric portion 719. The portion 710' can be coupled to the conductive structure 761 and the portion 710. As shown in

[0141] In Figure 8 the portions 720' and 720" can be located between the conductive structure 761 and the charge storage structure 702. Thus, the portions 720' and 720" can be collectively regarded as a portion (e.g., the portion 720 in Figure 7A In Figure 8 the portion 720' is between the conductive structure 761 and the portion 720". The portion 720' can be coupled to the conductive structure 761. The portion 720" can be coupled to the charge storage structure 702.

[0142] Portion 720”' may be coupled to portion 720' at a portion (e.g., a left end portion) of portion 720' adjacent to conductive structure 761. Portions 720” and 720”' may include semiconductor materials of the same conductivity type. For example, the portion may have a semiconductor material of n-type conductivity. Portions 720” and 720”' may have semiconductor materials of the same conductivity type as portion 720'. Each of portions 720” and 720”' may have a semiconductor material having a doping concentration higher than that of the semiconductor material of portion 720. Portions 720” and 720”' may have a conductivity type (e.g., n-type) different from the conductivity type (e.g., p-type) of portions 710' and 710”.

[0143] The description above with reference to Figures 6A to 8 shows that elements (e.g., memory cells and access lines) may be arranged (e.g., formed) in different levels of memory device 200. This may allow multiple levels (e.g., levels 601 and 602 and similar levels) of memory device 200 to be formed together. Thus, the cost (e.g., cost per bit) of forming memory device 200 may be reduced. In addition, the length of the conductive structure of the data line may be based on the number of levels. The hierarchical structure and the memory cell structure of the memory cells of memory device 200 (as Figure 7A shown) may have a relatively compact size (e.g., each memory cell includes a relatively small (e.g., thin) size in the Z direction). This may improve (e.g., increase) the area efficiency of the memory device compared to some similar memory devices. The compact size (e.g., relatively small memory cell size in the Z direction) may also improve (e.g., shorten) the length of the data lines of memory device 200 (e.g., the vertical length in the Z direction). This may reduce the coupling capacitance between the data lines of memory device 200 and the total capacitance of the data lines. The reduction of these capacitances may result in improved operation of memory device 200.

[0144] The description of the devices (e.g., memory devices 100 and 200) and methods (e.g., the operations of memory devices 100 and 200) is intended to provide a general understanding of the structures of the various embodiments and is not intended to provide a complete description of all elements and features of the devices that may use the structures described herein. The devices herein refer to, for example, an apparatus (e.g., any of memory devices 100 and 200) or a system (e.g., an electronic product that may include any of memory devices 100 and 200).

[0145] The description above with reference to Figures 1 to 8Any of the described components can be implemented in numerous ways, including via software simulation. Thus, a device (such as memory devices 100 and 200) or portions of each of these memory devices can herein be characterized generally as "modules" (or "a module"). Such modules can include, depending on the expectations and / or requirements of a particular implementation of each embodiment, hardware circuitry, single and / or multi-processor circuitry, memory circuitry, software program modules and objects, and / or firmware and combinations thereof. For example, such modules can be included in system operation simulation packages, such as software electrical signal simulation packages, power usage and range simulation packages, capacitance-inductance simulation packages, power / thermal dissipation simulation packages, signal transmission-reception simulation packages, and / or combinations of software and hardware for operating or simulating the operation of various possible embodiments.

[0146] The memory devices described herein (such as memory devices 100 and 200) can be included in a device (such as an electronic circuitry), such as a high-speed computer, communication and signal processing circuitry, single or multi-processor modules, single or multiple embedded processors, multi-core processors, message information switches, and specialized modules including multi-layer multi-chip modules. Such devices can further be included as sub-components within a variety of other devices (such as electronic systems), such as televisions, cellular phones, personal computers (such as laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (such as MP3 (Moving Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (such as heart monitors, blood pressure monitors, etc.), set-top boxes, and others.

[0147] The foregoing references Figures 1 to 8 The described embodiments include devices and methods of operating the devices. One of the devices includes a first conductive structure, a second conductive structure, a conductive portion coupled to one of the conductive structures, and a memory cell. The memory cell includes different semiconductor portions positioned at different levels of the device and separated from each other by a dielectric portion. The first semiconductor portion is coupled to the first and second conductive structures. The second semiconductor portion is coupled to the first conductive structure. The memory cell includes a charge storage structure coupled to the second semiconductor portion. The charge storage structure includes multiple portions. A portion of the conductive portion is positioned between portions of the charge storage structure and separated from the charge storage structure by a dielectric material. Other embodiments including additional devices and methods are described.

[0148] In the detailed description and claims, the term "on" as used with respect to two or more elements (e.g., materials), one "on" another means that there is at least some contact between the elements (e.g., between the materials). The term "above" means that the elements (e.g., materials) are in close proximity, but may have one or more additional intervening elements (e.g., materials) such that contact is possible but not required. Neither "on" nor "above" implies any directionality as used herein, unless so stated.

[0149] In the detailed description and claims, the terms "first", "second", "third", etc. are used only as labels and are not intended to impose numerical requirements on their objects.

[0150] In the detailed description and claims, a list of items joined by the term "at least one of..." can mean any combination of the listed items. For example, if the items A and B are listed, then the phrase "at least one of A and B" means only A, only B, or A and B. In another example, if the items A, B, and C are listed, then the phrase "at least one of A, B, and C" means only A, only B, only C, A and B (excluding C), A and C (excluding B), B and C (excluding A), or all of A, B, and C. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

[0151] In the detailed description and claims, a list of items joined by the term "one of..." can mean only one of the listed items. For example, if the items A and B are listed, then the phrase "one of A and B" means only A (excluding B) or only B (excluding A). In another example, if the items A, B, and C are listed, then the phrase "one of A, B, and C" means only A, only B, or only C. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

[0152] The foregoing description and drawings illustrate some embodiments of the invention to enable those skilled in the art to practice the embodiments of the invention. Other embodiments may incorporate structural, logical, electrical, process, and other variations. Examples merely represent possible variations. Portions and features of some embodiments may be included in portions and features of other embodiments or may replace portions and features of other embodiments. Many other embodiments will be apparent to those skilled in the art after reading and understanding the foregoing description.

[0153] type

Claims

1. A device, comprising: A first conductive structure; A second conductive structure; A memory cell, comprising: A first semiconductor portion positioned on a first tier of the device and coupled to the first and second conductive structures; A dielectric portion positioned on a second tier of the device and having a first side adjacent to the first semiconductor portion; A second semiconductor portion positioned on a third tier of the device and adjacent to a second side of the dielectric portion, the second semiconductor portion being coupled to the first conductive structure; And A charge storage structure positioned on the third tier and coupled to the second semiconductor portion, the charge storage structure comprising a first portion, a second portion opposite the first portion, and a third portion joining the first and second portions; And A conductive portion coupled to the second conductive structure, the conductive portion positioned on the third tier, a portion of the conductive portion being positioned between the first and second portions of the charge storage structure and separated from the first, second, and third portions of the charge storage structure by a dielectric material.

2. The device according to claim 1, wherein the first conductive structure is part of a data line of the device.

3. The device according to claim 1, wherein the second conductive structure is part of a ground connection of the device.

4. The device according to claim 1, wherein the first and second semiconductor portions have different conductivity types.

5. The device according to claim 1, wherein the first and second semiconductor portions have the same conductivity type.

6. The device according to claim 1, wherein the second semiconductor portion comprises a semiconductive oxide material.

7. The device according to claim 1, wherein the dielectric material has a dielectric constant greater than that of silicon dioxide.

8. The device according to claim 1, further comprising: A third semiconductor portion positioned on a fourth tier of the device and coupled to the first semiconductor portion and the first conductive structure; A fourth semiconductor portion positioned on the fourth tier and coupled to the first semiconductor portion and the second conductive structure; And An additional dielectric portion positioned on the fourth tier and between the third and fourth semiconductor portions.

9. The device according to claim 8, wherein the third and fourth semiconductor portions have p-type conductivity.

10. The device according to claim 1, further comprising: A third semiconductor portion positioned on a fourth tier of the device and coupled to the second semiconductor portion and the first conductive structure, wherein: The second semiconductor portion comprises a first region and a second region, the first region being positioned between the first conductive structure and the second region, and the second region having a higher doping concentration than the first region.

11. The device according to claim 10, wherein the third semiconductor portion and the second region of the second semiconductor portion have n-type conductivity.

12. A device, comprising: A data line, comprising a first conductive structure having a length in a first direction; A second conductive structure having a length in the first direction; A memory cell coupled to the first and second conductive structures, the memory cell comprising: A first transistor including a first channel region coupled to the first and second conductive structures; A second transistor including a second channel region coupled to the first conductive structure; And A charge storage structure having a U-shaped structure coupled to the second channel region; A conductive portion coupled to the second conductive structure, the conductive portion positioned between the second conductive structure and the charge storage structure and separated from the charge storage structure by a dielectric material; A first conductive region separated from the first channel region and forming a gate of the first transistor, the first conductive region having a length in a second direction; and A second conductive region separated from the second channel region and forming a gate of the second transistor, the second conductive region having a length in the second direction.

13. The apparatus of claim 12, wherein the conductive portion has a length in a direction from the second conductive structure to the charge storage structure.

14. The apparatus of claim 12, wherein the first channel region includes a first semiconductor material having a first conductivity type, and the second channel region includes a second semiconductor material having a second conductivity type.

15. The apparatus of claim 12, wherein the first channel region includes a first semiconductor material having p-type conductivity, and the second channel region includes a second semiconductor material having n-type conductivity.

16. The apparatus of claim 12, wherein the first channel region includes a first semiconductor material having n-type conductivity, and the second channel region includes a second semiconductor material having n-type conductivity.

17. The apparatus of claim 12, wherein the first and second conductive regions are electrically separated from each other.

18. The apparatus of claim 12, wherein the first and second conductive regions are electrically coupled to each other.

19. The apparatus of claim 12, further comprising: A first driver for turning on the first transistor during an operation performed on the memory cell; And A second driver for turning off the second transistor during the operation.

20. The apparatus of claim 12, further comprising: A first driver for turning off the first transistor during an operation performed on the memory cell; And A second driver for turning on the second transistor during the operation.

21. An apparatus comprising: Layers positioned one above the other, each of the layers including memory cells; A first data line, a second data line, and a conductive line, each of the conductive line and the first and second data lines including a conductive structure extending through the layers; A first memory cell and a second memory cell, which are included in the memory cells of one of the levels, the first memory cell being positioned at a distance from the second memory cell in a direction perpendicular to the direction from one level to another level, each of the first and second memory cells comprising: A first semiconductor portion, which is positioned on a first tier of the device and coupled to first and second conductive structures; A dielectric portion, which is positioned on a second tier of the device and has a first side adjacent to the first semiconductor portion; A second semiconductor portion, which is positioned on a third tier of the device and adjacent to a second side of the dielectric portion, the second semiconductor portion being coupled to the first conductive structure; And A charge storage structure, which is positioned on the third tier and coupled to the second semiconductor portion, the charge storage structure comprising a first portion, a second portion opposite the first portion, and a third portion joining the first and second portions; A first conductive portion, which is coupled to the conductive structure of the conductive line, the first conductive portion being positioned between the first and second portions of the charge storage structure of the first memory cell and separated from the first, second, and third portions of the charge storage structure of the first memory cell by a first dielectric material; And A second conductive portion, which is coupled to the conductive structure of the conductive line, the second conductive portion being positioned between the first and second portions of the charge storage structure of the second memory cell and separated from the first, second, and third portions of the charge storage structure of the second memory cell by a second dielectric material.

22. The device according to claim 21, wherein the conductive line is a part of the ground connection of the device.

23. The device according to claim 21, further comprising: A first conductive region, which is opposite to the first semiconductor portion of the first memory cell; A first additional conductive region, which is opposite to the second semiconductor portion of the first memory cell; A second conductive region, which is opposite to the first semiconductor portion of the second memory cell and electrically separated from the first conductive region; And A second additional conductive region, which is opposite to the second semiconductor portion of the second memory cell and electrically separated from the first additional conductive region.

24. The device according to claim 23, wherein each of the first conductive region, the first additional conductive region, the second conductive region, and the second additional conductive region has a length in a direction perpendicular to the direction from the first memory cell to the second memory cell.

25. The device according to claim 23, wherein the first conductive region is electrically coupled to the first additional conductive region, and the second conductive region is electrically coupled to the second additional conductive region.

26. The device according to claim 23, wherein the first conductive region is electrically separated from the first additional conductive region, and the second conductive region is electrically separated from the second additional conductive region.

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