Memory device having through-stack contact via structure contacting multiple stacks and method of manufacturing same

Abstract

A memory device includes a first layer structure including a first alternating stack of first layers and a second alternating stack of first layers; a second layer structure overlying or underlying the first layer structure and including a first second layer alternating stack and a second second layer alternating stack laterally spaced apart from each other by a jumper alternating stack; and a memory stack structure extending vertically through the respective set of at least two alternating stacks. Each of the alternating stacks includes a respective vertical alternating sequence of insulating layers and conductive layers. A conductive path electrically connects a first first conductive layer within the first first layer alternating stack, a second first conductive layer within the second first layer alternating stack, a first second conductive layer within the jumper wire alternating stack, a first layer contact via structure, and a second layer contact via structure.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Non - Provisional Application No. 18 / 455,079, filed on August 24, 2023, in the United States Patent and Trademark Office, entitled "MEMORY DEVICE WITH THROUGH - STACK CONTACT VIA STRUCTURES WHICH CONTACT PLURAL STACKS AND METHOD OF MAKING THE SAME", and the entire contents of the non - provisional application are hereby incorporated by reference for all purposes. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly, to three - dimensional memory devices including through - stack contact via structures that contact multiple stacks and methods of manufacturing the same. Background Art

[0004] A three - dimensional vertical NAND string with one bit per cell is disclosed in the article "Novel Ultra High Density Memory With A Stacked - Surrounding Gate Transistor (S - SGT) Structured Cell" by T. Endoh et al., in the Proceedings of the IEDM (2001), pages 33 - 36. Summary of the Invention

[0005] According to one aspect of the present disclosure, a memory device is provided, the memory device comprising: a first layer structure including a first first-layer alternating stack and a second first-layer alternating stack, wherein each of the first first-layer alternating stack and the second first-layer alternating stack includes a respective vertical alternating sequence of a first-layer insulating layer and a first-layer conductive layer; a second layer structure overlying or underlying the first layer structure and including a first second-layer alternating stack and a second second-layer alternating stack laterally spaced apart from each other by a passive alternating stack, wherein each of the first second-layer alternating stack, the second second-layer alternating stack, and the passive alternating stack includes a respective vertical alternating sequence of a second-layer insulating layer and a second-layer conductive layer; a first memory stack structure vertically extending through the first first-layer alternating stack and the first second-layer alternating stack; a second memory stack structure vertically extending through the second first-layer alternating stack and the second second-layer alternating stack, wherein each of the first memory stack structure and the second memory stack structure includes a respective vertical semiconductor channel and a respective set of memory elements located at levels of the first-layer conductive layer and the second-layer conductive layer; and a conductive path including a first first-layer conductive layer within the first first-layer alternating stack, a first second-layer conductive layer within the passive alternating stack, a second first-layer conductive layer within the second first-layer alternating stack, a first-layer contact via structure, and a second-layer contact via structure, the first-layer contact via structure contacting the first first-layer conductive layer and a first portion of the first second-layer conductive layer within the passive alternating stack, and the second-layer contact via structure contacting the second first-layer conductive layer and a second portion of the first second-layer conductive layer within the passive alternating stack.

[0006] According to another aspect of the present disclosure, a method of forming a memory device is provided. The method includes: forming a first layer structure over a substrate, the first layer structure including a first first-layer alternating stack and a second first-layer alternating stack, wherein each of the first first-layer alternating stack and the second first-layer alternating stack includes a corresponding vertical alternating sequence of a first layer insulating layer and a first layer conductive layer; forming a second layer structure over the substrate, the second layer structure including a first second-layer alternating stack and a second second-layer alternating stack that are laterally spaced apart from each other by a passive alternating stack, wherein each of the first second-layer alternating stack, the second second-layer alternating stack, and the passive alternating stack includes a corresponding vertical alternating sequence of a second layer insulating layer and a second layer conductive layer, and wherein the second layer structure is formed above or below the first layer structure; forming a first memory stack structure that vertically extends through the first first-layer alternating stack and the first second-layer alternating stack; forming a second memory stack structure that vertically extends through the second first-layer alternating stack and the second second-layer alternating stack, wherein each of the first memory stack structure and the second memory stack structure includes a corresponding vertical semiconductor channel and a corresponding set of memory elements located at levels of the first layer conductive layer and the second layer conductive layer; and forming a first layer contact via structure and a second layer contact via structure, thereby providing a conductive path that includes a first first-layer conductive layer within the first first-layer alternating stack, a first second-layer conductive layer within the passive alternating stack, a second first-layer conductive layer within the second first-layer alternating stack, the first layer contact via structure, and the second layer contact via structure, wherein: the first layer contact via structure contacts the first first-layer conductive layer and a first portion of the first second-layer conductive layer within the passive alternating stack; and the second layer contact via structure contacts the second first-layer conductive layer and a second portion of the first second-layer conductive layer within the passive alternating stack. Description of the Drawings

[0007] Figure 1 is a vertical cross-sectional view of a first exemplary structure after forming an alternating stack of a dielectric isolation layer, a first insulating layer, and a first sacrificial material layer, and a first stepped surface, according to an embodiment of the present disclosure.

[0008] Figure 2 is a vertical cross-sectional view of a first exemplary structure after forming a first insulating pad and a first sacrificial pad over the first stepped surface, according to an embodiment of the present disclosure.

[0009] Figure 3 is a vertical cross-sectional view of a first exemplary structure after forming a first stepped dielectric material portion, according to an embodiment of the present disclosure.

[0010] Figure 4is a vertical cross-section of a first exemplary structure after forming an interlayer dielectric layer and a first memory opening.

[0011] Figure 5A is a vertical cross-section of a first exemplary structure after forming a first support opening and a first contact opening.

[0012] Figure 5B is Figure 5A a top view of a first exemplary structure. The articulated vertical plane A-A' is Figure 5A the plane of the vertical cross-section.

[0013] Figure 6 is a vertical cross-section of a first exemplary structure after forming a first sacrificial memory opening filling structure, a first sacrificial support opening filling structure, and a first sacrificial contact opening filling structure.

[0014] Figure 7 is a vertical cross-section of a first exemplary structure after forming a second alternating stack of a second insulating layer and a second sacrificial material layer, and a second stepped surface.

[0015] Figure 8 is a vertical cross-section of a first exemplary structure after forming a second insulating liner and a second sacrificial liner on the second stepped surface.

[0016] Figure 9 is a vertical cross-section of a first exemplary structure after forming a second stepped dielectric material portion and an insulating capping layer.

[0017] Figure 10 is a vertical cross-section of a first exemplary structure after forming a multi-layer support opening and a multi-layer contact opening.

[0018] Figure 11 is a vertical cross-section of a first exemplary structure after forming a sacrificial support opening filling structure and a sacrificial contact opening filling structure.

[0019] Figure 12 is a vertical cross-section of a first exemplary structure after forming a support pillar structure.

[0020] Figure 13 is a vertical cross-section of a first exemplary structure after forming a dielectric capping layer.

[0021] Figure 14is a vertical cross - sectional view of a first exemplary structure after forming a memory opening according to an embodiment of the present disclosure.

[0022] Figure 15 is a vertical cross - sectional view of a first exemplary structure after forming a memory opening filling structure according to an embodiment of the present disclosure.

[0023] Figure 16A is a vertical cross - sectional view of a first exemplary structure after forming a contact - level dielectric layer and a contact via cavity according to an embodiment of the present disclosure.

[0024] Figure 16B is Figure 16A a top - view of the first exemplary structure. The hinged vertical plane A - A' is Figure 16A the plane of the vertical cross - sectional view of

[0025] Figure 17 is a vertical cross - sectional view of a first exemplary structure after forming fin - shaped contact via cavities in a first - stage process according to an embodiment of the present disclosure.

[0026] Figure 18 is a vertical cross - sectional view of a first exemplary structure after conformally depositing a conformal dielectric material layer according to an embodiment of the present disclosure.

[0027] Figure 19 is a vertical cross - sectional view of a first exemplary structure after forming a vertical stack of annular insulating plates according to an embodiment of the present disclosure.

[0028] Figure 20 is a vertical cross - sectional view of a first exemplary structure after laterally expanding fin - shaped contact via cavities in a second - stage process to form fin - shaped contact via cavities in a third - stage process according to an embodiment of the present disclosure.

[0029] Figure 21 is a vertical cross - sectional view of a first exemplary structure after forming a sacrificial fin - cavity filling material structure according to an embodiment of the present disclosure.

[0030] Figure 22A is a vertical cross - sectional view of a first exemplary structure after forming a sacrificial contact - level dielectric layer and laterally isolating trenches according to an embodiment of the present disclosure.

[0031] Figure 22B is Figure 22A a top - view of the first exemplary structure. The hinged vertical plane A - A' is Figure 22A the plane of the vertical cross - sectional view of

[0032] Figure 23 is a vertical cross - sectional view of a first exemplary structure after forming a laterally extended cavity according to an embodiment of the present disclosure.

[0033] Figure 24 is a vertical cross - sectional view of a first exemplary structure after forming a dorsal blocking dielectric layer and a blocking dielectric liner, in accordance with an embodiment of the present disclosure.

[0034] Figure 25 is a vertical cross - sectional view of a first exemplary structure after forming a conductive layer, in accordance with an embodiment of the present disclosure.

[0035] Figure 26 is a vertical cross - sectional view of a first exemplary structure after forming a source region and an insulating spacer, in accordance with an embodiment of the present disclosure.

[0036] Figure 27 is a vertical cross - sectional view of a first exemplary structure after forming a source contact via structure, in accordance with an embodiment of the present disclosure.

[0037] Figure 28 is a vertical cross - sectional view of a first exemplary structure after removing a sacrificial fin cavity fill material structure, in accordance with an embodiment of the present disclosure.

[0038] Figure 29 is a vertical cross - sectional view of a first exemplary structure after expanding a fin contact via cavity, in accordance with an embodiment of the present disclosure.

[0039] Figure 30A is a vertical cross - sectional view of a first exemplary structure after forming a contact via structure, in accordance with an embodiment of the present disclosure.

[0040] Figure 30B is Figure 30A a top - view of a first exemplary structure. The articulated vertical plane A - A' is Figure 30A the plane of the vertical cross - sectional view of

[0041] Figure 31 is a top - view of a semiconductor die including a second exemplary structure in accordance with an embodiment of the present disclosure.

[0042] Figure 32 is a vertical cross - sectional view of a second exemplary structure after forming a three - layer structure including various alternating stacked, reverse - stepped dielectric material portions, a sacrificial memory opening fill structure up to an intermediate layer level, and a sacrificial contact opening fill structure up to an intermediate layer level, in accordance with an embodiment of the present disclosure.

[0043] Figure 33 is a vertical cross - sectional view of a second exemplary structure after forming an intermediate layer sacrificial contact opening fill structure, in accordance with an embodiment of the present disclosure.

[0044] Figure 34is a vertical cross - sectional view of a second exemplary structure after forming a memory opening filling structure according to an embodiment of the present disclosure.

[0045] Figure 35 is a vertical cross - sectional view of a second exemplary structure after forming a contact via cavity according to an embodiment of the present disclosure.

[0046] Figure 36 is a vertical cross - sectional view of a second exemplary structure after forming a lateral recess and an annular cavity surrounding the contact via cavity according to an embodiment of the present disclosure.

[0047] Figure 37 is a vertical cross - sectional view of a second exemplary structure after forming an annular insulating plate according to an embodiment of the present disclosure.

[0048] Figure 38 is a vertical cross - sectional view of a second exemplary structure after forming a sacrificial fin cavity filling material structure according to an embodiment of the present disclosure.

[0049] Figure 39 is a vertical cross - sectional view of a second exemplary structure after replacing a sacrificial material layer with a conductive layer according to an embodiment of the present disclosure.

[0050] Figure 40 is a vertical cross - sectional view of a second exemplary structure after forming a fin - shaped contact via cavity according to an embodiment of the present disclosure.

[0051] Figure 41 is a vertical cross - sectional view of a second exemplary structure after forming a layer - to - layer contact via structure according to an embodiment of the present disclosure.

[0052] Figure 42 is a composite view according to an embodiment of the present disclosure, the composite view including a schematic vertical cross - sectional view of a second exemplary structure and a schematic circuit diagram for electrically biasing various layers within the second exemplary structure.

[0053] Figure 43 is a composite view according to an embodiment of the present disclosure, the composite view including a schematic vertical cross - sectional view of an alternative embodiment of a second exemplary structure and a schematic circuit diagram for electrically biasing various layers within the alternative embodiment of the second exemplary structure. DETAILED DESCRIPTION

[0054] As discussed above, the present disclosure relates to three - dimensional memory devices including contacts to multiple stacked through - stack contact via structures and methods of manufacturing the same, and various aspects thereof are described below.

[0055] The accompanying drawings are not drawn to scale. Multiple instances of an element may be replicated in the case of a single instance of an illustrated element, unless otherwise explicitly described or clearly indicated that there is no replication of the element. Ordinal numbers such as "first", "second", and "third" are only used to identify similar elements, and different ordinal numbers may be used in the description and claims of the present disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0056] Like reference numerals represent like or similar elements. Unless otherwise specified, elements having the same reference numeral are considered to have the same composition and the same function. Unless otherwise specified, "contact" between elements means direct contact providing an edge or surface shared by the elements. If two or more elements do not directly contact each other or do not directly contact each other, these two elements are "separated" from each other or are "separated" from each other. As used herein, an element located "on" a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, an element is "directly" located "on" a second element if there is physical contact between the surface of the element and the surface of the second element. As used herein, an element is "electrically connected to" a second element if there is an electrical conduction path composed of at least one conductive material between the element and the second element. As used herein, a "prototype" structure or a "work-in-progress" structure refers to a transient structure whose shape or composition of at least one of its components is subsequently modified.

[0057] As used herein, a "layer" refers to a portion of a material including a region having a thickness. The layer may extend over the entire underlying or overlying structure, or its extent may be less than the extent of the underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top surface and the bottom surface of a continuous structure or at the top surface and the bottom surface. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above it, and / or below it.

[0058] Generally, a semiconductor die or a semiconductor package may include a memory chip. Each semiconductor package contains one or more dies (e.g., one, two, or four). A die is the smallest unit capable of independently executing commands or reporting status. Each die contains one or more planes (usually one or two). Although there are some limitations, the same and concurrent operations can be performed on each plane. Each plane contains multiple blocks, which are the smallest units that can be erased in a single erase operation. Each block contains multiple pages, which are the smallest programmable units, i.e., the smallest units on which a read operation can be performed.

[0059] Reference Figure 1 Figure 1 illustrates a first exemplary structure according to an embodiment of the present disclosure. The first exemplary structure includes a substrate 8 that includes a semiconductor material layer 9 at least in its upper portion. The semiconductor material layer 9 may include a single-crystalline semiconductor material layer or a polycrystalline semiconductor material layer. Below the semiconductor material layer, the substrate 8 may or may not include additional layers (such as a dielectric material layer embedding a metal interconnect structure) and / or semiconductor devices (such as peripheral circuits for controlling the operation of a three-dimensional memory array to be formed subsequently). In one embodiment, the substrate 8 may include a commercially available semiconductor wafer, such as a single-crystalline silicon wafer. The semiconductor material layer 9 may include an upper portion of the silicon wafer, doped wells in the silicon wafer, an epitaxial silicon layer on the silicon wafer, etc.

[0060] The first exemplary structure includes a memory array region 100 and a contact region 300. The memory array region 100 is a region where a three-dimensional memory array will be formed subsequently. The contact region 300 is a region where a layer contact via structure that contacts a conductive wire serving as a word line of the three-dimensional memory array will be formed subsequently. The contact region 300 may include a first contact region 301 and a second contact region 302. In the first contact region, a first contact via structure that provides an electrical connection to a first conductive layer is formed subsequently. In the second contact region, a second contact via structure that provides an electrical connection to a second conductive layer is formed subsequently. The memory array region 100 may be disposed adjacent to the contact region 300.

[0061] An optional dielectric isolation layer 6 may be formed in the upper portion of the substrate 8. The dielectric isolation layer 6 may include a silicon oxide layer that is located in the contact region 300 and may optionally extend into the memory array region 100.

[0062] A first alternating stack of a first insulating layer 132 and a first sacrificial material layer 142 may be formed over a substrate 8. The first insulating layer 132 includes an insulating material such as undoped silicate glass or doped silicate glass, and the first sacrificial material layer 142 includes a sacrificial material such as silicon nitride or a silicon-germanium alloy. The first alternating stack (132, 142) may include multiple repetitions of a unit layer stack that includes the first insulating layer 132 and the first sacrificial material layer 142. The total number of repetitions of the unit layer stack within the first alternating stack (132, 142) may be, for example, in the range of 8 to 1,024 (such as 32 to 256), but fewer and greater numbers of repetitions may also be employed. The thickness of each first insulating layer in the first insulating layer 132 may be in the range from 20 nm to 100 nm (such as from 30 nm to 60 nm), but smaller and greater thicknesses may also be employed. The thickness of each first sacrificial material layer in the first sacrificial material layer 142 may be in the range from 20 nm to 100 nm (such as from 30 nm to 60 nm), but smaller and greater thicknesses may also be employed.

[0063] A first stepped surface is formed in the first contact region 301. As used herein, a "stepped surface" refers to a set of surfaces that includes at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is adjacent to a first vertical surface that extends upward from a first edge of the horizontal surface and to a second vertical surface that extends downward from a second edge of the horizontal surface. A first stepped cavity is formed within a volume from which a portion of the first alternating stack (132, 142) has been removed by the formation of the first stepped surface. A "stepped cavity" refers to a cavity having a stepped surface.

[0064] The first stepped cavity may have various first stepped surfaces such that the horizontal cross-sectional shape of the first stepped cavity changes stepwise as a function of the vertical distance from the top surface of the substrate 8. In one embodiment, a first stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process and a second type of etching process, the first type of etching process vertically increasing the depth of the cavity by one or more levels, and the second type of etching process laterally expanding the region that is vertically etched in a subsequent first type of etching process. As used herein, a "tier" of a structure that includes multiple alternating ones is defined as the relative position of a pair of a first material layer and a second material layer within the structure.

[0065] Each first sacrificial material layer 142 within the first alternating stack (132, 142), except for the topmost first sacrificial material layer 142, extends further laterally than any overlying first sacrificial material layer 142 within the stepped region of the first alternating stack (132, 142). The first stepped surface of the first alternating stack (132, 142) extends continuously from the lowermost layer within the first alternating stack (132, 142) to the topmost layer within the first alternating stack (132, 142). Generally, the first stepped surface extends continuously from the lowermost layer within the first alternating stack (132, 142) to at least the topmost layer within the first alternating stack (132, 142).

[0066] Reference Figure 2 , the first insulating liner 152 and the first sacrificial liner 154 may be sequentially deposited over the first stepped surface. The first insulating liner 152 may be formed by a first conformal deposition process and may include an insulating material such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass. The thickness of the first insulating liner 152 may be in the range from 10 nm to 50 nm, such as from 15 nm to 30 nm, but smaller and larger thicknesses may also be employed. The first sacrificial liner 154 may be formed by a second conformal deposition process and may include a sacrificial material that can be subsequently selectively removed with respect to the material of the first insulating liner 152. In one embodiment, the first sacrificial liner 154 may include silicon nitride. The thickness of the first sacrificial liner 154 is greater than the thickness of the first sacrificial material layer 142 and may be in the range from 40 nm to 150 nm, such as from 60 nm to 100 nm, but smaller and larger thicknesses may also be employed.

[0067] Reference Figure 3 , a dielectric fill material, such as silicon oxide, may be deposited within the first stepped cavity. The excess portion of the deposited dielectric fill material may be removed, for example, by chemical mechanical planarization (CMP) above a horizontal plane including the top surface of the first sacrificial liner 154. A recess etching process may be performed to vertically recess the remaining portion of the dielectric fill material by a vertical recess distance equal to the thickness of the first sacrificial liner 154. Subsequently, an isotropic etching process may be performed to selectively remove the horizontally extending portions of the first sacrificial liner 154 with respect to the material of the first insulating liner 152. The remaining portion of the dielectric fill material filling the first stepped cavity constitutes the first stepped dielectric material portion 165. The first stepped dielectric material portion 165 may be reverse stepped.

[0068] As used herein, a "reverse step" element refers to an element having a first stepped surface and a horizontal cross-sectional area that monotonically increases as a function of the vertical distance from the top surface of the substrate on which the element is present. If silicon dioxide is used for the first stepped dielectric material portion 165, the silicon dioxide of the first stepped dielectric material portion 165 may or may not be doped with dopants such as B, P, and / or F. In one embodiment, the first stepped dielectric material portion 165 covers and contacts the first stepped surface and has a top surface coplanar with the top surface of the horizontal extension portion of the first insulating liner 152 that covers the first alternating stack (132, 142) in the memory array region 100.

[0069] Reference Figure 4 , a dielectric material layer may be formed over the first insulating liner 152 and the first stepped dielectric material portion 165. This dielectric material layer is referred to herein as the interlayer dielectric layer 180. The interlayer dielectric layer 180 includes a dielectric material (such as silicon oxide) and may have a thickness in the range from 50 nm to 200 nm (such as 80 nm to 160 nm), but smaller and larger thicknesses may also be employed.

[0070] A first photoresist layer (not shown) may be applied over the interlayer dielectric layer 180, and the first photoresist layer may be lithographically patterned to form an array of openings in the memory array region 100. An anisotropic etching process may be performed to transfer the pattern of the openings in the first photoresist layer through the interlayer dielectric layer 180, the first insulating liner 152, and the first alternating stack (132, 142) and optionally into the upper portion of the semiconductor material layer 9. The first layer of memory openings 149 may be formed through the interlayer dielectric layer 180, the first insulating liner 152, and the first alternating stack (132, 142). The overetch depth of the first layer of memory openings 149 into the semiconductor material layer 9 may be in the range from 0 nm to 50 nm, such as from 5 nm to 30 nm, but larger overetch depths may also be employed. The first photoresist layer may then be removed, for example, by ashing.

[0071] Reference Figure 5A and Figure 5B, a second photoresist layer (not shown) may be applied over the interlayer dielectric layer 180, and the second photoresist layer may be lithographically patterned to form an opening in the contact region 300. An anisotropic etching process may be performed to transfer the pattern of the opening in the second photoresist layer through the interlayer dielectric layer 180, the first sacrificial liner 154, the first insulating liner 152, the first stepped dielectric material portion 165, and the portion of the first alternating stack (132, 142) underlying the first stepped dielectric material portion 165, and optionally into the upper portion of the dielectric isolation layer 6 (if present) or the semiconductor material layer 9 (if layer 6 is omitted). The first layer contact opening 139 may be formed in the region where the layer contact via structure will subsequently be formed. The layer contact via structure is a contact via structure that will contact a subsequently formed conductive layer. The first layer support opening 119 may be formed in the region laterally surrounding the first layer contact opening 139. A support pillar structure is subsequently formed in the volume of the first layer support opening 119, and the support pillar structure serves as a structural support structure during the replacement of the first sacrificial material layer 142 with the first conductive layer. The second photoresist layer may then be removed, for example, by ashing. The first layer memory openings 149 may be arranged in rows extending along a first horizontal direction hd1, which may be the word line direction. The rows of the first layer memory openings 149 may be laterally spaced apart from each other along a second horizontal direction hd2, which may be perpendicular to the first horizontal direction hd1 and may be the bit line direction. The first layer contact openings 139 may be arranged in rows extending laterally along the first horizontal direction hd1.

[0072] Reference Figure 6 , an optional etch stop liner (not shown) and a first sacrificial fill material may be deposited in the first layer memory openings 149, the first layer support openings 119, and the first layer contact openings 139. The optional etch stop liner layer (if present) includes a thin silicon oxide layer having a thickness in the range of 1 nm to 6 nm. The first sacrificial fill material may include a carbon-based material (such as amorphous carbon or diamond-like carbon), a semiconductor material (such as amorphous silicon or polycrystalline silicon), a dielectric fill material (such as borosilicate glass or organosilicate glass), or a polymer material.

[0073] An executable recess etching process can be performed to remove portions of the first sacrificial fill material above a horizontal plane including the top surface of the interlayer dielectric layer 180. In one embodiment, each remaining portion of the first sacrificial fill material has a top surface within the horizontal plane including the top surface of the interlayer dielectric layer 180. The remaining portions of the first sacrificial fill material filling the first layer memory openings 149 constitute the first layer sacrificial memory opening fill structure 148. The remaining portions of the first sacrificial fill material filling the first layer support openings 119 constitute the first layer sacrificial support opening fill structure 118. The remaining portions of the first sacrificial fill material filling the first layer contact openings 139 constitute the first layer sacrificial contact opening fill structure 138.

[0074] Reference Figure 7 , a second alternating stack of a second insulating layer 232 and a second sacrificial material layer 242 can be formed over the first alternating stack (132, 142). The second insulating layer 232 includes an insulating material such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass, and the second sacrificial material layer 242 includes a sacrificial material such as silicon nitride. The second alternating stack (232, 242) can include multiple repetitions of a unit layer stack including the second insulating layer 232 and the second sacrificial material layer 242. The total number of repetitions of the unit layer stack within the second alternating stack (232, 242) can be, for example, in the range of 8 to 1,024 (such as 32 to 256), but fewer and more repetitions can also be employed. The thickness of each second insulating layer in the second insulating layer 232 can be in the range from 20 nm to 100 nm (such as from 30 nm to 60 nm), but smaller and larger thicknesses can also be employed. The thickness of each second sacrificial material layer in the second sacrificial material layer 242 can be in the range from 20 nm to 100 nm (such as from 30 nm to 60 nm), but smaller and larger thicknesses can also be employed. Although two alternating stacks are provided in this embodiment, in other embodiments, only one alternating stack or more than two alternating stacks (e.g., three or more alternating stacks) can be used.

[0075] A second stepped surface is formed in the second contact region 302. A second stepped cavity is formed within the volume from which portions of the second alternating stack (232, 242) are removed by the formation of the second stepped surface. The second stepped cavity can have various second stepped surfaces such that the horizontal cross-sectional shape of the second stepped cavity changes stepwise as a function of the vertical distance from the top surface of the substrate 8. In one embodiment, the second stepped cavity can be formed by repeatedly performing a set of processing steps. The set of processing steps can include, for example: an etching process of a second type that vertically increases the depth of the cavity by one or more levels, and an etching process of a second type that laterally expands the region to be vertically etched in a subsequent second type of etching process.

[0076] Each second sacrificial material layer 242 within the second alternating stack (232, 242), except for the topmost second sacrificial material layer 242, extends further laterally than any overlying second sacrificial material layer 242 within the stepped region of the second alternating stack (232, 242). The second stepped surface of the second alternating stack (232, 242) extends continuously from the lowermost layer within the second alternating stack (232, 242) to the topmost layer within the second alternating stack (232, 242). Generally, the second stepped surface extends continuously from the lowermost layer within the second alternating stack (232, 242) to at least the topmost layer within the second alternating stack (232, 242).

[0077] Reference Figure 8 , a second insulating liner 252 and a second sacrificial liner 254 may be sequentially deposited over the second stepped surface. The second insulating liner 252 may be formed by a conformal deposition process and may include an insulating material such as undoped silicate glass or doped silicate glass. The thickness of the second insulating liner 252 may be the same as the thickness of the first insulating liner 152. The second sacrificial liner 254 may be formed by a conformal deposition process and may include a sacrificial material that can be subsequently selectively removed with respect to the material of the second insulating liner 252. In one embodiment, the second sacrificial liner 254 may include silicon nitride. The thickness of the second sacrificial liner 254 is greater than the thickness of the second sacrificial material layer 242 and may be the same as the thickness of the first sacrificial liner 154.

[0078] A resist layer (not shown) may be applied over the second sacrificial liner 254 and may be lithographically patterned such that the photoresist layer covers the memory array region 100 and the second contact region 302 and does not cover the first contact region 301. A first etch process may be performed to remove the unmasked portion of the second sacrificial liner 254 in the first contact region 301. A second etch process may be performed to remove the unmasked portion of the second insulating liner 252 in the first contact region 301. Subsequently, the photoresist layer may be removed, for example, by ashing.

[0079] Reference Figure 9 , a dielectric fill material such as silicon oxide may be deposited in the second stepped cavity. The excess portion of the deposited dielectric fill material may be removed, for example, by chemical mechanical planarization (CMP) above a horizontal plane including the top surface of the second sacrificial liner 254. A recess etch process may be performed to vertically recess the remaining portion of the dielectric fill material by a vertical recess distance equal to the thickness of the second sacrificial liner 254. Subsequently, an isotropic etch process may be performed to selectively remove the horizontally extending portion of the second sacrificial liner 254 with respect to the material of the second insulating liner 252. The remaining portion of the dielectric fill material filling the second stepped cavity constitutes the second stepped dielectric material portion 265.

[0080] If silicon dioxide is used for the second-level dielectric material portion 265, the silicon dioxide of the second-level dielectric material portion 265 may or may not be doped with dopants such as B, P, and / or F. In one embodiment, the second-level dielectric material portion 265 covers and contacts the second-level surface and has a top surface coplanar with the top surface of the horizontal extension portion of the second insulating liner 252, and the horizontal extension portion covers the second alternating stack (232, 242) in the memory array region 100.

[0081] An insulating cap layer 270 may be formed over the second insulating liner 252 and the second-level dielectric material portion 265. The insulating cap layer 270 includes a dielectric material (such as silicon oxide) and may have a thickness in the range from 50 nm to 200 nm (such as 80 nm to 260 nm), but smaller and larger thicknesses may also be employed.

[0082] Reference Figure 10 , a photoresist layer (not shown) may be applied over the insulating cap layer 270, and the photoresist layer may be lithographically patterned to form openings over the regions of the first-level sacrificial contact opening fill structure 138 and the first-level sacrificial support opening fill structure 118. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the insulating cap layer 270, the second-level dielectric material portion 265, the second sacrificial liner 254, the second insulating liner 252, and the portion of the second alternating stack (232, 242) underlying the second-level dielectric material portion 265. Subsequently, the sacrificial fill materials of the first-level sacrificial contact opening fill structure 138 and the first-level sacrificial support opening fill structure 118 may be selectively removed for the materials of the insulating cap layer, the first alternating stack (132, 232), the second alternating stack (232, 242), the interlayer dielectric layer 180, and the dielectric isolation layer 6. For example, a selective etching process or an ashing process (for carbon sacrificial materials) may be performed to remove the sacrificial fill materials of the first-level sacrificial contact opening fill structure 138 and the first-level sacrificial support opening fill structure 118.

[0083] The multi-layer contact opening 39 (also referred to as contact opening 39) can be formed in the volume from which the first layer of sacrificial contact opening fill structure 138 has been removed, and in the volume overlying the volume of the first layer of sacrificial contact opening fill structure 138 and extending vertically through the second alternating stack (232, 242) and / or the second stepped dielectric material portion 265 and through the insulating capping layer 270. The multi-layer support opening 19 (also referred to as support opening 39) can be formed in the volume from which the first layer of sacrificial support opening fill structure 118 has been removed, and in the volume overlying the volume of the first layer of sacrificial support opening fill structure and extending vertically through the second alternating stack (232, 242) and / or the second stepped dielectric material portion 265 and through the insulating capping layer 270. Subsequently, the photoresist layer can be removed, for example, by ashing.

[0084] Reference Figure 11 , an optional etch stop liner (not shown) and a second sacrificial fill material can be deposited in the multi-layer support opening 19 and the multi-layer contact opening 39. The optional etch stop liner (if present) includes a thin silicon oxide layer having a thickness in the range of 2 nm to 6 nm. The second sacrificial fill material can include a carbon-based material (such as amorphous carbon or diamond-like carbon), a semiconductor material (such as amorphous silicon or polysilicon), a dielectric fill material (such as borosilicate glass or organosilicate glass), or a polymeric material.

[0085] A recess etch process can be performed to remove portions of the second sacrificial fill material from above a horizontal plane including the top surface of the insulating capping layer 270. In one embodiment, each remaining portion of the second sacrificial fill material has a top surface in the horizontal plane including the top surface of the insulating capping layer 270. The remaining portions of the second sacrificial fill material filling the multi-layer support opening 19 constitute the sacrificial support opening fill structure 18. The remaining portions of the second sacrificial fill material filling the multi-layer contact opening 39 constitute the sacrificial contact opening fill structure 38. A covering insulating layer 270A is formed over the insulating capping layer 270, the sacrificial support opening fill structure 18, and the sacrificial contact opening fill structure 38. The covering insulating layer 270A can include silicon oxide and is incorporated into the insulating capping layer 270.

[0086] Reference Figure 12, a photoresist layer (not shown) can be applied over the insulating capping layer 270, and the photoresist layer can be lithographically patterned to form an opening in the area overlying the sacrificial support opening fill structure 18. The sacrificial support opening fill structure 18 can be selectively removed with respect to the materials of the insulating capping layer 270, the alternating stack {(132, 142), (232, 242)}, the interlayer dielectric layer 180, and the dielectric isolation layer 6. An anisotropic etching process, an isotropic etching process, or an ashing process can be employed. Subsequently, the photoresist layer can be removed, for example, by ashing. The cavity formed by removing the sacrificial support opening fill structure 18 includes a plurality of support openings 19, which are referred to as subsequent process support openings.

[0087] Reference Figure 13 , at least one dielectric spacer layer (272, 273) can be optionally formed in the support openings 19 and over the insulating capping layer 270. The at least one dielectric spacer layer (272, 273) can include an outer dielectric spacer layer 272 and an optional inner dielectric spacer layer 273. In an illustrative example, the outer dielectric spacer layer 272 can include a silicon nitride layer, which is converted into a silicon oxide or silicon oxynitride layer by plasma oxidation. The inner dielectric spacer layer 273 can include a deposited silicon oxide layer. Alternatively, the inner dielectric spacer layer 273 can be omitted. The at least one dielectric spacer layer (272, 273) prevents the silicon nitride layer subsequently formed in the plurality of support openings 19 from being exposed to the subsequently formed lateral isolation trenches and thus prevents it from being removed together with other silicon nitride sacrificial material layers (142, 242) during the replacement of the sacrificial material layer with a conductive layer.

[0088] Reference Figure 14 , a photoresist layer (not shown) can be applied over the dielectric spacer layer (272, 273), and the photoresist layer can be lithographically patterned to form an opening in the area of the first layer sacrificial memory opening fill structure 148. An anisotropic etching process can be performed to form an opening through the dielectric spacer layer (272, 273), the insulating capping layer 270, and the second alternating stack (232, 242) below the opening in the photoresist layer and above the first layer sacrificial memory opening fill structure 148. Subsequently, the first layer sacrificial memory opening fill structure 148 can be selectively removed with respect to the materials of the dielectric spacer layer (272, 273), the insulating capping layer 270, the alternating stack {(132, 142), (232, 242)}, and the interlayer dielectric layer 180. A plurality of memory openings 49 (also referred to as memory openings 49) are formed in the volume from which the first layer sacrificial memory opening fill structure 148 has been removed and in the volume of the cavity overlying the volume from which the first layer sacrificial memory opening fill structure 148 has been removed. Subsequently, the photoresist layer can be removed, for example, by ashing.

[0089] ReferenceFigure 15 A series of processing steps can be performed to form a memory opening fill structure 58 within each multi-layer memory opening 49 and simultaneously form a support pillar structure 20 within each multi-layer support opening 19. For example, a memory film 50 can be formed within each of the memory opening 49 and the support opening 19. The memory film 50 can include any memory material capable of storing information through charge trapping, change in resistivity, change in ferroelectric polarization direction (e.g., in a ferroelectric material), or any other material in which information can be stored. For example, each memory film 50 can include a layer stack that includes a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56. In one embodiment, the memory film 50 can be formed by depositing a layer and / or a portion of material and, for example, removing the excess portions of the layer and / or the portion of material from the exterior and the bottom of the memory opening 49 and the support opening 19 by performing an anisotropic etching process (e.g., a sidewall spacer etching process). In one embodiment, the blocking dielectric layer 52 can include a silicon oxide or an aluminum oxide layer. The charge storage layer 54 can include a silicon nitride layer. The tunneling dielectric layer 56 can include a silicon oxide layer or an "ONO" stack of a silicon oxide / silicon nitride / silicon oxide layer.

[0090] A vertical semiconductor channel 60 can be formed within each of the memory opening 49 and the support opening 19 by conformally depositing a doped semiconductor channel material of a first conduction type, such as amorphous silicon or polysilicon. The semiconductor channel material can be doped with the same conduction type as the horizontal semiconductor channel (not explicitly shown) located in the substrate 8. A dielectric fill material can be deposited in the remaining volume of the memory opening 49 and the support opening 19, and the dielectric fill material can be vertically recessed to form a dielectric core 62. A semiconductor material of a second conduction type, such as amorphous silicon or polysilicon, doped with a second conduction type, can be deposited on top of each dielectric core 62 at the top end of each vertical semiconductor channel 60 to form a drain region 63 within each of the memory opening 49 and the support opening 19. The second conduction type is opposite to the first conduction type. Each adjacent combination of the memory film 50 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. Each memory stack structure 55 includes a corresponding vertical stack of memory elements. For example, each vertical stack of memory elements can include portions of the charge storage layer 54 located at the levels of the sacrificial material layers (142, 242), which are subsequently replaced by conductive layers.

[0091] Typically, a memory opening fill structure 58 is formed in the memory opening 49, and a support pillar structure 20 is formed in the support opening 19. Each memory opening fill structure in the memory opening fill structure 58 includes a corresponding vertical semiconductor channel 60, a corresponding vertical stack of memory elements (e.g., a portion of the memory film 50), a drain region 63, and an optional dielectric core 62. Each support pillar structure in the support pillar structure 20 includes a dummy vertical semiconductor channel (which is not electrically connected to the bit line), a dummy memory film, a dummy drain region, and an optional dielectric core, which include the same materials as those of the memory opening fill structure 58. In one embodiment, each support pillar structure in the support pillar structure 20 further includes at least one dielectric spacer layer (272, 273) surrounding the dummy memory film, while the memory opening fill structure 58 lacks at least one dielectric spacer layer (272, 273). In an alternative embodiment, the support pillar structure may be formed separately from the memory opening fill structure 58 (i.e., before or after it). In an alternative embodiment, the support pillar structure 20 may contain only insulating materials, such as silicon oxide. The drain select level dielectric isolation structure 72 may be formed through the uppermost assembly of the second sacrificial material layer 242.

[0092] Reference Figure 16A and Figure 16B, a contact-level dielectric layer 280 may be formed, optionally, over the dielectric spacer layers (272, 273). A photoresist layer may be applied over the contact-level dielectric layer 280, and the photoresist layer may be lithographically patterned to form an opening in a region overlying the sacrificial contact opening fill structure 38. An anisotropic etching process may be performed to transfer the pattern of the opening in the photoresist layer through the contact-level dielectric layer 280 and the dielectric spacer layers (272, 273). A cavity may be formed over each sacrificial contact opening fill structure 38 through the contact-level dielectric layer 280 and the dielectric spacer layers (272, 273). The sacrificial contact opening fill structures 38 may then be selectively removed for the materials of the contact-level dielectric layer 280, the dielectric spacer layers (272, 273), the insulating capping layer 270, the alternating stacks {(132, 142), (232, 242)}, the interlayer dielectric layer 180, and the optional dielectric isolation layer 6 (if present). Contact vias cavities 81 are formed in the volume from which the sacrificial contact opening fill structures 38 have been removed and in the volume of the cavities overlying the volume from which the sacrificial contact opening fill structures 38 have been removed. The photoresist layer may then be removed, for example, by ashing. The contact vias cavities 81 include: a first contact vias cavity 81A formed in the first contact region 301 and extending through the first stepped dielectric material portion 165 and the first alternating stack (132, 142); and a second contact vias cavity 81B formed in the second contact region 302 and extending through the second stepped dielectric material portion 265, the first alternating stack (132, 142), and the second alternating stack (232, 242).

[0093] Reference Figure 17 , a first isotropic etching process may be performed to isotropically recess the materials of the sacrificial material layers (142, 242), the first sacrificial liner 154, and the second sacrificial liner 254 selectively for the materials of the contact-level dielectric layer 280, the dielectric spacer layers (272, 273), the insulating capping layer 270, the insulating layers (132, 232), the interlayer dielectric layer 180, and the dielectric isolation layer 6 (if present). For example, if the sacrificial material layers (142, 242), the first sacrificial liner 154, and the second sacrificial liner 254 include silicon nitride, a wet etching process using hot phosphoric acid may be performed to laterally recess the sacrificial material layers (142, 242).

[0094] Typically, the sidewalls of the sacrificial material layers (142, 242), the first sacrificial liner 154, and the second sacrificial liner 254 can be laterally recessed relative to the sidewalls of the insulating layers (132, 232) and the stepped dielectric material portions (165, 265) around the contact via cavities 81. A lateral recess 41 is formed in the volume where the material of the sacrificial material layers (142, 242) has been removed. The lateral recess 41 can have a width of 50 nm to 250 nm (such as 100 nm to 150 nm), and can be arranged to obtain a desired electric field between the word line and the layer contact via structure to be formed in subsequent steps, as will be described below. A first annular cavity 155 can be formed in each volume where the annular portion of the first sacrificial liner 154 has been removed around a corresponding one of the first contact via cavities 81A. A second annular cavity 255 can be formed in each volume where the annular portion of the second sacrificial liner 254 has been removed around a corresponding one of the second contact via cavities 81B.

[0095] Typically, a first isotropic etching process etches the proximal portions of the first sacrificial liner 154 and the first sacrificial material layer 142 around each first contact via cavity 81A to form corresponding fin-shaped cavities, which are referred to herein as fin-shaped contact via cavities 82A in the first first-stage process. In addition, the first isotropic etching process etches the proximal portions of the second sacrificial liner 154, the first sacrificial material layer 142, and the second sacrificial material layer 242 around each second contact via cavity 81B to form corresponding fin-shaped cavities, which are referred to herein as fin-shaped contact via cavities 82B in the second first-stage process. The fin-shaped contact via cavities 82A in the first first-stage process and the fin-shaped contact via cavities 82A in the second first-stage process include the fin-shaped contact via cavities 82 in the first-stage process.

[0096] Each fin-shaped contact via cavity 82A in the first first-stage process includes a cylindrical cavity, a first annular cavity 155, and at least one lateral recess 41 formed by removing the annular portion of the corresponding first sacrificial material layer 142, where the cylindrical cavity includes the volume of the corresponding first contact via cavity 82A. Each fin-shaped contact via cavity 82B in the second first-stage process includes a cylindrical cavity, a second annular cavity 255, and a lateral recess 41 formed by removing the first sacrificial material layer 142 and the annular portion of at least one second sacrificial material layer 242, where the cylindrical cavity includes the volume of the corresponding second contact via cavity 82B.

[0097] The physically exposed recessed surfaces of the sacrificial material layers (142, 242), the first sacrificial liner 154, and the second sacrificial liner 254 after the first isotropic etching process include sidewall segments that are laterally offset from the sidewalls of the insulating layers (132, 232) and the stepped dielectric material portions (165, 265) around the cylindrical cavity of the fin contact via cavity 82 in the respective first stage process by a uniform lateral offset distance. The uniform lateral offset distance can be the same as the etching distance of the first isotropic etching process.

[0098] Reference Figure 18 , a conformal dielectric material layer 40L can be deposited in the fin contact via cavity 82 in the first stage process by a conformal deposition process (such as a low-pressure chemical vapor deposition process or an atomic layer deposition process). The conformal dielectric material layer 40L can be conformally deposited to completely fill the volume of the lateral recess 41, without completely filling the volume of the first annular cavity 155 or the second annular cavity 255. The conformal dielectric material layer 40L includes a material different from the material of the sacrificial material layers (142, 242). For example, the conformal dielectric material layer 40L includes silicon oxide.

[0099] As discussed above, the first sacrificial liner 154 and the second sacrificial liner 254 have a thickness greater than the thickness of the sacrificial material layers (142, 242). Therefore, the first annular cavity 155 or the second annular cavity 255 has a height greater than the height of the lateral recess 41. The thickness of the conformal dielectric material layer 40L can be greater than half of the height of the lateral recess 41 and can be less than half of the height of the first annular cavity 155 or the second annular cavity 255. Therefore, the volume of the first annular cavity 155 or the second annular cavity 255 can be partially filled with the conformal dielectric material layer 40L, and there is still an unfilled volume within each of the first annular cavity 155 or the second annular cavity 255.

[0100] Reference Figure 19 , an isotropic recess etching process can be performed to isotropically recess the conformal dielectric material layer 40L. For example, if the conformal dielectric material layer 40L includes silicon oxide, a wet etching process using dilute hydrofluoric acid can be performed to isotropically recess the conformal dielectric material layer 40L around the cavities passing through the alternating stacks {(132, 142), (232, 242)}. The duration of the isotropic etching process can be selected such that the isotropic recess etching process completely removes the material of the conformal dielectric material layer 40L from the interior of each of the first annular cavity 155 and the second annular cavity 255. The remaining portion of the conformal dielectric material layer 40L that fills the lateral recess 41 (i.e., the volume from which the sacrificial material layers (142, 242) have been removed) constitutes an annular insulating plate 40 (e.g., an insulating fin).

[0101] The remaining volume of the fin contact via cavity 82 in the first stage process is referred to herein as the fin contact via cavity 83 in the second stage process. The fin contact via cavity 83 in the second stage process may include a first fin contact via cavity 83A in the second stage process that extends through a portion of the first stepped dielectric material portion 165 and the first alternating stack (132, 142), and a second fin contact via cavity 83B in the second stage process that extends through a portion of the second stepped dielectric material portion 265 and the second alternating stack (232, 242). Each fin contact via cavity 83 in the second stage process includes a cylindrical cavity portion 83C and an annular cavity portion 83F. The cylindrical cavity portion has a cylindrical shape and extends vertically from the top surface of the contact level dielectric layer 280 to the dielectric isolation layer 6 (if present, or alternatively to the substrate 8). The annular cavity portion abuts and laterally surrounds the cylindrical cavity portion 83C. Each annular cavity portion 83F may be defined by the annular bottom surface of the stepped dielectric material portions (165, 265), the cylindrical sidewalls of the sacrificial pads (154, 254), and the annular top surface segments of the insulating pads (152, 252).

[0102] At least one annular insulating plate 40 may be present around each fin contact via cavity 83 in the second stage process. Each of the plurality of first fin contact via cavities 83A in the second stage process and the second fin contact via cavities 83B in the second stage process may be laterally surrounded by a corresponding vertical stack of annular insulating plates 40. The first fin contact via cavity 83A in the second stage process may include a first cylindrical surface and a second cylindrical surface. The first cylindrical surface extends vertically through the first stepped dielectric material portion 165 and the second stepped dielectric material portion 265 and has a bottom perimeter that abuts the inner perimeter of the annular top surface of the annular cavity portion 83F. The second cylindrical surface extends vertically through a subset of the layers within the first alternating stack (132, 142) and has a top perimeter that abuts the annular bottom surface of the annular cavity portion 83F. The second fin contact via cavity 83B in the second stage process may include a first cylindrical surface and a second cylindrical surface. The first cylindrical surface extends vertically through the second stepped dielectric material portion 265 and has a bottom perimeter that abuts the inner perimeter of the annular top surface of the annular cavity portion 83F. The second cylindrical surface extends vertically through a subset of the layers within the second alternating stack (232, 242) and each layer within the first alternating stack (132, 142) and has a top perimeter that abuts the annular bottom surface of the annular cavity portion 83F. Generally, each fin contact via cavity 83 in the second stage process includes the entire volume of the corresponding contact via cavity 81 and the volume formed by removing a portion of the sacrificial pads (154, 254) during the first isotropic etch process.

[0103] Reference Figure 20, a second isotropic etching process can be performed to isotropically and selectively recess the material of the sacrificial liners (154, 254) with respect to the materials of the contact-level dielectric layer 280, the dielectric spacer layers (272, 273), the insulating cap layer 270, the insulating layers (132, 232), the interlayer dielectric layer 180, the dielectric isolation layer 6 (if present), and the annular insulating plate 40. For example, if the sacrificial liners (154, 254) include silicon nitride, a wet etching process using hot phosphoric acid can be performed to isotropically recess the sacrificial liners (154, 254). The volume of each annular cavity portion 83F can be laterally expanded by the second isotropic etching process. The fin contact via cavity 83 in the second stage process expanded by the second isotropic etching process is referred to herein as the fin contact via cavity 85 in the third stage process.

[0104] Generally, the fin contact via cavity 85 in the third stage process can be formed by laterally recessing the sidewalls of the sacrificial liners (154, 254) surrounding the fin contact via cavity 83 in the second stage process by performing a second isotropic etching process. The lateral recessing distance of the second isotropic etching process can be in the range from 20 nm to 300 nm, such as from 40 nm to 150 nm, but smaller and larger lateral etching distances can also be employed. The fin contact via cavity 85 in the third stage process includes a first fin contact via cavity 85A formed in the first contact region 301 and a second fin contact via cavity 85B formed in the second contact region 302. Each of the fin contact via cavities 85 in the third stage process includes a cylindrical cavity portion 85C and an annular cavity portion 85F. In one embodiment, each annular cavity portion 85F can have: a stepped top surface that includes a first annular top surface section that is an annular bottom surface section of the stepped dielectric material portion (165, 265); a cylindrical surface section adjacent to the outer perimeter of the first annular top surface section; and a second annular top surface section that is another annular bottom surface section of the stepped dielectric material portion (165, 265).

[0105] Reference Figure 21 , a sacrificial fill material can be deposited in the fin contact via cavity 85 in the third stage process. The sacrificial fill material can include a semiconductor material (such as amorphous silicon or polysilicon), a carbon-based material (such as amorphous carbon or diamond-like carbon), a dielectric fill material (such as borosilicate glass or organosilicate glass), or a polymer material. Optionally, a thin etch stop liner (not shown) can be deposited before filling the fin contact via cavity 85 in the third stage process with the sacrificial fill material. The thin etch stop liner can include silicon oxide or a dielectric metal oxide and can have a thickness in the range from 2 nm to 6 nm, but smaller and larger thicknesses can also be employed.

[0106] Portions of the sacrificial fill material that overlie a horizontal plane including the top surface of the contact-level dielectric layer 280 can be removed by a planarization process, which can include a recess etch process or a chemical mechanical polishing process. Each remaining portion of the corresponding one of the fin contact vias 85 in the third stage fill process of the sacrificial fill material constitutes a sacrificial fin cavity fill material structure 84. Each sacrificial fin cavity fill material structure 84 includes a corresponding cylindrical fill material portion 84C and at least one fin-shaped fill material portion 84F. Each fin-shaped fill material portion 84F has a corresponding annular shape.

[0107] Reference Figure 22A and Figure 22B , a sacrificial contact-level dielectric layer 282 can be formed over the contact-level dielectric layer 280. The sacrificial contact-level dielectric layer 282 includes a dielectric material such as undoped silicate glass or doped silicate glass and can have a thickness in the range from 10 nm to 200 nm, such as from 20 nm to 100 nm, but smaller and larger thicknesses can also be employed.

[0108] A photoresist layer (not shown) can be applied over the sacrificial contact-level dielectric layer 282, and the photoresist layer can be lithographically patterned to form openings in a region extending across the memory array region 100 and the contact region 300. The openings in the photoresist layer can extend laterally between each adjacent cluster of the memory opening fill structures 58 along a first horizontal direction hd1. The lateral isolation trenches 79 can be formed by transferring the pattern in the photoresist layer through the sacrificial contact-level dielectric layer 282, the contact-level dielectric layer 280, the second alternating stack (232, 242) and the first alternating stack (132, 142), the stepped dielectric material portions (165, 265) and into the substrate 8. Portions of the sacrificial contact-level dielectric layer 282, the contact-level dielectric layer 280, the second alternating stack (232, 242) and the first alternating stack (132, 142), the stepped dielectric material portions (165, 265) underlying the openings in the photoresist layer can be removed to form the lateral isolation trenches 79. In one embodiment, the lateral isolation trenches 79 can be formed between clusters (e.g., blocks) of the memory opening fill structures 58. The clusters of the memory opening fill structures 58 can be laterally spaced apart by the lateral isolation trenches 79 along a second horizontal direction hd2. In one embodiment, the lateral isolation trenches 79 form the sidewalls of the memory blocks.

[0109] Reference Figure 23, an etchant for selectively etching the materials of the first and second sacrificial material layers (142, 242), the first sacrificial liner 154, and the second sacrificial liner 254, which can be, for example, the material of the outermost layer of the memory film 50 of the memory opening filling structure 58, the material of at least one dielectric spacer layer (272, 273) of the support pillar structure 20, and the materials of the first and second insulating layers (132, 232), can be introduced into the lateral isolation trench 79. The first laterally extending cavity 143 is formed in the volume from which the first sacrificial material layer 142 has been removed. The second laterally extending cavity 143 is formed in the volume from which the second sacrificial material layer 242 has been removed. The first stepped cavity 153 is formed in the volume from which the first sacrificial liner 154 has been removed. The second stepped cavity 253 is formed in the volume from which the second sacrificial liner 254 has been removed.

[0110] The isotropic etching process can be a wet etching process using a wet etching solution, or can be a gas-phase (dry) etching process in which the etchant is introduced into the lateral isolation trench 79 in a gas phase. For example, if the first and second sacrificial material layers (142, 242), the first sacrificial liner 154, and the second sacrificial liner 254 include silicon nitride, the etching process can be a wet etching process of immersing the first exemplary structure in a wet etching tank including phosphoric acid, which selectively etches silicon nitride with respect to silicon oxide and silicon.

[0111] The annular insulating plate 40 and the sacrificial fin cavity filling material structure 84 extend vertically from the dielectric isolation layer 6 (if present, or from the substrate 8) to the contact-level dielectric layer 280, and provide structural support for the portions of the insulating layers (132, 232) and the stepped dielectric material portions (165, 265) present in the contact region 300 after the removal of the sacrificial material layers. The annular insulating plate 40 can enhance the structural support for the insulating layers (132, 232) and the stepped dielectric material portions (165, 265). The memory opening filling structure 58 provides structural support for the insulating layers (132, 232) in the memory array region 100.

[0112] Each of the first laterally extending cavity and the second laterally extending cavity (143, 243) may be a laterally extending cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the first laterally extending cavity and the second laterally extending cavity (143, 243) may be greater than the height of the corresponding laterally extending cavity. A plurality of first laterally extending cavities may be formed in the volume of material from which the first sacrificial material layer 142 has been removed. A plurality of second laterally extending cavities may be formed in the volume of material from which the second sacrificial material layer 242 has been removed. Each of the first laterally extending cavity and the second laterally extending cavity may extend substantially parallel to the top surface of the substrate 8. The laterally extending cavities (143, 243) may be vertically defined by the top surface of the underlying insulating layer (132 or 232) and the bottom surface of the overlying insulating layer (132 or 232). In one embodiment, each of the first laterally extending cavity and the second laterally extending cavity (143, 243) may always have a uniform height.

[0113] The first stepped cavity 153 may be formed above the first stepped surface and the first insulating pad 152. As discussed above, the first sacrificial pad 154 may be formed by a conformal deposition process and has a uniform thickness greater than the thickness of each first sacrificial material layer 142.

[0114] Thus, after removing the first sacrificial pad 154, each horizontal extending portion of the first stepped cavity 153 has a uniform height that is the same as the uniform width of each vertical extending portion of the first stepped cavity 153. Each horizontal extending portion of the second stepped cavity 253 has a uniform height that is the same as the uniform width of each vertical extending portion of the second stepped cavity 253. The uniform width and the uniform height of the first stepped cavity 153 and the second stepped cavity 253 are greater than the thickness of the sacrificial material layers (142, 242).

[0115] Reference Figure 24 , an optional blocking dielectric material (i.e., a dielectric material that can be used to block electron tunneling) may be conformally deposited in the laterally extending cavities (143, 243), the first stepped cavity 153, and the second stepped cavity 253. In one embodiment, the blocking dielectric material includes a dielectric metal oxide material such as alumina, hafnium oxide, tantalum oxide, titanium oxide, yttrium oxide, etc. Alternatively or additionally, the blocking dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, and / or silicon carbonitride. The thickness of the blocking dielectric material may be in the range of 2 nm to 20 nm, such as 6 nm to 12 nm, but smaller and larger thicknesses may also be employed.

[0116] A dorsal blocking dielectric layer 44 can be formed within each of the laterally extending cavities (143, 243). A blocking dielectric liner 144 can be formed in each of the first stepped cavity 153 and the second stepped cavity 253. Each outer sidewall of the annular insulating plate 40 can be in contact with the dorsal blocking dielectric layer 44. Each fin-shaped filler material portion 84F of the sacrificial fin cavity filler material structure 84 can be in contact with a corresponding blocking dielectric liner 144. The first blocking dielectric liner 144 formed within the first stepped cavity 153 can be in contact with each of the first sacrificial fin cavity filler material structures 84A. The second blocking dielectric liner 144 formed within the second stepped cavity 253 can be in contact with each of the second sacrificial fin cavity filler material structures of the second sacrificial fin cavity filler material structure 84B.

[0117] Reference Figure 25 , at least one conductive material can be conformally deposited in the plurality of laterally extending cavities (143, 243), in the stepped cavities (153, 253), on the sidewalls of the lateral isolation trenches 79, and above the contact level dielectric layer 280. The at least one conductive material can include at least one metallic material, that is, a conductive material including at least one metallic element.

[0118] The at least one metallic material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, and / or a combination thereof. The at least one metallic material can be elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal semiconductor alloy (such as a metal silicide), an alloy thereof, and a combination or stack thereof. Non-limiting exemplary metallic materials that can be deposited in the laterally extending cavities include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and / or ruthenium. In one embodiment, the at least one metallic material can include a combination of a metal barrier liner material and a metal filler material. The metal barrier liner material can include titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, or a combination thereof. The metal filler material can include titanium, tantalum, tungsten, cobalt, molybdenum, ruthenium, copper, etc. In one embodiment, the at least one metallic material can be deposited by chemical vapor deposition or atomic layer deposition.

[0119] According to one aspect of the present disclosure, the total thickness of the at least one conformally deposited conductive material can be greater than half of the height of the laterally extending cavity (143, 243) and less than half of the height of the horizontally extending portion of the stepped cavity (153, 253) (the height of the horizontally extending portion being the same as the width of the vertically extending portion of the stepped cavity (153, 253)). Thus, each of the laterally extending cavities (143, 243) can be completely filled with the at least one conformally deposited conductive material, while the stepped cavity (153, 253) is only partially filled and contains unfilled voids.

[0120] The at least one conformally deposited conductive material can be isotropically etched back from inside the stepped cavity (153, 253), from the sidewalls of the lateral isolation trench 79, and from above the sacrificial contact layer dielectric 282. The etch distance of the isotropic etch-back process can be the same as or greater than the total thickness of the at least one deposited conductive material. Each remaining portion of the deposited metallic material in the first laterally extending cavity constitutes the conductive layer 146. Each remaining portion of the deposited metallic material in the second laterally extending cavity constitutes the second conductive layer 246. Each conductive layer (146, 246) can be a conductive line structure, which can be a word line or a select gate electrode. The at least one conductive material can be completely removed from inside the stepped cavity (153, 253), and the blocking dielectric liner 144 can be physically exposed around each stepped cavity (153, 253).

[0121] A plurality of conductive layers 146 can be formed in the plurality of first laterally extending cavities 143, and a plurality of second conductive layers 246 can be formed in the plurality of second laterally extending cavities 243. Thus, the first sacrificial material layer and the second sacrificial material layer (142, 242) can be replaced with the first conductive material layer and the second conductive material layer (146, 246), respectively. Specifically, each first sacrificial material layer 142 can be replaced with the backside blocking dielectric layer 44 and the first conductive layer 146, and each second sacrificial material layer 242 can be replaced with the backside blocking dielectric layer 44 and the second conductive layer 246. Backside cavities exist in the portions of each lateral isolation trench 79 that are not filled with a continuous metallic material layer.

[0122] Each memory opening fill structure 58 (which includes a corresponding memory stack structure 55) in the memory opening fill structure includes a vertical stack of memory elements at each level of the conductive layer (146, 246). A subset of the intermediate conductive layers (146, 246) can include word lines for the memory elements. At least one uppermost conductive layer 246 can include a drain-side select gate electrode. At least one lowermost conductive layer 146 can include a source-side select gate electrode.

[0123] The dorsal blocking dielectric layer 44 may be interposed between each adjacent pair of the first conductive layer 146 and the first insulating layer 132 within the first alternating stack (132, 146), and may be interposed between each adjacent pair of the second conductive layer 246 and the second insulating layer 232. In one embodiment, a subset of the dorsal blocking dielectric layer 44 is embedded in a corresponding layer of the first conductive layer 146 and is interposed between a corresponding layer of the first conductive layer 146 and a corresponding layer of the first insulating layer 132. A subset of the dorsal blocking dielectric layer 44 is embedded in a corresponding layer of the first conductive layer 246 and is interposed between a corresponding layer of the first conductive layer 246 and a corresponding layer of the first insulating layer 232. In one embodiment, each annular insulating plate 40 may contact a sidewall of a corresponding layer of the dorsal blocking dielectric layer 44. Each fin-shaped filler material portion 84F of the sacrificial fin cavity filler material structure 84 may contact a sidewall of a corresponding blocking dielectric liner 144. The blocking dielectric liner 144 and the dorsal blocking dielectric layer 44 may have the same material composition and the same thickness. The first alternating stack of the first insulating layer 132 and the first conductive layer 146 may be formed below the interlayer dielectric layer 180, and the second alternating stack of the second insulating layer 232 and the second conductive layer 246 may be formed above the interlayer dielectric layer 180.

[0124] Reference Figure 26 , dopants of the second conductivity type may optionally be implanted into the surface portion of the semiconductor material layer 9 underlying the lateral isolation trench 79 to form the source region 61. The source region 61 may include dopants of the second conductivity type having an atomic concentration in the range of 5.0×10 18 / cm 3 to 2.0×10 21 / cm 3 . Alternatively, the formation of the source region 61 may be omitted at this time, and instead, a top source contact may be formed above the bottom tip of the vertical semiconductor channel after the substrate 8 is removed.

[0125] The dielectric filler material may be conformally deposited in the staircase-shaped cavities (153, 253) and in the peripheral portions of the lateral isolation trenches 79 by a conformal deposition process. The dielectric filler material may include silicon oxide or silicon nitride. The thickness of the deposited dielectric filler material may be greater than half of the height of the horizontal extension portion of the staircase-shaped cavities (153, 253), such that the staircase-shaped cavities (153, 253) are filled within the dielectric filler material. The portion of the dielectric filler material that fills the first staircase-shaped cavity 153 constitutes the first dielectric filler material layer 174. The portion of the dielectric filler material that fills the second staircase-shaped cavity 253 constitutes the second dielectric filler material layer 274. The adjacent combination of the first dielectric filler material layer 174 and the blocking dielectric liner 144 constitutes the first composite dielectric layer (144, 174). The adjacent combination of the second dielectric filler material layer 274 and the blocking dielectric liner 144 constitutes the second composite dielectric layer (144, 274).

[0126] An anisotropic etching process can be performed to remove horizontal extensions of the dielectric fill material from above the top surface of the sacrificial contact level dielectric layer 282 and from the bottom of each of the lateral isolation trenches 79. Each remaining tubular portion of the dielectric fill material that remains within the respective lateral isolation trench 79 constitutes an insulating spacer 74. A laterally extending cavity 79' may be present within each unfilled volume of the lateral isolation trench 79 that is laterally surrounded by a respective one of the insulating spacers 74.

[0127] Generally, a first composite dielectric layer (144, 174) may be interposed between the first stepped surface and the first stepped dielectric material portion 165 and includes a first barrier dielectric liner 144 and a first dielectric fill material layer 174 embedded within the first barrier dielectric liner 144. The first barrier dielectric liner 144 contacts each top surface of the first dielectric fill material layer 174, each bottom surface of the first dielectric fill material layer 174, and a subset of the sidewalls of the first dielectric fill material layer 174. A second composite dielectric layer (144, 274) may be interposed between the second stepped surface and the second stepped dielectric material portion 265 and includes a second barrier dielectric liner 144 and a second dielectric fill material layer 274 embedded within the barrier dielectric liner 144. The second barrier dielectric liner 144 contacts each top surface of the second dielectric fill material layer 274, each bottom surface of the second dielectric fill material layer 274, and a subset of the sidewalls of the second dielectric fill material layer 274.

[0128] Each composite dielectric layer {(144, (174 or 274)} includes a horizontally extending portion and a vertically extending portion that are interconnected above the stepped surface. The vertical thickness of the horizontally extending portion and the lateral thickness of the vertically extending portion are the same for each composite dielectric layer {(144, (174 or 274)} and are greater than the interlayer gap between vertically adjacent pairs of the first insulating layer 132 within the first alternating stack (232, 246) and are greater than the interlayer gap between vertically adjacent pairs of the second insulating layer 232 within the second alternating stack (132, 146).

[0129] Reference Figure 27 , at least one conductive fill material can optionally be deposited within the laterally extending cavity 79'. The portion of the at least one conductive material that overlies a horizontal plane including the top surface of the sacrificial contact level dielectric layer 282 can be removed by a planarization process such as a recess etching process and / or a chemical mechanical polishing process. Each remaining portion of the at least one conductive fill material that fills the respective laterally extending cavity 79' constitutes a source contact via structure 76. Alternatively, if the source region 61 is omitted, then the source contact via structure 76 can also be omitted at this step. Alternatively, the lateral isolation trench 79 can be completely filled with the insulating spacer 74.

[0130] Reference Figure 28 ,A photoresist layer (not shown) may be applied over the sacrificial contact-level dielectric layer 282, and the photoresist layer may be lithographically patterned to form an opening in an area overlapping the top surface of the sacrificial fin cavity fill material structure 84. An anisotropic etching process may be performed to form an etch through the unmasked portion of the sacrificial contact-level dielectric layer 282 to physically expose the top surface of the sacrificial fin cavity fill material structure 84. A selective etching process may be performed to selectively remove the sacrificial fill material of the sacrificial fin cavity fill material structure 84 for the materials of the annular insulating plate 40, the stepped dielectric material portions (165, 265), and the dielectric isolation layer 6 (if present). A fin contact via cavity 87 is formed in the volume from which the sacrificial fin cavity fill material structure 84 has been removed. The fin contact via cavity 87 includes a first fin contact via cavity 87A and a second fin contact via cavity 87B, with the first stepped dielectric material portion 165 being exposed to the first fin contact via cavity and the first stepped dielectric material portion 165 not being exposed to the second fin contact via cavity. Each fin contact via cavity 87 includes a cylindrical cavity portion 87C and a fin cavity portion 87F.

[0131] Reference Figure 29 ,An isotropic etching process may be performed to isotropically etch the materials of the first insulating liner 152 and the second insulating liner 252. The duration of the isotropic etching may be selected such that the etching distance of the materials of the first insulating liner 152 and the second insulating liner 252 is greater than the thicknesses of the first insulating liner 152 and the second insulating liner 252. Accordingly, each physically exposed portion of the first insulating liner 152 and the second insulating liner 252 underlying the fin cavity portion 87F is etched through. Each layer of the conductive layers (146, 246) has a corresponding annular top surface section physically exposed to a corresponding one of the fin cavity portions 87F of the fin contact via cavity 87. The annular tapered concave surfaces of the insulating liners (152, 252) may be physically exposed around each fin cavity portion 87F. The isotropic etching for the first insulating liner 152 and the second insulating liner 252 may include dilute hydrofluoric acid etching.

[0132] In the presence of the barrier dielectric layer 44, additional isotropic etching may be performed to remove the exposed portions of the corresponding barrier dielectric liner 144 and the corresponding backside barrier dielectric layer 44. If the corresponding barrier dielectric liner 144 and the backside barrier dielectric layer 44 include aluminum oxide, the isotropic etching may include hot phosphoric acid etching.

[0133] In one embodiment, surface portions of the stepped dielectric material portions (165, 265), the annular insulating plate 40, the contact-level dielectric layer 280, the interlayer dielectric layer 180, and the dielectric isolation layer 6 may be isotropically recessed in parallel during the isotropic etching process.

[0134] Common reference Figures 16A to 29 Regarding the processing steps, the proximal portions of the first sacrificial liner 154 and the first insulating liner 152 can be removed around the volume of each first contact via cavity 81A to form a first finned contact via cavity 87A, and the proximal portions of the second sacrificial liner 254 and the second insulating liner 252 can be removed around the volume of each second contact via cavity 81B to form a second finned contact via cavity 87B. After removing the first sacrificial fin cavity fill material structure 84A that forms the first finned contact via cavity 87A, the annular top surface section of the first conductive layer 146 can be physically exposed by at least removing the proximal portion of the first insulating liner 152. After removing the second sacrificial fin cavity fill material structure 84B that forms the second finned contact via cavity 87B, the annular top surface section of the second conductive layer 246 can be physically exposed by at least removing the proximal portion of the second insulating liner 252.

[0135] Reference Figure 30A And Figure 30B , at least one conductive material, such as at least one metal material, can be deposited in the finned contact via cavity 87. The at least one conductive material can include a combination of a metal barrier liner material (such as TiN, TaN, WN, MoN, or a combination thereof) and a metal fill material (such as W, Ti, Ta, Mo, Ru, Co, Cu, etc.). The excess portion of the at least one conductive material can be removed from above the horizontal plane including the top surface of the contact level dielectric layer 280 by a planarization process (such as a chemical mechanical polishing process). In one embodiment, the sacrificial contact level dielectric layer 282 and the portions of the insulating spacer 74 and the source contact via structure 76 that overlie the horizontal plane including the top surface of the contact level dielectric layer 280 can be removed in parallel during the planarization process. Each remaining portion of the at least one conductive material that fills the corresponding finned contact via cavity 87 constitutes a contact via structure, which is referred to herein as the layer contact via structure 86.

[0136] The layer contact via structure 86 includes a first contact via structure 86A formed in a first fin contact via cavity 87A and a second contact via structure 86B formed in a second fin contact via cavity 87B. Each of the layer contact via structures 86 extends vertically at least from the bottommost surface of the first alternating stack (132, 146) to a horizontal plane located at or above the top surface of the memory opening fill structure 58. Each layer contact via structure 86 includes a respective conductive pillar portion 86C and a respective conductive fin portion 86F that laterally projects from the respective conductive pillar portion 86C and has a first annular bottom surface section ABSS1 that contacts an annular top surface section of one of the contact conductive layers (146, 246). Each conductive fin portion 86F may also have a second annular bottom surface section ABSS2 that contacts an annular top surface section of the annular insulating plate 40, which may be the topmost annular insulating plate 40 within a vertical stack of annular insulating plates 40 underlying the respective conductive fin portion 86F. Sections ABSS1 and ABSS2 may be horizontally coplanar. Each conductive fin portion 86F may have an annular top surface ATS that contacts an annular bottom surface section of one of the stepped dielectric material portions (165, 265).

[0137] A plurality of first contact via structures 86A extend vertically through the first stepped dielectric material portion 165 and the second stepped dielectric material portion 265. A plurality of second contact via structures 86B extend vertically through the second stepped dielectric material portion 265. In one embodiment, each annular insulating plate 40 within the vertical stack of annular insulating plates 40 has a lateral width that causes the respective conductive layer (146, 246) to be laterally offset from the conductive pillar portion 86C by a uniform lateral offset distance, which is referred to herein as the first lateral offset distance lod1. Each conductive fin portion 86F of the layer contact via structure 86 may have an outer sidewall that is laterally spaced from the sidewall of the conductive pillar portion 86C of the layer contact via structure 86 by a second lateral offset distance lod2.

[0138] Common reference Figures 1 to 30BAnd according to various embodiments of the present disclosure, a memory device includes: a first alternating stack (132, 146) of a first insulating layer 132 and a first conductive layer 146, wherein the first alternating stack (132, 146) includes a first stepped surface in a contact region 300; a first stepped dielectric material portion 165 overlying the first stepped surface of the first alternating stack (132, 146); a memory opening 49 that extends at least vertically through each layer within the first alternating stack (132, 146); a memory opening fill structure 58 that is located within the memory opening 49 and includes a vertical semiconductor channel 60 and a vertical stack of memory elements (e.g., portions of a memory film 50); and a first contact via structure 86A that extends at least vertically from the bottommost surface of the first alternating stack (132, 146) through the first stepped dielectric material portion 165 and to a horizontal plane located at or above the top surface of the memory opening fill structure 58. The first contact via structure 86A includes a conductive column portion 86C and a conductive fin portion 86F that laterally protrudes from the conductive column portion 86C and has a first annular bottom surface section ABSS1 that contacts an annular top surface section of one of the layers in the first conductive layer 146.

[0139] In one embodiment, the memory device includes a vertical stack of annular insulating plates 40 that laterally surround and contact the conductive column portion 86C and underlie the conductive fin portion 86F. The annular insulating plates 40 isolate the conductive layers (146, 246) underlying the conductive fin portion 86F from contacting the conductive column portion 86C. This prevents short - circuits between conductive layers at different vertical levels caused by the conductive column portion 86C.

[0140] In one embodiment, the topmost annular insulating plate 40 within the vertical stack of annular insulating plates 40 contacts a second annular bottom surface section of the conductive fin portion 86F.

[0141] In one embodiment, the memory device includes a back - side blocking dielectric layer 44, wherein each layer in the back - side blocking dielectric layer 44 is embedded in a corresponding one of the first conductive layers 146 and is interposed between a corresponding one of the first conductive layers 146 and a corresponding one of the first insulating layers 132. In one embodiment, each annular insulating plate 40 within the vertical stack of annular insulating plates 40 contacts a sidewall of a corresponding one of the layers in the back - side blocking dielectric layer 44.

[0142] In one embodiment, each annular insulating plate 40 within the vertical stack of annular insulating plates 40 has a lateral width that laterally offsets a corresponding one of the conductive layers (146, 246) located at the same vertical level (as plate 40) by a uniform lateral offset distance lod1 from the conductive post portion 86C.

[0143] In one embodiment, the conductive fin portion 86F includes an annular top surface that contacts an annular planar surface section of the first stepped dielectric material portion 165. In one embodiment, the conductive post portion 86C includes: a first cylindrical surface that extends vertically through the first stepped dielectric material portion 165 and has a bottom perimeter that abuts an inner perimeter of the annular top surface of the conductive fin portion 86F; and a second cylindrical surface that extends vertically through a subset of the layers within the first alternating stack (132, 146) and has a top perimeter that abuts a bottom surface of the conductive fin portion 86F.

[0144] In one embodiment, the memory device includes a composite dielectric layer (144, 174) that is interposed between the first stepped surface and the first stepped dielectric material portion 165 and includes a barrier dielectric liner 144 and a dielectric fill material layer 174 embedded within the barrier dielectric liner 144, wherein the barrier dielectric liner 144 contacts each top surface and each bottom surface of the dielectric fill material layer 174. In one embodiment, the conductive fin portion 86F contacts a sidewall of the dielectric fill material layer 174.

[0145] In one embodiment, the memory device further includes a backside barrier dielectric layer 44 that is interposed between each adjacent pair of the first conductive layer 146 and the first insulating layer 132 within the first alternating stack (132, 146) and has the same material composition and the same thickness as the barrier dielectric liner 144. In one embodiment, the composite dielectric layer (144, 174) includes a horizontally extending portion and a vertically extending portion that are interconnected above the first stepped surface; and the vertical thickness of the horizontally extending portion and the lateral thickness of the vertically extending portion are the same and are greater than the interlayer gap between vertically adjacent pairs of the first insulating layer 132 within the first alternating stack (132, 146).

[0146] In one embodiment, the memory device further includes: a second alternating stack (232, 246) of a second insulating layer 232 and a second conductive layer 246 in the first alternating stack (232, 246), wherein the second alternating stack (132, 146) includes a second stepped surface in the contact region 300, and wherein the memory opening fill structure 58 extends vertically through the second alternating stack (232, 246); a second stepped dielectric material portion 265 overlying the second stepped surface of the second alternating stack (232, 246); and a second contact via structure 86B extending vertically at least from the bottommost surface of the first alternating stack (132, 146) to a horizontal plane at or above the top surface of the memory opening fill structure 58, and including an additional conductive pillar portion 86C and an additional conductive fin portion 86F, the additional conductive fin portion protruding laterally from the additional conductive pillar portion 86C and having an additional annular bottom surface section that contacts an annular top surface section of one of the second conductive layers 246.

[0147] The above method provides a more precise method of forming the contact via structure 86. Accordingly, the formation of a contact via cavity 87 that penetrates or fails to reach the corresponding conductive layer (146, 246) due to etching non-uniformity can be avoided. The conductive fin portion 86F of the layer contact via structure 86 provides a reliable electrical contact between the conductive layer (146, 246) and the layer contact via structure 86, which can be used as a word line contact via structure.

[0148] Reference Figure 31 , a schematic top view of a semiconductor die 900 is shown, which includes a second exemplary structure according to an embodiment of the present disclosure. The semiconductor die may include a plurality of memory planes (P0 to P7), each memory plane including a pair of corresponding three-dimensional memory arrays located in a corresponding memory array region 100 (e.g., 100A and 100B). Each three-dimensional memory array may be formed in a corresponding memory array region 100. A pair of contact regions 300 (e.g., 300A and 300B) may be provided between the pair of memory array regions 100 in each plane (P0 to P7). The pair of memory array regions 100 within each plane (P0 to P7) may be laterally spaced apart from each other along a first horizontal direction (e.g., the word line direction) hd1. Generally, in the second exemplary structure, at least two alternating stacks of the insulating layers (132, 232) and the conductive layers (146, 246) and the layer contact via structure 86 described with reference to the first exemplary structure may be employed.

[0149] Reference Figure 32, illustrates a second exemplary structure of a vertical stack including a three-layer structure (1000, 2000, 3000), which can be formed by adopting the processing steps described with reference to the first exemplary structure, wherein the pattern of the alternating stack {(132, 142), (232, 242), (332, 342)} is modified. Figure 32 The illustrated second exemplary structure is a three-layer structure including a lower layer structure 1000, an intermediate layer structure 2000, and an upper layer structure 3000. Figure 32 The cutting plane of the vertical sectional view corresponds to Figure 31 the vertical plane X-X' in Figure 32 The illustrated region includes, from left to right, an end portion of the first memory array region 100A, a first contact region 300A, a second contact region 300B, and an end portion of the second memory array region 100B.

[0150] The lower layer structure 1000 can be formed by performing the processing steps described with reference to Figures 1 to 6 wherein the pattern of the first stepped surface formed at the processing step in Figure 1 is modified. Specifically, the first stepped surface of each patterned first alternating stack (132, 142) can be formed in the corresponding contact region 300. Since a pair of contact regions 300 (e.g., 300A and 300B) are adjacent to each other and are laterally spaced apart from each other along the first horizontal direction hd1 in each plane (P0 to P7), a pair of first stepped surfaces within a pair of adjacent contact regions (300A and 300B) can be laterally spaced apart by a first lateral spacing LS1 along the first horizontal direction, and the first lateral spacing can be in the range of 100 nm to 1,000 nm, but smaller and larger first lateral spacings LS1 can also be adopted. The first stepped dielectric material portion 165 can be formed on a pair of adjacent first stepped surfaces.

[0151] Each first alternating stack (132, 142) in the second exemplary structure is also referred to as a lower layer alternating stack (132, 142). Each set of stepped surfaces on the first alternating stack (132, 142) is referred to as a lower layer stepped surface herein. In the second exemplary structure, the first layer sacrificial memory opening filling structure 148 is also referred to as a lower layer sacrificial memory opening filling structure 148, and the first layer sacrificial contact opening filling structure 138 is also referred to as a lower layer sacrificial contact opening filling structure 138.

[0152] The first lower layer alternating stack (132, 142) is located in the first memory array region 100A and the first contact region 300A, and the second lower layer alternating stack (132, 142) is located in the second memory array region 100B and the second contact region 300B. Each lower layer alternating stack in the lower layer alternating stack (132, 232) includes a respective vertical alternating sequence of a lower layer insulating layer 132 and a lower layer sacrificial material layer 142. In the second exemplary structure, the first stepped dielectric material portion 165 is also referred to as the lower stepped dielectric material portion 165. In the second exemplary structure, the first insulating pad 152 is also referred to as the lower insulating pad 152. In the second exemplary structure, the first sacrificial pad 154 is also referred to as the lower sacrificial pad 154. A lower sacrificial support opening filling structure (not shown) may be formed as needed.

[0153] The lower sacrificial memory opening filling structure 148 is formed in the first memory array region 100A and the second memory array region 100B. The lower sacrificial contact opening filling structure 138 is formed in each region where a layer contact via structure 86 will subsequently be formed. The regions where the lower sacrificial contact opening filling structure 138 is formed include the region of the lower stepped surface of the lower layer alternating stack (132, 232), the region of the intermediate layer stepped surface of the intermediate layer structure 2000, and the region of the upper stepped surface of the upper layer structure 3000. Specifically, the region of the lower sacrificial contact opening filling structure 138 includes the region of the central portion of the horizontal extension surface of the lower stepped surface of the lower layer alternating stack (132, 232), the intermediate layer stepped surface of the intermediate layer structure 2000, and the upper stepped surface of the upper layer structure 3000.

[0154] The intermediate layer structure 2000 can be formed by performing the processing steps described with reference to Figures 7 to 9 and by performing the processing steps described with reference to Figures 4 to 6 where the processing parameters for forming the intermediate layer sacrificial memory opening filling structure 248 and the intermediate layer sacrificial contact opening filling structure 238 are appropriately modified. Each second alternating stack (232, 242) in the second exemplary structure is also referred to as the intermediate layer alternating stack (232, 242). Each set of stepped surfaces on the intermediate layer alternating stack (232, 242) is referred to herein as the intermediate layer stepped surface. The intermediate layer sacrificial memory opening filling structure 248 is formed on the lower sacrificial memory opening filling structure 148. The intermediate layer sacrificial contact opening filling structure 238 is formed on the lower sacrificial contact opening filling structure 138.

[0155] In one embodiment, the intermediate layer structure 2000 includes a first intermediate layer alternating stack (232, 242) formed in the first memory array region 100A and the first contact region 300A, a second intermediate layer alternating stack (232, 242) formed in the second memory array region 100B and the second contact region 300B, and a passive alternating stack 203 formed between the first intermediate layer alternating stack (232, 242) and the second intermediate layer alternating stack (232, 242) and extending across the first contact region 300A and the second contact region 300B. Each of the first intermediate layer alternating stack (232, 242), the second intermediate layer alternating stack (232, 242), and the passive alternating stack 203 includes a respective vertical alternating sequence of an intermediate layer insulating layer 232 and an intermediate layer sacrificial material layer 242.

[0156] The first intermediate layer alternating stack (232, 242) and the second intermediate layer alternating stack (232, 242) may be laterally spaced apart by a lateral pitch along a first horizontal direction hd1, which may be referred to as a second lateral pitch LS2 or a first lateral pitch LS1'. The second lateral pitch LS2 or the first lateral pitch LS1' is greater than the lateral extent of the passive alternating stack 203 along the first horizontal direction hd1. A second stepped dielectric material portion 265 may be formed over the stepped surfaces of the intermediate layer alternating stack (232, 242), e.g., between the passive alternating stack 203 and the first intermediate layer alternating stack (232, 242) and between the passive alternating stack 203 and the second intermediate layer alternating stack (232, 242).

[0157] In the second exemplary structure, the second stepped dielectric material portion 265 is also referred to as an intermediate layer stepped dielectric material portion 265. In the second exemplary structure, the second insulating liner 252 is also referred to as an intermediate layer insulating liner 252. In the second exemplary structure, the second sacrificial liner 254 is also referred to as an intermediate layer sacrificial liner 254. The passive alternating stack 203 may not have any intermediate layer sacrificial memory opening filling structures 248, i.e., no intermediate layer sacrificial memory opening filling structures 248 may be included therein.

[0158] The passive alternating stack 203 may include a first stepped surface formed in the first contact region 300A and a second stepped surface formed in the second contact region 300B. In the first contact region 300A, each horizontal extension surface of the first stepped surface of the passive alternating stack 203 may have an area overlap with the corresponding horizontal extension surface of the stepped surface of the first lower alternating stack (132, 142). In the second contact region 300B, each horizontal extension surface of the second stepped surface of the passive alternating stack 203 may have an area overlap with the corresponding horizontal extension surface of the stepped surface of the second lower alternating stack (132, 142). An intermediate layer sacrificial support opening filling structure (not shown) may be formed as needed.

[0159] The intermediate layer sacrificial memory opening filling structure 248 is formed in the first memory array region 100A and the second memory array region 100B. The intermediate layer sacrificial contact opening filling structure 238 is formed in each region where the layer contact via structure 86 will be subsequently formed. The regions where the intermediate layer sacrificial contact opening filling structure 238 is formed include the regions of the lower stepped surfaces of the lower alternating stack (132, 232), the regions of the intermediate stepped surfaces of the intermediate layer structure 2000, and the regions of the upper stepped surfaces of the upper layer structure 3000. Specifically, the regions of the intermediate layer sacrificial contact opening filling structure 238 include the regions of the central portions of the horizontal extension surfaces of the lower stepped surfaces of the lower alternating stack (132, 232), the intermediate stepped surfaces of the intermediate layer structure 2000, and the upper stepped surfaces of the upper layer structure 3000.

[0160] The upper layer structure 3000 can be formed by performing the processing steps described with reference to Figures 7 to 9 where the patterns of various elements are appropriately modified. The alternating stacks formed within the upper layer structure 3000 are collectively referred to as the upper alternating stacks (332, 342). Each set of stepped surfaces on the upper alternating stacks (332, 342) is referred to herein as an upper stepped surface.

[0161] In one embodiment, the upper layer structure 3000 includes a first upper alternating stack (332, 342) formed in the first memory array region 100A and the first contact region 300A, a second upper alternating stack (332, 342) formed in the second memory array region 100B and the second contact region 300B, and a passive alternating stack 303 formed between the first upper alternating stack (332, 342) and the second upper alternating stack (332, 342) and extending across the first contact region 300A and the second contact region 300B. Each of the first upper alternating stack (332, 342), the second upper alternating stack (332, 342), and the passive alternating stack 303 includes a corresponding vertical alternating sequence of an upper insulating layer 332 and an upper sacrificial material layer 342.

[0162] The first upper alternating stack (332, 342) and the second upper alternating stack (332, 342) may be laterally spaced apart by a lateral spacing along a first horizontal direction hd1, and this lateral spacing may be referred to as a second lateral spacing LS2'. The second lateral spacing LS2' is greater than the lateral extent of the passive alternating stack 303 along the first horizontal direction hd1. An upper stepped dielectric material portion 365 may be formed over the stepped surfaces of the upper alternating stack (332, 342), for example, between the passive alternating stack 303 and the first upper alternating stack (332, 342) and between the passive alternating stack 303 and the second upper alternating stack (332, 342).

[0163] The upper insulating liner 352 may be formed in the second exemplary structure by performing the processing steps for forming the second insulating liner 252 in the first exemplary structure. The upper sacrificial liner 354 may be formed in the second exemplary structure by performing the processing steps for forming the second sacrificial liner 254 in the first exemplary structure.

[0164] The passive alternating stack 303 may include a first stepped surface formed in a first contact region 300A and a second stepped surface formed in a second contact region 300B. In the first contact region 300A, each horizontal extending surface of the first stepped surface of the passive alternating stack 303 may have an area overlap with a corresponding horizontal extending surface of the stepped surface of the first intermediate layer alternating stack (232, 242). In the second contact region 300B, each horizontal extending surface of the second stepped surface of the passive alternating stack 303 may have an area overlap with a corresponding horizontal extending surface of the stepped surface of the second intermediate layer alternating stack (232, 242).

[0165] Reference Figure 33 and, the processing steps described in reference Figure 10 and Figure 11 may be performed, wherein the pattern of the openings formed through the upper structure to form various sacrificial contact opening filling structures 38 and sacrificial support opening filling structures (not shown) is appropriately modified. The sacrificial contact opening filling structure 38 is formed in each region where a layer contact via structure 86 will be subsequently formed. The regions where the sacrificial contact opening filling structure 38 is formed include the regions of the lower stepped surfaces of the lower alternating stack (132, 232), the regions of the upper stepped surfaces of the upper structure 2000, and the regions of the upper stepped surfaces of the upper structure 3000. Specifically, the regions of the sacrificial contact opening filling structure 38 include the regions of the central portions of the horizontal extending surfaces of the lower stepped surfaces of the lower alternating stack (132, 232), the upper stepped surfaces of the upper structure 2000, and the upper stepped surfaces of the upper structure 3000.

[0166] Reference Figure 34 , in view of the presence of the intermediate layer structure 2000 and the lower layer structure 1000 below the upper layer structure 3000, a reference is formed without appropriate modification Figures 12 to 15 The processing steps described to form the memory opening fill structure 58 and an optional support pillar structure (not shown). As discussed above, each memory opening fill structure in the memory opening fill structure 58 includes a corresponding vertical semiconductor channel 60, a corresponding vertical stack of memory elements (e.g., a portion of the memory film 50), a drain region 63, and an optional dielectric core 62. Each support pillar structure in the support pillar structure 20 may include a dielectric material, or may include a dummy vertical semiconductor channel (which is not electrically connected to the bit line), a dummy memory film, a dummy drain region, and an optional dielectric core, which include the same materials as those of the memory opening fill structure 58. Generally, the passive alternating stack (203, 303) may not include memory openings or the memory opening fill structure 58.

[0167] Although embodiments are described in which the second exemplary structure has a three-layer structure including a lower layer structure 1000, an intermediate layer structure 2000, and an upper layer structure 3000, the present disclosure can generally be practiced with two or more layer structures (such as two, four, etc. layer structures). Thus, the illustrated second exemplary structure can be modified to include only two layer structures, or can be modified to include four or more layer structures, which include the three layer structures (1000, 2000, 3000) and at least one additional layer structure. In addition, the positions of the layer structures can vary vertically in any order. For example, the patterns of any pair of layer structures (1000, 2000, 3000) in the second exemplary structure can be exchanged without affecting the functionality of the second exemplary structure. In the illustrative example, the pattern of the upper layer structure 3000 and the pattern of the lower layer structure 1000 can be exchanged, the pattern of the upper layer structure 3000 and the pattern of the intermediate layer structure 2000 can be exchanged, and so on.

[0168] In summary, the second exemplary structure may include a vertical stack of a plurality of layer structures, the plurality of layer structures including at least a first layer structure and a second layer structure. The first layer structure may be any one of the lower layer structure 1000, the intermediate layer structure 2000, the upper layer structure 3000, or any additional layer structure (not shown) formed above the upper layer structure 3000. The second layer structure may include any other layer structure within the vertical stack. In an illustrative example, the first layer structure may include, for example, the lower layer structure 1000 or the intermediate layer structure 2000, and the second layer structure may include the intermediate layer structure 2000 or the upper layer structure 3000. In one embodiment, the first layer structure may include the lower layer structure 1000, and the second layer structure may include the intermediate layer structure 2000. In another embodiment, the first layer structure may include the intermediate layer structure 2000, and the second layer structure may include the upper layer structure 3000.

[0169] In accordance with one aspect of the present disclosure, a first layer structure is formed over a substrate 8, the first layer structure including a first first-layer alternating stack (101 or 101') and a second first-layer alternating stack (102 or 102'). Each of the first first-layer alternating stack (101 or 101') and the second first-layer alternating stack (102 or 102') includes a respective vertical alternating sequence of a first layer insulating layer (132, 232, or 332) and a first layer sacrificial material layer (142, 242, or 342). In a first exemplary embodiment, the first first-layer alternating stack 101 includes a first lower alternating stack (132, 142) formed in a first memory array region 100A, and the second first-layer alternating stack 102 includes a second lower alternating stack (132, 142) formed in a second memory array region 100B. In a second exemplary embodiment, the first first-layer alternating stack 101' includes a first intermediate-layer alternating stack (232, 242) formed in a first memory array region 100A, and the second first-layer alternating stack 102' includes a second intermediate-layer alternating stack (232, 242) formed in a second memory array region 100B.

[0170] In addition, a second layer structure is formed over the substrate 8, the second layer structure including a first second layer alternating stack (201 or 201') and a second second layer alternating stack (202 or 202') that are laterally spaced apart from each other by a passive alternating stack (203 or 303). The second layer structure may be formed above or below the first layer structure. Each of the first second layer alternating stack (201 or 201'), the second second layer alternating stack (202 or 202'), and the passive alternating stack (203 or 303) includes a respective vertical alternating sequence of a second layer insulating layer (232, 332, or 132) and a second layer sacrificial material layer (242, 342, or 142). In a first exemplary embodiment, the first second layer alternating stack 201 includes a first intermediate layer alternating stack (232, 242) formed in the first memory array region 100A, and the second second layer alternating stack 202 includes a second intermediate layer alternating stack (232, 242) formed in the second memory array region 100B. In a second exemplary embodiment, the first second layer alternating stack 201' includes a first upper layer alternating stack (332, 342) formed in the first memory array region 100A, and the second second layer alternating stack 202' includes a second upper layer alternating stack (332, 342) formed in the second memory array region 100B.

[0171] In one embodiment, the first layer structure and the second layer structure overlie the substrate 8, and the first first layer alternating stack (101 or 101') includes a first stepped surface such that the lateral extent of the first layer sacrificial material layer (142, 242, or 342) in the first first layer alternating stack (101 or 101') decreases with the vertical distance from the substrate 8. The passive alternating stack (203 or 303) includes a second stepped surface such that the lateral extent of the second layer sacrificial material layer (242, 342, or 142) in the passive alternating stack (203 or 303) decreases with the vertical distance from the substrate 8. The sacrificial contact opening fill structure 38 extends vertically through the first stepped surface and through the second stepped surface.

[0172] In one embodiment, the first first layer alternating stack (101 or 101') and the second first layer alternating stack (102 or 102') are laterally spaced apart from each other by a first lateral spacing (LS1 or LS1') along a first horizontal direction hd1; the first second layer alternating stack (201 or 201') and the second second layer alternating stack (202 or 202') are laterally spaced apart from each other by a second lateral spacing (LS2 or LS2') along the first horizontal direction hd1, the second lateral spacing being greater than the first lateral spacing (LS1 or LS1'); and the passive alternating stack (203 or 303) has a lateral extent along the first horizontal direction hd1 that is less than the second lateral spacing (LS2 or LS2').

[0173] In one embodiment, the passive alternating stack (203 or 303) includes a first set of stepped surfaces and a second set of stepped surfaces that are laterally spaced apart from each other; the first set of stepped surfaces has an area overlap with the first first-layer alternating stack (101 or 101') in a plan view; and the second set of stepped surfaces has an area overlap with the second first-layer alternating stack (102 or 102') in a plan view.

[0174] In one embodiment, the passive alternating stack (203 or 303) does not laterally surround any material portion having the same material composition as the memory element (such as a portion of the charge storage layer 54). In one embodiment, the passive alternating stack (203 or 303) does not laterally surround any semiconductor material portion, such as the vertical semiconductor channel 60 or the drain region 63.

[0175] A subset of the sacrificial contact opening fill structures 38 extends vertically through a pair of corresponding sacrificial pads (154, 254, 354) and contacts the cylindrical surface segments of the pair of corresponding sacrificial pads. A subset of the sacrificial contact opening fill structures 38 may extend vertically through two horizontally extending surfaces of two stepped surfaces within the first-layer structure and the second-layer structure.

[0176] In one embodiment, the first memory stack structure 55 (located in the first memory opening fill structure 58) extends vertically through the first first-layer alternating stack (101 or 101') and the first second-layer alternating stack (201 or 201'), and the second memory stack structure 55 (located in the second memory opening fill structure 58) extends vertically through the second first-layer alternating stack (102 or 102') and the second second-layer alternating stack (202 or 202'). Each of the first memory stack structure 55 and the second memory stack structure 55 includes a corresponding set of memory elements (such as a portion of the charge storage layer 54) located at the levels of the first-layer sacrificial material layer (142, 242, or 342) and the second-layer sacrificial material layer (242, 342, or 142).

[0177] Reference Figure 35 , a contact-level dielectric layer 380 may optionally be formed over the upper layer structure 3000. The processing steps described in reference Figure 16A and Figure 16B may be performed to form the contact via cavity 81. Specifically, the contact via cavity 81 may be formed by forming an opening through the contact-level dielectric layer 380 and by removing the sacrificial contact opening fill structures 38.

[0178] Reference Figure 36 may be performed, and reference Figure 17The described processing steps. A lateral recess 41 is formed in the volume of the material from which the sacrificial material layer (142, 242, 342) has been removed. A lower annular cavity 155 can be formed in each volume from which an annular portion of the lower sacrificial liner 154 has been removed around the corresponding contact via cavity 81 in the contact via cavities. An intermediate layer annular cavity 255 can be formed in each volume from which an annular portion of the intermediate layer sacrificial liner 254 has been removed around the corresponding contact via cavity 81 in the contact via cavities. An upper layer annular cavity 355 can be formed in each volume from which an annular portion of the upper layer sacrificial liner 354 has been removed around the corresponding contact via cavity 81 in the contact via cavities. The contact via cavity 81 is converted into a fin-shaped contact via cavity 82 in the first stage process. A subset of the fin-shaped contact via cavities 82 in the first stage process that vertically extends through a pair of corresponding stepped surfaces located in two different layer structures includes a pair of corresponding annular cavities (155 and 255) or (255 and 355).

[0179] Reference Figure 37 , the reference can be executed Figure 18 and Figure 19 The described processing steps can be executed to form an annular insulating plate 40 in the lateral recess 41. The fin-shaped contact via cavity 82 in the first stage process is converted into a fin-shaped contact via cavity 83 in the second stage process. A subset of the fin-shaped contact via cavities 83 in the second stage process that vertically extends through a pair of corresponding stepped surfaces located in two different layer structures includes a pair of corresponding annular cavities (155 and 255) or (255 and 355).

[0180] Reference Figure 38 , the reference can be executed Figure 20 and Figure 21The described processing steps. Specifically, a second isotropic etching process can be performed to isotropically recess the material of the sacrificial pads (154, 254, 354) selectively with respect to the materials of the contact-level dielectric layer 380, the insulating layers (132, 232, 332), the interlayer dielectric layers (180, 280), the dielectric isolation layer 6 (if present), and the annular insulating plate 40. For example, if the sacrificial pads (154, 254, 354) include silicon nitride, a wet etching process using hot phosphoric acid can be performed to isotropically recess the sacrificial pads (154, 254, 354). The volume of each annular cavity portion can be laterally expanded by the second isotropic etching process. The fin contact via cavity 83 in the second stage process expanded by the second isotropic etching process is referred to herein as the fin contact via cavity in the third stage process. A sacrificial fill material can be deposited in the fin contact via cavity in the third stage process to form a sacrificial fin cavity fill material structure 84. Each sacrificial fin cavity fill material structure 84 includes a corresponding cylindrical fill material portion and at least one fin-shaped fill material portion. Each fin-shaped fill material portion has a corresponding annular shape. According to one aspect of the present disclosure, a subset of the sacrificial fin cavity fill material structures 84 that vertically extends through two step surfaces located in two different layer structures includes a pair of fin-shaped fill material portions.

[0181] In summary, the sacrificial fin cavity fill material structures 84 can be formed through the first layer structure and the second layer structure. A subset of the sacrificial fin cavity fill material structures 84 can be laterally surrounded by the first annular insulating plate 40 at the level of a subset of the first layer sacrificial material layers (142, 242, or 342) located within the first first-layer alternating stack (101 or 101'), and can be laterally surrounded by the second annular insulating plate 40 at the level of a subset of the second layer sacrificial material layers (242, 342, or 142) located within the passive alternating stack (203 or 303').

[0182] Reference Figure 39 can be made, and reference Figure 22A and Figure 22B 、 Figure 23 、 Figure 24 、 Figure 25 and Figure 26The described processing steps are performed to form a laterally isolated trench, a source region (not shown), and a laterally extending cavity; a conductive layer (146, 246, 346) is formed in the laterally extending cavity, and the sacrificial liner (154, 254, 354) is replaced with a dielectric fill material layer (174, 274, 374). The conductive layer (146, 246, 346) may include a lower conductive layer 146 formed in the lower layer structure 1000, an intermediate conductive layer 246 formed in the intermediate layer structure 2000, and an upper conductive layer 346 formed in the upper layer structure 3000. In an active alternating stack including a memory opening fill structure 58, the bottommost lower conductive layer 146 can be used as a source select gate electrode, and the uppermost upper conductive layer 346 can be used as a drain select gate electrode. In the active alternating stack, the remaining conductive layers (146, 246, 346) can be used as word lines. The dielectric fill material layer (174, 274, 374) may include a lower dielectric fill material layer 174 formed in the lower layer structure 1000, an intermediate dielectric fill material layer 274 formed in the intermediate layer structure 2000, and an upper dielectric fill material layer 374 formed in the upper layer structure 3000.

[0183] Reference Figure 40 , the reference can be executed Figure 27 The described processing steps are performed to form a source contact via structure (not shown). The reference can be executed Figure 28 The described processing steps are performed to form a fin contact via cavity 87. Specifically, a selective etching process can be executed to selectively remove the sacrificial fill material of the sacrificial fin cavity fill material structure 84 for the materials of the annular insulating plate 40, the insulating layers (132, 232, 332), the stepped dielectric material portions (165, 265, 365), and the dielectric isolation layer 6 (if present). The fin contact via cavity 87 is formed in the volume from which the sacrificial fin cavity fill material structure 84 has been removed. Each fin contact via cavity 87 includes a cylindrical cavity portion 87C and a fin cavity portion 87F.

[0184] Subsequently, an isotropic etching process can be performed to etch the material of the insulating liners (152, 252, 352) isotropically. The duration of the isotropic etching can be selected such that the etching distance of the material of the insulating liners (152, 252, 352) is greater than the thickness of the insulating liners (152, 252, 352). Accordingly, each physically exposed portion of the insulating liners (152, 252, 352) underlying the fin cavity portion 87F is etched through. Each conductive layer in the conductive layers (146, 246, 346) has a corresponding annular top surface section of the corresponding fin cavity portion physically exposed in the fin cavity portion 87F of the fin contact via cavity 87. An annular tapered concave surface (not explicitly shown) of the insulating liners (152, 252, 352) can be physically exposed around each fin cavity portion 87F. The isotropic etching of the insulating liners (152, 252, 352) can include dilute hydrofluoric acid etching.

[0185] In the presence of a barrier dielectric liner (not shown), an additional isotropic etching can be performed to remove the exposed portions of the corresponding barrier dielectric liner and the corresponding barrier dielectric layer (not shown) around each fin cavity portion 87F. If the corresponding barrier dielectric liner and the barrier dielectric layer include aluminum oxide, the isotropic etching can include hot phosphoric acid etching.

[0186] Reference Figure 41 and Figure 30A and Figure 30B The processing steps described in

[0187] Reference Figure 42 can be performed to form a layer contact via structure 86 within each fin contact via cavity 87. Generally, the sacrificial fin cavity fill material structure 84 is replaced with the layer contact via structure 86. An interlayer conductive path 886 can be formed, which includes a corresponding pair of layer contact via structures 86, two conductive layers (146, 246, or 346) positioned in two different alternating stacks of an insulating layer (132, 232, or 332) and a conductive layer (146, 246, or 346) within the same layer structure, and a conductive layer (246, 346, or 146) positioned in a passive alternating stack (203 or 303) within a different layer structure.

[0188] The word line driving circuits (e.g., word line switching circuits) (710, 720, 731, 732) may then be electrically connected to each of the layer contact vias in the layer contact via structure 86 through corresponding word line switching transistors 702. For each conductive path 886 including a pair of a first layer contact via structure 86 and a second layer contact via structure 86, one of the first layer contact via structure 86 and the second layer contact via structure 86 may be electrically connected to a corresponding word line driving circuit (710, 720) through a corresponding word line switching transistor 702. For example, if a pair of lower-level conductive layers 146 in different active lower layer alternating stacks (132, 146) are electrically connected to each other through the first layer contact via structure 86 and the second layer contact via structure 86 and an intermediate layer conductive layer 246 in the passive alternating stack 203, one of the first layer contact via structure 86 and the second layer contact via structure 86 may be electrically connected to the output node of the lower layer word line driving circuit 710 (i.e., the word line switching transistor 702A).

[0189] In another example, if a pair of intermediate-level conductive layers 246 in different active intermediate layer alternating stacks (232, 246) are electrically connected to each other through the first layer contact via structure 86 and the second layer contact via structure 86 and an upper layer conductive layer 346 in the passive alternating stack 303, one of the first layer contact via structure 86 and the second layer contact via structure 86 may be electrically connected to the output node of the intermediate layer word line driving circuit 720 (i.e., the word line switching transistor 702B). If a pair of upper-level conductive layers 346 located in different memory array regions 100 and at the same level are not electrically connected to each other, such upper conductive layers 346 may be independently driven by two different upper layer word line driving circuits (731, 732) through corresponding word line switching transistors 702.

[0190] Therefore, the interlayer conductive path 886 between two active alternating stacks of an insulating layer (132, 232, 332) and a conductive layer (146, 246, 336) located within the same layer structure (i.e., at the same vertical level from the substrate 8) and laterally spaced apart from each other is provided through the passive alternating stacks (203, 303) and a pair of layer contact via structures 86.

[0191] The active alternating stack includes memory cells capable of storing data. For example, the active alternating stack includes a memory opening fill structure 58, which contains a memory film 50 capable of storing data. The passive alternating stack does not include any memory opening fill structures 58 and does not include memory cells capable of storing data. The conductive layers of the passive alternating stack (203, 303) act as electrical jumpers or interconnects (e.g., dummy word lines) between the conductive layers of the active alternating stack, and the conductive layers of the active alternating stack act as word lines or select gate electrodes located at the same vertical level from the substrate. Therefore, the passive alternating stack can be referred to as a jumper alternating stack. The passive alternating stack and the active alternating stack are located in different layers and are electrically connected to each other. Thus, each layer contact via structure 86 in the interlayer conduction path 886 contacts two conductive layers (146, 246, 346) located in different layer structures (i.e., the jumper conductive layer in the passive alternating stack and the active conductive layer (i.e., word line or select gate electrode) in the active alternating stack are located in different layer structures).

[0192] In another embodiment, instead of using the dummy word lines of the passive alternating stack as jumpers between the active word lines and select gate electrodes of the active alternating stack, all alternating stacks include active alternating stacks. In this embodiment, the active word lines or select gate electrodes of the jumper alternating stack (203, 303) can be used as jumpers for the word lines or select gate electrodes of the active alternating stack located in different layer structures. Thus, in this embodiment, the alternating stack (203, 303) is also an active alternating stack including memory cells, such as a memory opening fill structure 58 containing a memory film 50 capable of storing data.

[0193] Therefore, the total number of word line drivers and / or word line switch transistors 702 can be reduced by driving multiple conductive layers (146, 246, 346) located in different alternating stacks and interconnected by the interlayer conduction path 886, and a more compact semiconductor die can be fabricated. For example, a single word line driver 720 can be used to drive both the first active alternating stack (201 / 101') and the second active alternating stack (202 / 102') (and optionally, drive the "jumper" alternating stack 303 if the "jumper" alternating stack includes an active alternating stack instead of a passive alternating stack). In another example, a single word line driver 710 can be used to drive both the first active alternating stack 101 and the second active alternating stack 102. Therefore, for at least the second active alternating stack, a separate word line driver is not required. In addition, for each conductive layer in the corresponding interlayer conduction path 886, only one word line switch transistor 702 is used instead of multiple word line switch transistors.

[0194] Reference Figure 43, a composite view illustrating an alternative embodiment of the present disclosure, where the passive alternating stack is located below rather than above the active alternating stacks that are electrically connected to each other.

[0195] Figure 43 An alternative second exemplary structure can be obtained from Figure 41 and Figure 42 the second exemplary structure illustrated as follows: forming the lower layer structure 1000 to have the same pattern as the upper layer structure 3000 in Figure 41 and Figure 42 , forming the intermediate layer structure 2000 to have the same pattern as the lower layer structure 1000 in Figure 41 and Figure 42 , and forming the upper layer structure 3000 to have the same pattern as the intermediate layer structure 2000 in Figure 41 and Figure 42 . In other words, in Figure 43 , the upper layer structure 3000 from Figure 42 is moved below the lower layer structure 1000 from Figure 42 .

[0196] Subsequently, the word line driving circuits (710, 720, 731, 732) can be electrically connected to each of the layer contact via structures 86. For each conductive path 886 including a pair of first layer contact via structures 86 and second layer contact via structures 86, one of the first layer contact via structure 86 and the second layer contact via structure 86 can be electrically connected to the corresponding word line driving circuit (720, 730). For example, if a pair of intermediate layer conductive layers 246 located in different active intermediate layer alternating stacks (232, 246) are electrically connected to each other through the first layer contact via structure 86 and the second layer contact via structure 86 and the upper conductive layer 346 located in the passive alternating stack 203, one of the first layer contact via structure 86 and the second layer contact via structure 86 can be electrically connected to the output node (e.g., word line switching transistor 702B) of the intermediate layer word line driving circuit 720. If a pair of upper layer conductive layers 346 located in different active upper layer alternating stacks (332, 346) are electrically connected to each other through the first layer contact via structure 86 and the second layer contact via structure 86 and the lower conductive layer 146 located in the passive alternating stack 303, one of the first layer contact via structure 86 and the second layer contact via structure 86 can be electrically connected to the output node (e.g., word line switching transistor 702A) of the upper layer word line driving circuit 730. If a pair of lower layer conductive layers 146 located in different memory array regions 100 and at the same level are not electrically connected to each other, such lower conductive layers 146 can be independently driven by two different lower layer word line driving circuits (711, 712).

[0197] Referring to all the drawings and in accordance with various embodiments of the present disclosure, a first layer contact via structure 86 and a second layer contact via structure 86 can be formed such that a conductive path 886 is provided. The conductive path 886 includes a first first-layer conductive layer (146, 246, or 346) within a first active first-layer alternating stack (101 or 101'), a first second-layer conductive layer (246, 346, or 146) within a passive alternating stack (203 or 303), a second first-layer conductive layer (146, 246, or 346) within a second active first-layer alternating stack (102 or 102'), the first layer contact via structure 86, and the second layer contact via structure 86. The first layer contact via structure 86 contacts the first first-layer conductive layer (146, 246, or 346) and a first portion of the first second-layer conductive layer (246, 346, or 146) within the passive alternating stack (203 or 303). The second layer contact via structure 86 contacts the second first-layer conductive layer (146, 246, or 346) and a second portion of the first second-layer conductive layer (246, 346, or 146) within the passive alternating stack (203 or 303).

[0198] According to one aspect of the present disclosure, a memory device is provided, the memory device comprising: a first layer structure including a first first-layer alternating stack (101 or 101') and a second first-layer alternating stack (102 or 102'), wherein each of the first first-layer alternating stack (101 or 101') and the second first-layer alternating stack (102 or 102') includes a respective vertical alternating sequence of a first-layer insulating layer (132, 232 or 332) and a first-layer conductive layer (146, 246 or 346); a second layer structure overlying or underlying the first layer structure and including a first second-layer alternating stack (201 or 201') and a second second-layer alternating stack (202 or 202') laterally spaced apart from each other by a jumper alternating stack (203 or 303), wherein each of the first second-layer alternating stack (201 or 201'), the second second-layer alternating stack (202 or 202'), and the jumper alternating stack (203 or 303) includes a respective vertical alternating sequence of a second-layer insulating layer (232, 332 or 132) and a second-layer conductive layer (246, 346 or 146); a first memory stack structure 55 (located in the first memory opening filling structure 58) vertically extending through the first first-layer alternating stack (101 or 101') and the first second-layer alternating stack (201 or 201'); a second memory stack structure 55 (located in the second memory opening filling structure 58) vertically extending through the second first-layer alternating stack (102 or 102') and the second second-layer alternating stack (202 or 202'), wherein each of the first memory stack structure 55 and the second memory stack structure 55 includes a respective vertical semiconductor channel 60 and a respective set of memory elements (e.g., memory cells, such as portions of the charge storage layer 54) at levels of the first-layer conductive layer (146, 246 or 346) and the second-layer conductive layer (246, 346 or 146);and a conductive path 886, which includes a first first-layer conductive layer (146, 246, or 346) within a first first-layer alternating stack (101 or 101'), a first second-layer conductive layer (246, 346, or 146) within a jumper alternating stack (203 or 303), a second first-layer conductive layer (146, 246, or 346) within a second first-layer alternating stack (102 or 102'), a first-layer contact via structure 86, and a second-layer contact via structure 86. The first-layer contact via structure contacts the first first-layer conductive layer (146, 246, or 346) and a first portion of the first second-layer conductive layer (246, 346, or 146) within the jumper alternating stack (203 or 303). The second-layer contact via structure contacts the second first-layer conductive layer (146, 246, or 346) and a second portion of the first second-layer conductive layer (246, 346, or 146) within the jumper alternating stack (203 or 303).;

[0199] In one embodiment, the jumper alternating stack (203, 303) includes a passive alternating stack that lacks memory elements for storing data. The passive alternating stack lacks the memory stack structure 55; and the first first-layer alternating stack, the second first-layer alternating stack, the first second-layer alternating stack, and the second second-layer alternating stack include active alternating stacks.

[0200] In one embodiment, the first-layer contact via structure 86 extends vertically from a horizontal plane of the bottommost surface of a combination including the first first-layer alternating stack (101 or 101') and the first second-layer alternating stack (201 or 201') to a horizontal plane of the topmost surface of a combination including the first first-layer alternating stack (101 or 101') and the first second-layer alternating stack (201 or 201').

[0201] In one embodiment, the first-layer contact via structure 86 is electrically isolated from each first-layer conductive layer (146, 246, or 346) within the first first-layer alternating stack (101 or 101') other than the first first-layer conductive layer (146, 246, or 346).

[0202] In one embodiment, the first-layer contact via structure 86 is electrically isolated from each second-layer conductive layer (246, 346, or 146) within the passive alternating stack (203 or 303) other than the first second-layer conductive layer (246, 346, or 146) within the passive alternating stack (203 or 303).

[0203] In one embodiment, the first-level contact via structure 86 includes: a conductive pillar portion 86C that extends vertically through a subset of the layers within the first first-level alternating stack (101 or 101') and through a subset of the layers within the passive alternating stack (203 or 303); a first conductive fin portion 86F that projects laterally from the conductive pillar portion 86C and contacts an annular top surface section of the first first-level conductive layer (146, 246, or 346); and a second conductive fin portion 86F that projects laterally from the conductive pillar portion 86C and contacts an annular top surface section of a first portion of the second first-level conductive layer (246, 346, or 146) within the passive alternating stack (203 or 303).

[0204] In one embodiment, the memory device includes: a first annular insulating plate 40 that laterally surrounds the conductive pillar portion 86C and is located at the level of a subset of the first-level conductive layers (146, 246, or 346) within the first first-level alternating stack (101 or 101') and is laterally surrounded by the subset of the first-level conductive layers within the first first-level alternating stack; and a second annular insulating plate 40 that laterally surrounds the conductive pillar portion 86C and is located at the level of a subset of the second-level conductive layers (246, 346, or 146) within the passive alternating stack (203 or 303) and is laterally surrounded by the subset of the second-level conductive layers within the passive alternating stack.

[0205] In one embodiment, the memory device includes: a first stack of a first insulating pad (152, 252, or 352) and a first dielectric fill material layer (174, 274, 374) that overlies the first conductive fin portion 86F and contacts a first cylindrical surface section of the first conductive fin portion 86F; and a second stack of a second insulating pad (252, 352, 152) and a second dielectric fill material layer (274, 374, 174) that overlies the second conductive fin portion 86F and contacts a second cylindrical surface section of the second conductive fin portion 86F.

[0206] In one embodiment, a first first-layer alternating stack (101 or 101') and a second first-layer alternating stack (102 or 102') are laterally spaced apart from each other by a first lateral spacing (LS1 or LS1') along a first horizontal direction hd1; a first second-layer alternating stack (201 or 201') and a second second-layer alternating stack (202 or 202') are laterally spaced apart from each other by a second lateral spacing (LS2 or LS2') along the first horizontal direction hd1, the second lateral spacing being greater than the first lateral spacing (LS1 or LS1'); and the passive alternating stack (203 or 303) has a lateral extent along the first horizontal direction hd1 that is less than the second lateral spacing (LS2 or LS2').

[0207] In one embodiment, the first first-layer alternating stack (101 or 101') and the second first-layer alternating stack (102 or 102') are laterally spaced apart from each other by a first lateral spacing (LS1 or LS1') along a first horizontal direction hd1; the first second-layer alternating stack (201 or 201') and the second second-layer alternating stack (202 or 202') are laterally spaced apart from each other by a second lateral spacing (LS2 or LS2') along the first horizontal direction hd1, the second lateral spacing being greater than the first lateral spacing (LS1 or LS1'); and the passive alternating stack (203 or 303) has a lateral extent along the first horizontal direction hd1 that is less than the second lateral spacing (LS2 or LS2').

[0208] In one embodiment, the passive alternating stack (203 or 303) includes a first set of stepped surfaces and a second set of stepped surfaces that are laterally spaced apart from each other; the first set of stepped surfaces has an area overlap with the first first-layer alternating stack (101 or 101') in a plan view; and the second set of stepped surfaces has an area overlap with the second first-layer alternating stack (102 or 102') in a plan view.

[0209] In one embodiment, a memory includes a word line driving circuit (710, 720, or 730) configured to apply a word line bias voltage to a first first-layer conductive layer (246, 346, or 146) within the first first-layer alternating stack (101 or 101') and to a second first-layer conductive layer (146, 246, or 346) within the second first-layer alternating stack (102 or 102') through a combination of a first layer contact via structure 86, a second layer contact via structure 86, and a first second-layer conductive layer (146, 246, or 346) within the passive alternating stack (203 or 303).

[0210] In one embodiment, the first layer contact via structure 86 is electrically connected to the word line driving circuit (710, 720, or 730) through the first word line switching transistor (702A or 702B); and the second layer contact via structure 86 is electrically connected to the word line driving circuit (710, 720, or 730) through the first word line switching transistor (702A or 702B), the first and second layer conductive layers in the passive alternating stack, and the first first layer conductive layer.

[0211] Although the foregoing relates to specific preferred embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art can envision various modifications to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed between all embodiments that are not mutually alternative. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of" or "consisting of" replace the words "comprising" or "including". In cases where embodiments employing a specific structure and / or configuration are illustrated in the present disclosure, it should be understood that the present disclosure can be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise known to be impossible for those of ordinary skill in the art. All publications, patent applications, and patents cited herein are hereby incorporated by reference in their entirety.

Claims

1. A memory device, the memory device comprising: A first layer structure, the first layer structure comprising a first first-layer alternating stack and a second first-layer alternating stack, wherein each of the first first-layer alternating stack and the second first-layer alternating stack comprises a respective vertical alternating sequence of a first-layer insulating layer and a first-layer conductive layer; A second layer structure, the second layer structure overlying or underlying the first layer structure and comprising a first second-layer alternating stack and a second second-layer alternating stack that are laterally spaced apart from each other by jumper alternating stacks, wherein each of the first second-layer alternating stack, the second second-layer alternating stack, and the jumper alternating stack comprises a respective vertical alternating sequence of a second-layer insulating layer and a second-layer conductive layer; A first memory stack structure, the first memory stack structure extending vertically through the first first-layer alternating stack and the first second-layer alternating stack; A second memory stack structure, the second memory stack structure extending vertically through the second first-layer alternating stack and the second second-layer alternating stack, wherein each of the first memory stack structure and the second memory stack structure comprises a respective vertical semiconductor channel and a respective set of memory elements located at levels of the first-layer conductive layer and the second-layer conductive layer; And A conductive path, the conductive path comprising a first first-layer conductive layer within the first first-layer alternating stack, a first second-layer conductive layer within the jumper alternating stack, a second first-layer conductive layer within the second first-layer alternating stack, a first-layer contact via structure, and a second-layer contact via structure, the first-layer contact via structure contacting the first first-layer conductive layer and a first portion of the first second-layer conductive layer within the jumper alternating stack, and the second-layer contact via structure contacting the second first-layer conductive layer and a second portion of the first second-layer conductive layer within the jumper alternating stack.

2. The memory device according to claim 1, wherein the jumper alternating stack comprises a passive alternating stack that lacks the memory elements for storing data.

3. The memory device according to claim 2, wherein: The passive alternating stack lacks the memory stack structure; and The first first-layer alternating stack, the second first-layer alternating stack, the first second-layer alternating stack, and the second second-layer alternating stack comprise active alternating stacks.

4. The memory device according to claim 2, wherein the first-layer contact via structure extends vertically from a horizontal plane of a bottommost surface of a combination comprising the first first-layer alternating stack and the first second-layer alternating stack to a horizontal plane of a topmost surface of the combination comprising the first first-layer alternating stack and the first second-layer alternating stack.

5. The memory device according to claim 2, wherein the first-layer contact via structure is electrically isolated from each of the first-layer conductive layers within the first first-layer alternating stack other than the first first-layer conductive layer.

6. The memory device according to claim 2, wherein the first layer contact via structure is electrically isolated from each of the second layer conductive layers in the passive alternating stack other than the first and second layer conductive layers in the passive alternating stack.

7. The memory device according to claim 2, wherein the first layer contact via structure comprises: a conductive pillar portion that vertically extends through a subset of the layers in the first first layer alternating stack and through a subset of the layers in the passive alternating stack; a first conductive fin portion that laterally protrudes from the conductive pillar portion and contacts an annular top surface section of the first first layer conductive layer; and a second conductive fin portion that laterally protrudes from the conductive pillar portion and contacts an annular top surface section of the first portion of the first and second layer conductive layer in the passive alternating stack.

8. The memory device according to claim 7, the memory device further comprising: a first annular insulating plate that laterally surrounds the conductive pillar portion and is located at the level of the subset of the first layer conductive layers in the first first layer alternating stack and is laterally surrounded by the subset of the first layer conductive layers in the first first layer alternating stack; and a second annular insulating plate that laterally surrounds the conductive pillar portion and is located at the level of the subset of the second layer conductive layers in the passive alternating stack and is laterally surrounded by the subset of the second layer conductive layers in the passive alternating stack.

9. The memory device according to claim 8, the memory device further comprising: a first stack of a first insulating liner and a first layer of dielectric filling material that overlies the first conductive fin portion and contacts a first cylindrical surface section of the conductive fin portion; and a second stack of a second insulating liner and a second layer of dielectric filling material that overlies the second conductive fin portion and contacts a second cylindrical surface section of the conductive fin portion.

10. The memory device according to claim 2, wherein: the first layer structure and the second layer structure overlie a substrate; and the first first layer alternating stack includes a first stepped surface such that the first layer conductive layers in the first first layer alternating stack have a first variable lateral extent that decreases with the vertical distance from the substrate.

11. The memory device according to claim 10, wherein: the passive alternating stack includes a second stepped surface such that the second layer conductive layers in the passive alternating stack have a second variable lateral extent that decreases with the vertical distance from the substrate; and the layer contact via structure vertically extends through the first stepped surface and through the second stepped surface.

12. The memory device according to claim 2, wherein: the first first layer alternating stack and the second first layer alternating stack are laterally spaced apart from each other in a first horizontal direction by a first lateral spacing; The first second-layer alternating stack and the second second-layer alternating stack are laterally spaced apart from each other by a second lateral spacing along the first horizontal direction, and the second lateral spacing is greater than the first lateral spacing; The passive alternating stack has a lateral extent along the first horizontal direction, and the lateral extent is less than the second lateral spacing; The passive alternating stack includes a first set of stepped surfaces and a second set of stepped surfaces that are laterally spaced apart from each other; The first set of stepped surfaces has an area overlap with the first first-layer alternating stack in a plan view; and The second set of stepped surfaces has an area overlap with the second first-layer alternating stack in the plan view.

13. The memory device according to claim 2, the memory device further comprising: A word line driving circuit configured to apply a word line bias voltage to the first first-layer conductive layer within the first first-layer alternating stack and to the second first-layer conductive layer within the second first-layer alternating stack through a combination of the first-layer contact via structure, the second-layer contact via structure, and the first second-layer conductive layer within the passive alternating stack.

14. The memory device according to claim 13, wherein: The first-layer contact via structure is electrically connected to the word line driving circuit through a first word line switching transistor; and The second-layer contact via structure is electrically connected to the word line driving circuit through the first word line switching transistor, the first second-layer conductive layer within the passive alternating stack, and the first first-layer conductive layer.

15. A method of forming a memory device, the method comprising: Forming a first-layer structure over a substrate, the first-layer structure including a first first-layer alternating stack and a second first-layer alternating stack, wherein each of the first first-layer alternating stack and the second first-layer alternating stack includes a respective vertical alternating sequence of a first-layer insulating layer and a first-layer conductive layer; Forming a second-layer structure over the substrate, the second-layer structure including a first second-layer alternating stack and a second second-layer alternating stack that are laterally spaced apart from each other by a jumper alternating stack, wherein each of the first second-layer alternating stack, the second second-layer alternating stack, and the jumper alternating stack includes a respective vertical alternating sequence of a second-layer insulating layer and a second-layer conductive layer, and wherein the second-layer structure is formed above or below the first-layer structure; Forming a first memory stack structure that vertically extends through the first first-layer alternating stack and the first second-layer alternating stack; Forming a second memory stack structure that vertically extends through the second first-layer alternating stack and the second second-layer alternating stack, wherein each of the first memory stack structure and the second memory stack structure includes a respective vertical semiconductor channel and a respective set of memory elements located at levels of the first-layer conductive layer and the second-layer conductive layer; Form a first layer contact via structure and a second layer contact via structure, thereby providing a conductive path, the conductive path including a first first layer conductive layer within the first first layer alternating stack, a first second layer conductive layer within the jumper alternating stack, a second first layer conductive layer within the second first layer alternating stack, the first layer contact via structure, and the second layer contact via structure, wherein: The first layer contact via structure contacts the first first layer conductive layer and a first portion of the first second layer conductive layer within the jumper alternating stack; And The second layer contact via structure contacts the second first layer conductive layer and a second portion of the first second layer conductive layer within the jumper alternating stack.

16. The method according to claim 15, wherein The jumper alternating stack includes a passive alternating stack that lacks the memory elements for storing data; and The first layer contact via structure is formed on a circular top surface section of the first first layer conductive layer and on a circular top surface section of the first portion of the first second layer conductive layer within the passive alternating stack.

17. The method according to claim 16, wherein: The first first layer alternating stack includes a first stepped surface such that a lateral extent of the first layer conductive layer within the first first layer alternating stack decreases with a vertical distance from the substrate; The passive alternating stack includes a second stepped surface such that a lateral extent of the second layer conductive layer within the passive alternating stack decreases with the vertical distance from the substrate; and The first layer contact via structure is directly formed on a horizontal extending surface of the first stepped surface and directly formed on a horizontal extending surface of the second stepped surface.

18. The method according to claim 16, the method further comprising: Forming a sacrificial fin cavity fill material structure through the first layer structure and the second layer structure, wherein the sacrificial fin cavity fill material structure is laterally surrounded by a first annular insulating plate at a level of a subset of the first layer conductive layers within the first first layer alternating stack, and is laterally surrounded by a second annular insulating plate at a level of a subset of the second layer conductive layers within the passive alternating stack; And Replacing the sacrificial fin cavity fill material structure with the first layer contact via structure.

19. The method according to claim 16, wherein: The first first layer alternating stack and the second first layer alternating stack are laterally spaced apart from each other in a first horizontal direction by a first lateral spacing; The first second layer alternating stack and the second second layer alternating stack are laterally spaced apart from each other in the first horizontal direction by a second lateral spacing, the second lateral spacing being greater than the first lateral spacing; and The passive alternating stack has a lateral extent in the first horizontal direction, the lateral extent being less than the second lateral spacing.

20. The method according to claim 16, the method further comprising: Electrically connect a word line driving circuit to one of the first layer contact via structures and the second layer contact via structures, wherein the word line driving circuit is configured to apply a word line bias voltage to the first first layer conductive layer within the first first layer alternating stack and to the second first layer conductive layer within the second first layer alternating stack through a combination of a first word line switching transistor electrically connected to the first layer contact via structure, the second layer contact via structure, and the first and second layer conductive layers within the passive alternating stack.

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