MEMORY DEVICE COMPRISING A FeFET MEMORY CELL LAYER AND A

Abstract

Some embodiments include devices and methods of forming the devices. One of the devices includes an electrical structure; a ferroelectric portion surrounding the conductive structure; a charge storage structure surrounding the ferroelectric portion; a dielectric portion surrounding the charge storage structure; a semiconductor portion surrounding the dielectric portion; a first additional conductive structure adjacent a first side of the semiconductor portion; and a second additional conductive structure adjacent a second side of the semiconductor portion, where a direction from the first additional conductive structure to the second additional conductive structure is perpendicular to a direction of a length of the conductive structure.

Description

[0001] Priority Application

[0002] This application claims the benefit of priority of U.S. Provisional Application No. 63 / 429,817, filed on Dec. 2, 2022, which is hereby incorporated by reference in its entirety. Background Art

[0003] A ferroelectric field-effect transistor (FeFET) is a type of transistor in which the gate dielectric is formed of a ferroelectric material rather than conventional silicon dioxide. Many conventional FeFET structures are available. However, some FeFET structures still face one or more challenges associated with operating voltage, parasitic capacitance between word lines and bit lines, and reliability. Brief Description of the Drawings

[0004] Figure 1 、 Figure 2 and Figure 3 show different views of a device in the form of a memory device including FeFET memory cells according to some embodiments described herein.

[0005] Figure 4A and Figures 4B to 10A and Figure 10B show different views of elements during the process of forming a memory device of Figure 1 、 Figure 2 and Figure 3 according to some embodiments described herein. Detailed Description

[0006] The memory devices described herein relate to FeFET memory devices having a layer of FeFET memory cells. The layers are positioned (e.g., stacked) one above the other over a substrate (e.g., a semiconductor substrate) of the memory device. The described memory device includes vertical conductive structures (e.g., pillars) extending through the layers. The vertical conductive structures are part of access lines (e.g., word lines) and can form control gates (e.g., vertical control gates) of FeFETs in memory cells positioned along the length of the vertical conductive structures. The described memory device also includes horizontal conductive structures that are part of data lines (e.g., bit lines) of the memory device. Improvements and benefits of the described memory device include relatively low operating voltage, low parasitic capacitance between word lines and data lines, and improved durability. Other improvements and benefits of the described memory device and its variations are discussed below with reference to Figures 1 to 10B .

[0007] Figure 1 shows a device in the form of a memory device 100 including memory cells according to some embodiments described herein.Figure 1 FIG. 1 shows a top view (e.g., a plan view) of the memory device 100 in the X-Y direction. Figure 2 FIG. 2 shows the memory device 100 along Figure 1 a side view (e.g., a cross-section) in the X-Z direction along line 2-2. Figure 3 FIG. 3 shows the memory device 100 along Figure 1 a side view (e.g., another cross-section) in the Y-Z direction along line 3-3. As Figure 1 , Figure 2 and Figure 3 shown, the memory device 100 may include memory cells 101 to 114. The memory cells of the memory device 100 (e.g., memory cells 101 to 114) may include the structure of FeFETs. As Figure 1 , Figure 2 and Figure 3 shown, the memory cells of the memory device 100 (e.g., memory cells 101 to 114) may be formed (e.g., arranged) in three dimensions including the X direction, the Y direction, and the Z direction (e.g., the vertical direction). Thus, the memory device 100 may be referred to as a 3D (three-dimensional) FeFET memory device.

[0008] The following description refers to Figure 1 , Figure 2 and Figure 3 . Figure 1 FIG. 4 shows a top view of layer 162 (one layer) of the memory device 100 including memory cells 101 to 109 positioned (e.g., formed) in the X-Y direction. Figure 2 and Figure 3 FIG. 5 show two layers 161 and 162 positioned (e.g., stacked) one above the other in the Z direction. The memory device 100 may include a number of memory cell layers (e.g., up to one hundred layers or more than one hundred layers). For simplicity, only two of the layers of the memory device 100 are shown in Figure 2 and Figure 3 . The other layers of the memory device 100 have elements similar (or identical) to the elements of layers 161 and 162.

[0009] For simplicity, the detailed description of the same elements of the memory device 100 is not repeated in the description herein (e.g., Figures 1 to 10B ). Also for simplicity and ease of viewing, from Figure 1 , Figure 2 and Figure 3Cross-sectional lines (e.g., hatching) are omitted from most of the elements shown in the other figures described herein. Some elements of the memory device 100 may be omitted from a particular figure of the drawings so as not to obscure the description of the element(s) being described in that particular figure. The dimensions (e.g., physical structure) of the elements shown in the figures described herein are not drawn to scale.

[0010] As Figure 2 and Figure 3 shown, the memory device 100 may include a substrate 199, and memory cells and other elements of the memory device 100 are positioned (e.g., formed) above the substrate 199. The substrate 199 may include a semiconductor (e.g., silicon) substrate or other types of substrates (e.g., dielectric substrates).

[0011] As Figure 1 , Figure 2 and Figure 3 shown, the memory device 100 may include a conductive structure 121 that extends in a length in the Z direction through a layer plane. Example materials for the conductive structure 121 include metal, doped polysilicon, or other conductive materials. Thus, as Figure 1 , Figure 2 and Figure 3 shown, each of the conductive structures 121 may have a length in the Z direction. The Z direction (e.g., the vertical direction) is a direction perpendicular to the substrate 199 (e.g., outward from the substrate 199). The Z direction is also perpendicular to the X direction ( Figure 2 )(e.g., extending vertically from the X direction) and perpendicular to the Y direction ( Figure 3 ). The X direction and the Y direction ( Figure 1 ) are perpendicular to each other. As Figure 1 , Figure 2 and Figure 3 shown, each conductive structure 121 may be a pillar structure (e.g., a conductive pillar) having a circular (or quasi-circular) cross-section, as Figure 1 shown.

[0012] The conductive structure 121 can be a part of an access line (e.g., a word line) that can be used to control access to corresponding memory cells of the memory device 100. Each conductive structure 121 can be associated with corresponding memory cells in different levels (in the Z direction), such that the memory cells in different levels can share a corresponding conductive structure among the conductive structures 121. Each conductive structure 121 can form a part of a gate (e.g., a control gate) of a transistor (e.g., a FeFET) of the memory cells of the memory device 100. Thus, the memory cells in different levels (FeFETs in different levels) can share a control gate (e.g., a vertical control gate) that is a specific conductive structure 121. The memory cells in different levels (FeFETs in different levels) can be controlled by the same signal (e.g., a word line signal) applied to the shared conductive structure 121 (e.g., the shared vertical control gate).

[0013] As Figure 1 shown, the memory device 100 can include conductive structures 131S, 131D, 132S, 132D, 133S, and 133D. Example materials for the conductive structures 131S, 131D, 132S, 132D, 133S, and 133D include metals, doped polysilicon, or other conductive materials. As Figure 1 shown, each of the conductive structures 131S, 131D, 132S, 132D, 133S, and 133D can have a length in the Y direction, which is perpendicular to the direction (Z direction) of the length of the conductive structure 121. As Figure 2 and Figure 3 shown, the direction from one level to another level of the memory device 100 (e.g., from level 161 to level 162) is parallel to the Z direction (e.g., the vertical direction) and parallel to the length of the conductive structure 121. Thus, the length of each of the conductive structures 131S, 131D, 132S, 132D, 133S, and 133D is also perpendicular to the direction from one level to another level of the memory device 100 (e.g., from level 161 to level 162).

[0014] The conductive structures 131S, 131D, 132S, 132D, 133S, and 133D can be parts of data lines of the memory device 100. The data lines (which include the conductive structures 131S, 131D, 132S, 132D, 133S, and 133D) can include bit lines (or also referred to as digital lines). The memory device 100 can use the data lines (which include the conductive structures 131S, 131D, 132S, 132D, 133S, and 133D) to read information (e.g., during a read operation) from the memory cells of the memory device 100 (e.g., memory cells 101 to 114).

[0015] As Figure 1As shown, each of the conductive structures 131S, 131D, 132S, 132D, 133S, and 133D can be adjacent to (e.g., can contact) a portion of the corresponding memory cell in the Y direction on the same layer (e.g., layer 162 as shown in Figure 1 ). For example, the conductive structure 131S can be adjacent to (e.g., can contact) one side of the semiconductor portion 125 (described below) of each of the memory cells 101, 104, and 107 (e.g., the left side with respect to the view of Figure 1 ). In another example, the conductive structure 131D can be adjacent to (e.g., can contact) one side of the semiconductor portion 125 of each of the memory cells 101, 104, and 107 (e.g., the right side with respect to the view of Figure 1 ).

[0016] In a similar arrangement, the semiconductor portion 125 of each of the other memory cells of the memory device 100 can also be adjacent to two corresponding conductive structures and be in electrical contact with the two corresponding conductive structures. As shown in Figure 1 , the semiconductor portions 125 of the memory cells 102, 105, and 108 can be adjacent to the conductive structures 132S and 132D and be in electrical contact with the conductive structures 132S and 132D. The semiconductor portions 125 of the memory cells 103, 106, and 109 can be adjacent to the conductive structures 133S and 133D and be in electrical contact with the conductive structures 133S and 133D.

[0017] A portion of each conductive structure 121 can form a portion of the source or drain of a transistor (e.g., FeFET) of a memory cell of the memory device 100. For example, a portion of the conductive structure 131S can form the source (or a portion of the source) of a transistor (e.g., FeFET) of each of the memory cells 101, 104, and 107. A portion of the conductive structure 131D can form the drain (or a portion of the drain) of a transistor (e.g., FeFET) of each of the memory cells 101, 104, and 107. In the description herein, the source and drain of a transistor can be used interchangeably.

[0018] Similarly, the conductive structures 132S and 132D can respectively form the source and drain of a transistor (e.g., FeFET) of each of the memory cells 102, 105, and 108. The conductive structures 133S and 133D can respectively form the source and drain of a transistor (e.g., FeFET) of each of the memory cells 103, 106, and 109.

[0019] As shown in Figure 1As shown, the memory device 100 may include a dielectric structure 141, which may include a dielectric material (e.g., silicon dioxide). Each dielectric structure 141 may be positioned (e.g., formed) between two of the conductive structures 131S, 131D, 132S, 132D, 133S, and 133D and have sides (e.g., left and right sides) adjacent to (e.g., in contact with) the two in the X direction to separate (electrically separate) the two of the conductive structures.

[0020] As Figure 1 shown, the direction from one side to the other side of the semiconductor portion 125 in the X direction (e.g., from left to right) is perpendicular to the direction from one side to the other side of the semiconductor portion 125 in the Y direction (e.g., from top to bottom). As Figure 1 shown, the conductive structures 132S and 132D may be separated from each other by corresponding portions of the dielectric material 151 (in the X direction), which are adjacent to the corresponding sides of the semiconductor portion 125 in the Y direction (e.g., with respect to Figure 1 the top and bottom sides of the view). The dielectric material 151 may include silicon dioxide.

[0021] Different levels (e.g., Figure 2 and Figure 3 the levels 161 and 162 in) of the memory device 100 may have conductive structures of different data lines. As Figure 2 shown, the memory device 100 may include conductive structures 134S, 134D, 135S, 135D, 136S, and 136D located in level 161. Memory cells of different levels (e.g., levels 161 and 162) may not share data lines. Thus, the conductive structures of the data lines in one level (e.g., level 161) are electrically separated from the conductive structures of the data lines in another level (e.g., level 162). For example, the conductive structures 131S, 131D, 132S, 132D, 133S, and 133D are electrically separated from the conductive structures 134S, 134D, 135S, 135D, 136S, and 136D.

[0022] The conductive structures 134S, 134D, 135S, 135D, 136S, and 136D may have the same conductive material as the conductive structures 131S, 131D, 132S, 132D, 133S, and 133D. As Figure 2 and Figure 3 shown, each of the conductive structures 134S, 134D, 135S, 135D, 136S, and 136D may be adjacent to (e.g., in contact with) a portion of the corresponding memory cell of level 161. For example, the conductive structure 134D (in Figure 3The semiconductor portion 125 (not labeled) can be adjacent to and in electrical contact with one side of memory cells 110, 113, and 114 (partially shown in Figure 3 ). In another example, the conductive structure 131D (partially shown in Figure 2 ) can be adjacent to and in electrical contact with one side of the semiconductor portion 125 (not labeled) of memory cells 101, 104, and 107. In another example, Figure 2 the conductive structures 135S and 135D in

[0023] can be adjacent to the respective sides of the semiconductor portion 125 (not labeled) of memory cell 111. Figure 1 、 Figure 2 and Figure 3 The following description is of a portion of memory cell 101 of memory device 100 in Figure 1 . Other memory cells have similar or identical structures. Figure 2 shows a top view of memory cell 101 in the X-Y direction. Figure 1 shows a side view (e.g., cross-section) of memory cell 101 in the X-Z direction along line 2-2 of Figure 3 . Figure 1 shows a side view (e.g., another cross-section) of memory cell 101 in the Y-Z direction along line 3-3 of

[0024] As shown in Figure 1 , memory cell 101 can include a ferroelectric portion 122 having an annular shape (e.g., a toroidal structure). As shown in the top view in Figure 1 , the ferroelectric portion 122 surrounds a portion of the conductive structure 121 (e.g., the portion at level 162). The ferroelectric portion 122 includes a ferroelectric material or another type of material. The ferroelectric portion 122 can alternatively include a combination of films (e.g., a film sandwich).

[0025] Memory cell 101 ( Figure 1 ) can include a charge storage structure 123 having an annular shape (e.g., a toroidal structure) with a diameter larger than the diameter of the ferroelectric portion 122. As shown in Figure 1As shown in the top view of [description omitted], the charge storage structure 123 surrounds the ferroelectric portion 122. The charge storage structure 123 can form the floating gate of a transistor (e.g., a FeFET) of the memory cell 101. A portion of the conductive structure 121 in the layer 162 can form the gate (e.g., the control gate) of the transistor of the memory cell 101. The charge storage structure 123 can include a material capable of storing charge. Example materials for the charge storage structure 123 include polysilicon, metal, or other materials. The material (or materials) of the charge storage structure 123 can be the same as the material (or materials) of the conductive structure 121. Alternatively, the material (or materials) of the charge storage structure 123 can be different from the material (or materials) of the conductive structure 121.

[0026] The memory cell 101 ( Figure 1 ) can include a dielectric portion 124 having an annular shape (e.g., a ring structure) with a diameter larger than the diameter of the charge storage structure 123. As Figure 1 shown in the top view of [description omitted], the dielectric portion 124 surrounds the charge storage structure 123. The dielectric portion 124 can include silicon dioxide, a high-k dielectric material, or other dielectric materials. A high-k dielectric material is a dielectric material having a dielectric constant greater than the dielectric constant of silicon dioxide. The dielectric portion 124 can alternatively include a combination of films (e.g., a sandwich of films).

[0027] The memory cell 101 ( Figure 1 ) can include a semiconductor portion 125 having an annular shape (e.g., a ring structure) with a diameter A larger than the diameter of the dielectric portion 124. As Figure 1 shown in the top view of [description omitted], the semiconductor portion 125 surrounds the dielectric portion 124. The semiconductor portion 125 can include polysilicon (e.g., undoped polysilicon) or other semiconductor materials.

[0028] As Figure 2 and Figure 3 shown, the memory device 100 can include a dielectric material (e.g., a dielectric material layer) 152 adjacent to one side (e.g., Figure 2 and Figure 3 the top side in [description omitted]) of each of the ferroelectric portion 122, the charge storage structure 123, the dielectric portion 124, and the semiconductor portion 125. As Figure 2 and Figure 3 shown, the memory device 100 can also include a dielectric material (e.g., another dielectric material layer) 152 adjacent to one side (e.g., Figure 2 and Figure 3 the bottom side in [description omitted]) of each of the ferroelectric portion 122, the charge storage structure 123, the dielectric portion 124, and the semiconductor portion 125. The dielectric material 152 can include silicon nitride.

[0029] Other memory cells of the memory device 100 have a structure similar to that of the memory cell 101. As Figure 2 and Figure 3 shown, different memory cells may include elements that can surround different portions (in the Z direction). For example, the elements of the memory cell 110 may surround a portion of the conductive structure 121 in the layer 162, and the elements of the memory cell 110 may surround a portion of the conductive structure 121 in the layer 161 ( Figure 2 and Figure 3 ).

[0030] As Figure 2 and Figure 3 shown, the elements of the memory cell that are associated with the same conductive structure 121 (e.g., share the same conductive structure 121) may be separated from each other (e.g., electrically separated) by a dielectric material (e.g., silicon nitride) 152. For example, the ferroelectric portion 122 of the memory cell 101 is separated from the ferroelectric portion 122 of the memory cell 110 by the dielectric material 152. The charge storage structure 123 of the memory cell 101 is separated from the charge storage structure 123 of the memory cell 110 by the dielectric material 152. The dielectric portion 124 of the memory cell 101 is separated from the dielectric portion 124 of the memory cell 110 by the dielectric material 152. The semiconductor portion 125 of the memory cell 101 is separated from the semiconductor portion 125 of the memory cell 110 by the dielectric material 152. Thus, the materials forming the elements of the memory cell that are associated with the same conductive structure 121 are formed discontinuously in the Z direction from one memory cell to another memory cell in the Z direction (e.g., not formed as a single piece of material).

[0031] In operation, information may be stored in the memory cells (e.g., memory cells 101 to 114) of the memory device 100 during a write operation (also referred to as a programming operation). For example, in order to store information in the memory cell 101, a voltage (e.g., a programming voltage) may be applied to the conductive structure 121 associated with the memory cell 101 (e.g., applied to the word line including the conductive structure 121). As described above, the conductive structure 121 forms a part of the gate of the FeFET of the memory cell 101. The value of the voltage in the write operation (applied to the gate of the FeFET) may be based on the value of the information to be stored in the memory cell 101 (e.g., a digital value). The applied voltage may change the polarization state of the ferroelectric portion 122 of the memory cell 101. When reading the memory cell 101, different polarization states may give different read currents between the source and drain of the FeFET of the memory cell 101.

[0032] Information can be read from memory cells 101 to 114 in a read operation. For example, to read the information (e.g., previously stored information) in memory cell 101, a voltage can be applied to conductive structure 121. In the structure of a memory cell (e.g., memory cell 109), current can flow in the X direction (e.g., perpendicular to the length of conductive structure 121) through semiconductor portion 125 between conductive structures 131S and 131D. Memory device 100 can include detection circuitry (not shown) that can operate during a read operation to detect (e.g., sense) a current between data lines associated with a selected memory cell. In this example, the detection circuitry can operate to detect a current between data lines that include conductive structures 131S and 131D, which are coupled to the channel region (e.g., semiconductor portion 125) of the FeFET in memory cell 101 (the selected memory cell in this example). Memory device 100 can also include circuitry (not shown) for translating the value of the detected current into the value of the information stored in memory cell 101 (e.g., “0” or “1”). In the structure of the memory cells of memory device 100, after a read operation is performed on a selected memory cell, the information stored in the selected memory cell (e.g., memory cell 101 in this example) remains stored (e.g., not destroyed) in the selected memory cell.

[0033] Structuring memory device 100 as described above can provide improvements and benefits over some conventional memory devices. For example, memory device 100 can have a relatively low operating voltage, improved (e.g., reduced) parasitic elements with reduced parasitic capacitance between conductive structure 121 (e.g., a word line) and conductive structures 131S, 131D, 132S, 132D, 133S, 133D, 134S, 134D, 135S, 135D, 136S, and 136D (e.g., data lines), and improved durability. Additionally, in the structure of memory device 100 as shown in Figure 1 , Figure 2 and Figure 3 the read signal window can be based primarily on the read current. This can result in a higher read signal window, higher speed, or both.

[0034] Figure 4A and Figures 4B to 10A and Figure 10B show different views of elements during the process of forming memory device 100 according to some embodiments described herein. Figure 4AA side view (e.g., cross-section) of the memory device 100 in the X direction after dielectric materials (dielectric material layers) 151 and 152 are alternately formed over the substrate 199. The dielectric materials 151 and 152 may be formed over the substrate 199 one by one in an interleaved manner such that the dielectric material 151 is interleaved with the dielectric material 152. Figure 4B A top view of the memory device 100 after the dielectric materials 151 and 152 are formed.

[0035] In the following description, different views of the memory device 100 in subsequent processes are based on Figure 4A and Figure 4B views (e.g., side view and top view) of the memory device 100. For example, Figure 5A shows a side view of a portion of the memory device 100 taken along line Figure 5B 5B-5B (e.g., a cross-section line). Figure 5B shows Figure 5A a top view of a portion of the memory device 100. For simplicity, the following description omits the specific views (e.g., side view and top view) of the portions of the memory device 100 that are repeated from one process to the next and the specific cross-section lines.

[0036] Figure 5A and Figure 5B show the memory device 100 after openings (e.g., holes) 521 are formed in the dielectric materials 151 and 152. Forming the openings 521 may include removing (e.g., etching) a portion of the dielectric materials 151 and 152 at the locations of the openings 521. As shown in Figure 5A , forming the openings 521 also exposes the corresponding portions of the dielectric materials 151 and 152 at the openings 521.

[0037] Figure 6A and Figure 6B show the memory device 100 after the recess 601 is formed. Forming the recess 601 may include removing at least a portion of the portion of the dielectric material 151 that is exposed at the opening 521 to form the recess 601 at the location where the dielectric material is removed.

[0038] Figure 7A and Figure 7BFIG. 100 shows the memory device 100 after the memory cells 101-106 (and other memory cells, not shown) of the memory device 100 are formed in the recess 601. Forming the memory cells 101-106 may include (in each recess 601) forming a semiconductor material (e.g., polysilicon) adjacent to the sidewalls (not labeled) of the recess 601. The semiconductor material forms the semiconductor portion 125. Forming the memory cells 101-106 may include forming (in each recess 601) a dielectric material (e.g., silicon dioxide) adjacent to the semiconductor material. The dielectric material forms the dielectric portion 124. Forming the memory cells 101-106 may include forming (in each recess 601) a charge storage material (e.g., polysilicon or other material) adjacent to the dielectric material. The charge storage material forms the charge storage structure 123. Forming the memory cells 101-106 may include forming (in each recess 601) a ferroelectric material adjacent to the charge storage material. The ferroelectric material forms the ferroelectric portion 122. The elements for forming the memory cells 101-106 may be performed in sequence in the order described herein. For example, forming each of the memory cells 101-106 includes forming the semiconductor portion 125, forming the dielectric portion 124 after forming the semiconductor portion 125, forming the charge storage structure 123, and forming the dielectric portion 124, and forming the ferroelectric portion 122 after forming the charge storage structure 123.

[0039] As Figure 7A shown, each memory cell (e.g., memory cell 101) may include a semiconductor portion 125 adjacent to the sidewall of the corresponding recess 601, a dielectric portion 124 adjacent to the semiconductor portion 125, a charge storage structure 123 adjacent to the dielectric portion 124, and a ferroelectric portion 122 adjacent to the dielectric portion 124.

[0040] Figure 8A and Figure 8B FIG. 100 shows the memory device 100 after the conductive structure 121 is formed in the recess 601 and adjacent to the ferroelectric portion 122. Forming the conductive structure 121 may include depositing a conductive material in the recess 601 after forming the ferroelectric portion 122. The conductive material may include a metal, doped polysilicon, or other conductive material.

[0041] Figure 9A and Figure 9B FIG. 100 shows the memory device 100 after forming a trench (e.g., a slot) 941. As Figure 9BAs shown, each trench 941 may have a length in the Y direction, which is a direction perpendicular to the direction from one level of the dielectric material 151 to one level of the dielectric material 152. Forming the trench 941 may include removing a portion of the dielectric materials 151 and 152 between adjacent groups of memory cells in the X direction. For example, as Figure 9A and Figure 9B shown, a trench 941 may be formed between a group including memory cells 101 and 110 and a group including memory cells 102 and 111. In another example, as Figure 9A and Figure 9B shown, a trench 941 may be formed between a group including memory cells 102 and 111 and a group including memory cells 103 and 112.

[0042] The process associated with Figure 9A and Figure 9B may also include removing a portion 151P of the dielectric material 151 to expose a portion (e.g., sidewall) 125W of the semiconductor portion 125 of each of the memory cells 101, 102, 103, 110, 111, and 112 (marked in Figure 10A and Figure 10B ). Exposing the portion 125W (marked in Figure 10A and Figure 10B ) allows for the formation of corresponding conductive structures (e.g., portions of data lines) adjacent to and in electrical contact with the corresponding semiconductor portions 125 of the respective memory cells.

[0043] Figure 10A and Figure 10B show the memory device 100 after the formation of conductive structures 131S, 131D, 132S, 132D, 133S, 133D, 134S, 134D, 135S, 135D, 136S, and 136D adjacent to and in electrical contact with the corresponding semiconductor portions (e.g., channel regions) of the respective memory cells 101, 102, 103, 110, 111, and 112. Figure 10A and Figure 10B also show the memory device 100 after a dielectric structure 141 in the trench 941 between the corresponding conductive structures 131S, 131D, 132S, 132D, 133S, 133D, 134S, 134D, 135S, 135D, 136S, and 136D.

[0044] Reference Figures 4A to 10B to the description of forming the memory device 100 may include other processes for forming a complete memory device (e.g., the memory device 100). Such processes are omitted from the above description to avoid obscuring the subject matter described herein.

[0045] Descriptions of devices (e.g., memory device 100) and methods (e.g., method of forming memory device 100) are intended to provide a general understanding of the structure of various embodiments and are not intended to provide a complete description of all elements and features of the devices that may use the structures described herein. Devices herein refer to, for example, an apparatus (e.g., memory device 100) or a system (e.g., an electronic article that may include memory device 100).

[0046] Reference above Figures 1 to 10B Any of the components described above may be implemented in several ways, including by software simulation. Thus, the device (e.g., memory device 100) or portions of each of these memory devices described above may all be characterized herein as “a plurality of modules” (or “modules”). Such modules may include hardware circuitry, single and / or multi-processor circuitry, memory circuitry, software program modules and objects and / or firmware, and combinations thereof, as desired and / or appropriate for the particular implementation of the various embodiments. For example, such modules may be included in system operation simulation packages, such as software electrical signal simulation packages, power usage and range simulation packages, capacitance-inductance simulation packages, power / heat dissipation simulation packages, signal transmission-reception simulation packages, and / or combinations of software and hardware for operating or simulating the operation of various potential embodiments.

[0047] The memory devices described herein (e.g., memory device 100) may be included in a device (e.g., an electronic circuitry) (e.g., a high-speed computer, communication and signal processing circuitry, a single or multi-processor module, a single or multiple embedded processors, a multi-core processor, a message information switch, and a dedicated module including multi-layer, multi-chip modules). Such devices may further be included as sub-components within a variety of other devices (e.g., electronic systems) (e.g., a television, a cellular phone, a personal computer (e.g., a laptop computer, a desktop computer, a handheld computer, a tablet computer, etc.), a workstation, a radio, a video player, an audio player (e.g., an MP3 (Moving Picture Experts Group, Audio Layer 3) player), a vehicle, a medical device (e.g., a heart monitor, a blood pressure monitor, etc.), a set-top box, etc.).

[0048] Reference above Figures 1 to 10BThe described embodiments include devices and methods of forming the devices. One of the devices includes an electrical structure; a ferroelectric portion surrounding the conductive structure; a charge storage structure surrounding the ferroelectric portion; a dielectric portion surrounding the charge storage structure; a semiconductor portion surrounding the dielectric portion; a first additional conductive structure adjacent to a first side of the semiconductor portion; and a second additional conductive structure adjacent to a second side of the semiconductor portion, wherein a direction from the first additional conductive structure to the second additional conductive structure is perpendicular to a direction of a length of the conductive structure. Other embodiments including additional devices and methods are described.

[0049] In the detailed description and claims, the term "on" used with respect to two or more elements (e.g., materials), such as one "on" another, means at least some contact between the elements (e.g., materials). The term "above" means that the elements (e.g., materials) are extremely close, but may have one or more additional intervening elements (e.g., materials) such that contact is possible but not required. Unless so stated, neither "on" nor "above" implies any directionality as used herein.

[0050] In the detailed description and claims, terms such as "first," "second," and "third" are used only as labels and are not intended to impose numerical requirements on their objects.

[0051] In the detailed description and claims, a list of items joined by the term "at least one of..." can mean any combination of the listed items. For example, if items A and B are listed, then the phrase "at least one of A and B" means only A; only B; or A and B. In another example, if items A, B, and C are listed, then the phrase "at least one of A, B, and C" means only A; only B; only C; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

[0052] In the detailed description and claims, a list of items joined by the term "one of..." can mean only one of the listed items. For example, if items A and B are listed, then the phrase "one of A and B" means only A (excluding B) or only B (excluding A). In another example, if items A, B, and C are listed, then the phrase "one of A, B, and C" means only A; only B; or only C. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

[0053] The foregoing description and drawings illustrate some embodiments of the subject matter of the present invention so that those skilled in the art can practice the embodiments of the subject matter of the present invention. Other embodiments may incorporate structural changes, logical changes, electrical changes, process changes, and other changes. The examples represent only possible variations. Portions and features of some embodiments may be included in those of other embodiments or may replace those of other embodiments. After reading and understanding the foregoing description, those skilled in the art will appreciate many other embodiments.

[0054] Type

Claims

1. An apparatus, comprising: A conductive structure; A ferroelectric portion surrounding the conductive structure; A charge storage structure surrounding the ferroelectric portion; A dielectric portion surrounding the charge storage structure; A semiconductor portion surrounding the dielectric portion; A first additional conductive structure adjacent to a first side of the semiconductor portion; And A second additional conductive structure adjacent to a second side of the semiconductor portion, wherein a direction from the first additional conductive structure to the second additional conductive structure is perpendicular to a direction of a length of the conductive structure.

2. The apparatus according to claim 1, wherein the conductive structure is a part of an access line of the apparatus.

3. The apparatus according to claim 1, wherein the first additional conductive structure is a part of a data line of the apparatus.

4. The apparatus according to claim 1, wherein: The first additional conductive structure and the second additional conductive structure are separated from each other by a first additional dielectric portion adjacent to a third side of the semiconductor portion; The first additional conductive structure and the second additional conductive structure are separated from each other by a second additional dielectric portion adjacent to a fourth side of the semiconductor portion; And A direction from the first side of the semiconductor portion to the second side of the semiconductor portion is perpendicular to a direction from the third side of the semiconductor portion to the fourth side of the semiconductor portion.

5. The apparatus according to claim 1, wherein the semiconductor portion is a part of a transistor of the apparatus, and a part of the first additional conductive structure is a part of a source or a drain of the transistor.

6. The apparatus according to claim 1, wherein the charge storage structure forms a floating gate of a transistor of the apparatus.

7. The apparatus according to claim 1, wherein the semiconductor portion is a part of a channel region of a transistor of the apparatus, and a part of the conductive structure forms a gate of the transistor.

8. The apparatus according to claim 1, wherein the charge storage structure has the same material as the conductive structure.

9. The apparatus according to claim 1, further comprising: A first layer of dielectric material adjacent to a first side of each of the ferroelectric portion, the charge storage structure, the dielectric portion, and the semiconductor portion; And A second layer of dielectric material adjacent to a second side of each of the ferroelectric portion, the charge storage structure, the dielectric portion, and the semiconductor portion.

10. The apparatus according to claim 9, wherein the first layer of dielectric material and the second layer of dielectric material have the same dielectric material.

11. The apparatus according to claim 1, further comprising: A first layer of silicon nitride adjacent to a first side of each of the ferroelectric portion, the charge storage structure, the dielectric portion, and the semiconductor portion; And A second layer of silicon nitride adjacent to a second side of each of the ferroelectric portion, the charge storage structure, the dielectric portion, and the semiconductor portion.

12. An apparatus, comprising: Layers positioned one above the other, each of the layers containing memory cells, the layers including a first layer and a second layer; A first conductive structure extending through the layers; A first memory cell included in the memory cells of the first layer, the first memory cell including: A first ferroelectric portion adjacent to a first portion of the first conductive structure; A first charge storage structure adjacent to the first ferroelectric portion; A first dielectric portion adjacent to the first charge storage structure; And A first semiconductor portion adjacent to the first dielectric portion; A second memory cell included in the memory cells of the second layer of the layers, the second memory cell including: A second ferroelectric portion adjacent to a second portion of the first conductive structure; A second charge storage structure adjacent to the second ferroelectric portion; A second dielectric portion adjacent to the second charge storage structure; And A second semiconductor portion adjacent to the second dielectric portion; A first additional conductive structure located in the first layer and adjacent to a first side of the first semiconductor portion; A second additional conductive structure located in the first layer and adjacent to a second side of the first semiconductor portion; A third additional conductive structure located in the second layer and adjacent to a first side of the second semiconductor portion; And A fourth additional conductive structure located in the second layer and adjacent to a second side of the second semiconductor portion, wherein each of the first additional conductive structure, the second additional conductive structure, the third additional conductive structure, and the fourth additional conductive structure has a length perpendicular to the direction from the first layer to the second layer.

13. The device according to claim 12, wherein the first ferroelectric portion is separated from the second ferroelectric portion by a dielectric material.

14. The device according to claim 12, wherein the first charge storage structure is separated from the second charge storage structure by a dielectric material.

15. The device according to claim 12, wherein the first semiconductor portion is separated from the second semiconductor portion by a dielectric material.

16. The device according to claim 12, further comprising: A dielectric structure including a first side adjacent to the first additional conductive structure and the third additional conductive structure and a second side adjacent to the second additional conductive structure and the fourth additional conductive structure.

17. A method, comprising: Forming interleaved first dielectric material layers and second dielectric material layers; Forming openings through the first dielectric material layers and the second dielectric material layers to expose a portion of the dielectric material layers among the first dielectric material layers and the second dielectric material layers at the openings; Removing at least a portion of the portion of the dielectric material layers to form recesses in the dielectric material layers; And Forming memory cells in the recesses, including: Forming a semiconductor material in the recesses; Forming a dielectric material adjacent to the semiconductor material; Form a charge storage material adjacent to the dielectric material; Form a ferroelectric material adjacent to the charge storage material; and Form a conductive material adjacent to the dielectric material.

18. The method of claim 17, wherein the first dielectric material comprises silicon dioxide and the second dielectric material layer comprises silicon nitride.

19. The method of claim 18, wherein the dielectric material layer is one of the layers of the first dielectric material.

20. The method of claim 17, further comprising: Form an additional conductive material adjacent to the semiconductor material.

21. The method of claim 20, wherein forming the additional conductive material comprises: Removing a portion of the first dielectric material layer and the second dielectric material layer to expose a portion of the semiconductor material; and Forming the additional conductive material such that the additional conductive material contacts the portion of the semiconductor material.

22. The method of claim 21, wherein removing the first dielectric material layer and the second dielectric material layer comprises forming trenches in the first dielectric material layer and the second dielectric material layer.

23. The method of claim 22, wherein the trenches have a length in a direction perpendicular to the direction from one of the first dielectric material layers to one of the second dielectric material layers.

24. A method comprising: Forming alternating first dielectric material layers and second dielectric material layers; Forming a first opening and a second opening through the first dielectric material layers and the second dielectric material layers to expose a first portion of the dielectric material layer among the first dielectric material layers and the second dielectric material layers, and exposing a second portion of the dielectric material layer at the second opening; Removing at least a portion of the first portion to form a first recess in the dielectric material layer, and removing at least a portion of the second portion to form a second recess in the dielectric material layer; Forming a semiconductor material, a dielectric material adjacent to the semiconductor material, a charge storage material adjacent to the dielectric material, a ferroelectric material adjacent to the charge storage material, and a conductive material adjacent to the dielectric material in each of the first recess and the second recess; Removing a portion of the alternating first dielectric material layers and second dielectric material layers to expose a portion of the semiconductor material formed in the first recess and a portion of the semiconductor material formed in the second recess; Forming a first conductive material adjacent to the portion of the semiconductor material in the first recess; and Forming a second conductive material adjacent to the portion of the semiconductor material in the second recess.

25. The method of claim 24, wherein the first dielectric material layer comprises silicon dioxide and the second dielectric material layer comprises silicon nitride.

26. The method according to claim 25, wherein the dielectric material layer is one of the first dielectric material layers.

27. The method according to claim 26, wherein the first conductive material and the second conductive material are formed on the same layer as the dielectric material layer.

28. The method according to claim 24, wherein removing the portions of the first dielectric material layer and the second dielectric material layer that are interleaved includes forming trenches in the portions of the first dielectric material layer and the second dielectric material layer that are interleaved.

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