Manufacturing method of TSV (Through Silicon Via) with horn mouth shape

Abstract

The invention relates to a method for manufacturing a TSV (Through Silicon Via) with a horn mouth shape. The method comprises the following steps: a, manufacturing a first oxide layer on a wafer; b, photoetching a horn mouth pattern on the first oxide layer; c, manufacturing a second oxide layer on the first oxide layer; d, performing photoetching on the second oxide layer to form a TSV window pattern, and performing dry etching to expose the to-be-etched wafer substrate silicon; e, first etching: etching the wafer by adopting a deep silicon etching process to form a TSV deep groove; f, performing BOE wet etching to remove the second oxide layer; g, second etching: etching the horn mouth etching area by adopting an isotropic or near-isotropic etching process with optimized parameters to form a TSV deep groove with a horn mouth shape; and h, removing the first oxide layer by wet etching. The size of the opening of the horn mouth can be freely designed according to requirements, the shape of the horn mouth with the large opening can be achieved, filling holes can be better avoided when the deep groove is filled, a filling process window is larger, and a non-TSV area on the surface of the wafer is protected by the oxide layer and is not damaged in the process.

Description

Technical Field

[0001] The invention belongs to the TSV deep silicon etching method in the field of semiconductor technology, and particularly relates to a manufacturing method of a TSV with a flared shape. Background Art

[0002] MEMS devices are developing towards high integration, miniaturization, multi-function, low power consumption, etc., which urgently requires the TSV (Through-Silicon Via) technology. The TSV technology can achieve electrical vertical interconnection, which can greatly reduce the chip area, reduce the parasitic resistance and capacitance of the leads, and improve the signal transmission rate, etc. It is widely used in advanced technologies such as MEMS device manufacturing and 3D packaging.

[0003] The key technologies for TSV manufacturing include deep trench deep silicon etching and deep trench filling. In MEMS device manufacturing, common deep trench filling includes polysilicon deposition filling, silicon dioxide deposition filling, etc., and usually the LPCVD process is adopted. In the filling process, due to the corner effect of the TSV top film deposition and the slight Bow at the top of the TSV morphology, narrow gaps (bottlenecks) are gradually formed at the TSV opening, and then a seal is formed, resulting in incomplete filling of the TSV, forming filling pores or filling void defects. The defects will cause serious stress problems, poor electrical connection or signal transmission problems, etc., which are very important for process stability and device reliability.

[0004] Avoiding filling voids is an important requirement and a major problem for most TSV filling technologies. There are mainly three solutions: (1) using etching technology to form a TSV opening with a flared shape to avoid narrow gaps in the opening during filling; (2) adding a "re-etching" step during the filling process to eliminate the narrow gaps that have appeared; (3) adopting a special HDPCVD deposition process technology to realize the process of "deposition-etching-deposition-etching-..", avoiding the formation of narrow gaps in the opening. Solution (1) etching to form a flared shape is the most effective solution to avoid filling voids. Solutions (2) and (3) usually also need to be based on solution (1) to obtain better effects. Therefore, the flared shape is a research hotspot and a technical challenge in TSV deep silicon etching.

[0005] In some literature, a two-step etching process is used to fabricate the flared mouth morphology. In the first step, anisotropic deep silicon etching is first used to form TSV deep grooves. By adjusting the etching process parameters, the top of the TSV has a side-etched morphology with sharp corners. In the second step, the etching mask layer is removed, and isotropic etching with optimized parameters is used to remove the side-etched sharp corners, while having less impact on other positions of the TSV. This method requires adjusting unconventional etching process parameters to form a side-etched morphology with sharp corners at the top of the TSV, which is relatively complex. Moreover, the second-step etching will damage the surface of the silicon wafer and is not suitable for the MEMS device process with high surface requirements. Another method is proposed in a patent application. Silicon dioxide is used as the mask for TSV deep silicon etching. After etching, BOE etching solution is used to etch the silicon dioxide mask. Since the solution is isotropic, it will etch the silicon dioxide from the surface and side of the TSV opening simultaneously, thereby exposing the silicon at the TSV opening edge. Then, an isotropic etching menu with optimized parameters is used for etching at the TSV opening to obtain the flared mouth morphology. Due to the limited thickness of the prepared silicon dioxide (usually 2 microns), and a certain thickness of silicon dioxide needs to be retained during etching to ensure that the silicon surface is not damaged in the second-step etching, the maximum distance of the exposed silicon can only be 1 - 2 μm. After the second-step etching, the flared mouth morphology is very limited, and a TSV flared mouth morphology with a large opening cannot be formed. The process window for avoiding filling voids is small, and the method has certain limitations. Summary of the Invention

[0006] The object of the present invention is to provide a method for fabricating a TSV with a flared mouth morphology, and the size of the flared mouth opening can be arbitrarily adjusted according to different requirements to meet the requirements such as no filling voids.

[0007] To achieve the above object, the present invention adopts the following technical solutions, including the following steps: Fabricate the first oxide layer on the wafer: Grow a thin silicon dioxide layer through thermal oxidation process; Pattern the first oxide layer: Photolithography is performed on the first oxide layer to form a flared mouth opening pattern, and the thermal oxide layer in the flared mouth opening area is removed by wet etching or dry etching; Fabricate the second oxide layer on the first oxide layer: Deposit a silicon dioxide thin film using PECVD process; Pattern the second oxide layer: Photolithography is performed on the second oxide layer to form a TSV etching window pattern, and the PECVD oxide layer in the TSV etching area is removed by dry etching to expose the silicon of the wafer substrate to be etched; First etching: Adopt deep silicon etching process to etch a TSV deep groove in the silicon of the wafer substrate through the TSV etching window pattern; Remove the second oxide layer by BOE wet etching to expose the flared mouth etching area of the wafer substrate silicon; Second Etching: Use an isotropic or near-isotropic etching process with optimized parameters to etch the etched area of the silicon flared opening on the wafer substrate, forming a TSV deep groove with a top flared opening morphology; Wet etching is used to remove the first oxide layer.

[0008] In the present invention, the flared opening is formed by patterning the first oxide layer, and the opening size can be freely designed according to requirements. A flared opening morphology with a larger opening can be achieved, which is more conducive to avoiding filling voids during deep groove filling and provides a larger filling process window; the first oxide layer is formed by a thermal oxidation process, and the second oxide layer is formed by a PECVD process. The wet etching rates of BOE are quite different, and the typical rate ratio is about 1:3. The thickness and boundary of the first oxide layer can be effectively controlled when etching and removing the second oxide layer; the non-TSV areas on the wafer surface are protected by the oxide layer during the process and are not damaged. In the present invention, the opening size of the TSV flared opening can be freely designed, with less limitation and wide process applicability, which can meet the complex and diverse application requirements in MEMS device manufacturing and advanced packaging.

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for description in the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. Brief Description of the Drawings

[0010] Figure 1 It is the process flow for manufacturing the TSV with a flared opening morphology described in the present invention; Figure 2 It is the typical relationship between the etching time and etching effect of the flared opening morphology. Detailed Embodiments

[0011] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below in conjunction with the drawings and specific embodiments.

[0012] As Figure 1 shown: Grow a silicon dioxide layer as the first oxide layer with a thickness of 300 nm on a single-crystalline silicon wafer (silicon substrate) through a thermal oxidation process; Lithograph a flared opening pattern on the first oxide layer, which is a circular hole with a diameter of 30 μm; Deposit a silicon dioxide layer as the second oxide layer with a thickness of 2 μm on the first oxide layer using a PECVD process; Second oxide layer patterning: Lithography is used to form the TSV etching window pattern, which is a round hole with a diameter of 10 μm. Dry etching is used to remove the PECVD second oxide layer in the TSV etching area, exposing the substrate silicon to be etched; Deep silicon etching BOSCH process is used to etch the TSV deep hole. The PECVD second oxide layer serves as the etching mask layer, and the etching depth is 200 μm, presenting a V-shaped morphology; after etching, the remaining PECVD silicon dioxide is 700 - 800 nm; The etching rates of BOE wet solution for thermally oxidized silicon dioxide (the first oxide layer) and PECVD silicon dioxide are 100 nm / min and 300 nm / min respectively. This solution is used to etch the remaining 700 - 800 nm PECVD silicon dioxide layer clean. The etching time is 3 min. After etching, the remaining thermally oxidized silicon dioxide layer has a remaining thickness of about 230 nm - 260 nm, exposing the silicon area of the flared opening pattern with an exposed width of 10 μm; An isotropic etching process with a lower rate is adopted. The deep silicon etcher has an isotropic etching rate of about 1 μm / min at a radio frequency power of 1500 W, an SF6 flow rate of 100 sccm, and an O2 flow rate of 50 sccm (process parameters may vary according to the performance of specific deep silicon etcher tools). The top opening area of the TSV is etched to form a flared morphology. The relationship between the etching time and the effect is determined according to process experiments. The typical relationship between the etching time and the etching effect is as Figure 2 shown. The longer the etching time, the larger the flare of the flared morphology. The etching time is determined according to the actual requirements of the flared morphology (as Figure 2 shown, with an etching rate of 1 μm / min and an etching time of 1 - 3 min, the flare of the etched flared morphology gradually increases); due to the isotropic etching with a lower rate, the etching loss of the silicon dioxide mask is less, and a thickness of more than 200 nm is sufficient to protect the wafer surface from damage; The BOE wet solution is used to remove the thermally oxidized silicon dioxide layer.

[0013] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present invention. However, the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A manufacturing method of a trumpet-shaped TSV, characterized in that Including the following steps: a. Fabricate a first oxide layer on the wafer; b. Pattern the first oxide layer: lithographically form a flared opening pattern on the first oxide layer; c. Fabricate a second oxide layer on the first oxide layer; d. Pattern the second oxide layer: lithographically form a TSV etching window pattern on the second oxide layer to expose the silicon of the wafer substrate to be etched; e. First etching: use deep silicon etching process to etch a TSV deep trench in the silicon of the wafer substrate through the TSV etching window pattern; f. Wet-etch the second oxide layer with BOE to expose the flared etching area of the wafer substrate silicon; g. Second etching: use an isotropic or near-isotropic etching process with optimized parameters to etch the flared etching area of the wafer substrate silicon to form a TSV deep trench with a top flared morphology; h. Wet-etch the first oxide layer to remove it.

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