Method for measuring etching rate of semiconductor
The method addresses the inaccuracy of existing etch rate measurements by using reflective spectroscopy on etched semiconductor substrates with different layers to measure etch rate accurately, minimizing crystal damage.
Patent Information
- Application Number
- CN202510465176.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-14
- Publication Date
- 2025-07-15
AI Technical Summary
In the prior art, the method of measuring the etching rate of silicon by a mixed solution of HF and HNO3 cannot accurately reflect the changes in wafer thickness and surface morphology, resulting in inaccurate calculation of etching rate.
The grooves are etched in the semiconductor substrate, and the grooves are filled with a second material layer of different reflection spectra, and the measurement is performed in combination with the reflection spectroscopy method, and the etching rate is obtained by the displacement method.
Accurate measurement of semiconductor etching rate is achieved, and the calculation accuracy of etching rate is improved, especially the accuracy of etching rate measurement at the wafer level.
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Figure CN120313495A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor manufacturing, and relates to a method for measuring the etching rate of a semiconductor. Background Art
[0002] In the process of semiconductor production, it is often necessary to perform a cleaning process on the back surface of a wafer to remove possible particles and metal contamination on the back surface of the wafer. Among them, a mixed solution of HF and HNO3 is often used as the cleaning solution for the cleaning process. This mixed solution has an obvious etching effect on the wafer, especially on the silicon wafer. In the cleaning process, there is a risk of rough contact surface and increased scratches on the back surface of the wafer, and in severe cases, it may cause problems such as wafer breakage. Therefore, when performing a cleaning process on the wafer, it is necessary to accurately understand the etching rate and etching characteristics of the etching solution on the wafer, so as to reasonably control cleaning conditions such as the concentration of the etching solution and the process time, and avoid damaging the wafer.
[0003] Currently, in the measurement of the etching rate of a mixed solution of HF and HNO3 on silicon, the weighing method is generally used, that is, the wafer before the reaction is weighed first, and then the mixed solution of HF and HNO3 is sprayed onto the surface of the wafer to react with silicon. After reacting for a period of time, the wafer is weighed again, and the weight difference between the two times is the part of silicon etched away, so that the etching rate of the mixed solution of HF and HNO3 on silicon can be calculated. However, this method has obvious disadvantages, that is, the decrease in weight cannot accurately reflect the changes in the wafer thickness and surface topography, and the etching rate of the mixed solution of HF and HNO3 on silicon cannot be accurately calculated.
[0004] Therefore, it is necessary to provide a method for measuring the etching rate of a semiconductor. Summary of the Invention
[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for measuring the etching rate of a semiconductor, which is used to solve the problem that it is difficult to accurately measure the etching rate of a semiconductor in the prior art.
[0006] To achieve the above purpose and other related purposes, the present invention provides a method for measuring the etching rate of a semiconductor, including the following steps:
[0007] Provide a semiconductor detection substrate, the semiconductor detection substrate includes a semiconductor substrate and a first material layer formed on the surface of the semiconductor substrate, and the first material layer and the semiconductor substrate have different reflection spectra, and the first material layer has an etching window exposing the semiconductor substrate;
[0008] Etch the semiconductor substrate to form a groove in the semiconductor substrate, and obtain the etching time t;
[0009] Form a second material layer that fills the groove, and the second material layer has a different reflection spectrum from the semiconductor substrate;
[0010] Perform a planarization process so that the first material layer and the second material layer are in the same plane, obtaining a structure to be measured;
[0011] Use reflection spectroscopy to measure the measurement structure, and obtain the thickness H1 of the first material layer and the thickness H2 of the second material layer;
[0012] Perform data processing to obtain the etching rate V of the semiconductor substrate = (H2 - H1) / t.
[0013] Optionally, the method for etching the semiconductor substrate to form the groove includes wet etching or dry etching.
[0014] Optionally, when wet etching is used, the etching solution includes a HF:HNO3 mixed solution, an NH4OH solution, or a TMAH solution.
[0015] Optionally, the method for the planarization process includes one or a combination of mechanical polishing, chemical polishing, or dry etching.
[0016] Optionally, the etching rate of the first material layer is less than the etching rate of the semiconductor substrate.
[0017] Optionally, after the planarization process, the value of the thickness H1 of the first material layer includes 0.
[0018] Optionally, the semiconductor substrate includes a silicon substrate, a glass substrate, a sapphire substrate, or a III-V group semiconductor substrate; the first material layer includes a stack formed by one or a combination of an NDC layer, a silicon oxide layer, or a silicon nitride layer; the second material layer includes an NDC layer, a silicon oxide layer, or a silicon nitride layer.
[0019] Optionally, the semiconductor substrate includes a wafer-level semiconductor substrate, and multiple grooves are formed when etching the semiconductor substrate.
[0020] Optionally, the grooves are arranged periodically in a direction from the center of the wafer to the edge of the wafer.
[0021] Optionally, the distribution morphology formed by combining multiple grooves includes a ring shape, an S shape, or a square shape.
[0022] As described above, in the method for measuring the semiconductor etching rate of the present invention, a groove is etched in a semiconductor substrate, and a second material layer different from the reflection spectrum of the semiconductor substrate is filled in the groove. By using the replacement method, the second material layer is replaced with a part of the semiconductor substrate, so that the etching rate of the semiconductor substrate can be accurately obtained by combining the reflection spectrum method. Further, the measurement method can also be used to measure the etching rate of a semiconductor substrate at the wafer level, so that the etching rate of each region of the wafer can be obtained as needed, thereby further improving the accuracy of the wafer etching rate. Description of the Drawings
[0023] Figure 1 It shows a process flow chart of the measurement of the semiconductor etching rate in an embodiment of the present invention.
[0024] Figure 2 It shows a schematic structural diagram after forming the first material layer in an embodiment of the present invention.
[0025] Figure 3 It shows a schematic structural diagram after forming a patterned photoresist layer in an embodiment of the present invention.
[0026] Figure 4 It shows a schematic structural diagram of a semiconductor detection substrate in an embodiment of the present invention.
[0027] Figure 5 It shows a schematic structural diagram after forming a groove in an embodiment of the present invention.
[0028] Figure 6 It shows a schematic structural diagram after forming the second material layer in an embodiment of the present invention.
[0029] Figure 7 It shows a schematic structural diagram of the measurement structure after planarization processing in an embodiment of the present invention.
[0030] Figure 8 It shows a top-view structural diagram of the measurement structure in which the grooves are annularly distributed in an embodiment of the present invention.
[0031] Figure 9 It shows a top-view structural diagram of the measurement structure in which the grooves are S-shaped distributed in an embodiment of the present invention.
[0032] Figure 10 It shows a top-view structural diagram of the measurement structure in which the grooves are square-shaped distributed in an embodiment of the present invention.
[0033] Description of the Reference Numerals
[0034] 100 Semiconductor Substrate
[0035] 101 Groove
[0036] 200 First Material Layer
[0037] 201 Etching window
[0038] 300 Photoresist layer
[0039] 400 Second material layer Detailed implementation manners
[0040] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0041] When detailing the embodiments of the present invention, for the convenience of description, the cross-sectional views showing the device structure will be locally enlarged in a non-general proportion, and the schematic diagrams are only examples, and they should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.
[0042] For the convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on", etc. may be used herein to describe the relationship between an element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. Embodiments may include those in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.
[0043] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention schematically. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and ratios of the components in actual implementation may be arbitrarily changed, and the component layout type may also be more complex.
[0044] As Figure 1 , this embodiment provides a method for measuring the etching rate of a semiconductor, including the following steps:
[0045] S1: Provide a semiconductor substrate;
[0046] S2: Form a first material layer on the surface of the semiconductor substrate, and the first material layer has a different reflection spectrum from the semiconductor substrate;
[0047] S3: Pattern the first material layer to form an etching window exposing the semiconductor substrate.
[0048] S4: Etch the semiconductor substrate to form a groove in the semiconductor substrate, and obtain the etching time t.
[0049] S5: Form a second material layer filling the groove, and the second material layer has a different reflection spectrum from the semiconductor substrate.
[0050] S6: Perform a planarization process so that the first material layer and the second material layer are in the same plane, and obtain the structure to be measured.
[0051] S7: Use the reflection spectroscopy method to measure the measurement structure, and obtain the thickness H1 of the first material layer and the thickness H2 of the second material layer.
[0052] S8: Perform data processing to obtain the etching rate V of the semiconductor substrate, where V = (H2 - H1) / t.
[0053] Wherein, in another embodiment, as Figure 4 , a semiconductor detection substrate may also be directly provided. The semiconductor detection substrate includes a semiconductor substrate 100 and a first material layer 200 formed on the surface of the semiconductor substrate 100. The first material layer 200 has a different reflection spectrum from the semiconductor substrate 100, and the first material layer 200 has an etching window 201 exposing the semiconductor substrate 100. That is, the semiconductor detection substrate can be directly provided to replace the above steps S1 - S3, and it can be understood that the preparation method of the semiconductor detection substrate is not limited to the above steps S1 - S3, and other process steps can also be used for preparation according to needs.
[0054] In the measurement method of the semiconductor etching rate of this embodiment, by etching the groove in the semiconductor substrate and filling the groove with the second material layer having a different reflection spectrum from the semiconductor substrate, the replacement method is used to replace the second material layer with a part of the semiconductor substrate, so that the etching rate of the semiconductor substrate can be accurately obtained by combining the reflection spectroscopy method.
[0055] The following will introduce the measurement method of the semiconductor etching rate in conjunction with the Figures 2 to 10 description of the accompanying drawings.
[0056] First, refer to Figure 1 and Figure 2 , and perform step S1 to provide the semiconductor substrate 100.
[0057] Specifically, regarding the selection of the semiconductor substrate 100, it may include a silicon substrate, a glass substrate, a sapphire substrate, or a group III-V semiconductor substrate, etc. In this embodiment, the semiconductor substrate 100 takes a silicon substrate as an example, but the selection of the semiconductor substrate 100 is not limited thereto.
[0058] Next, referring to Figure 1 and Figure 2 , perform step S2 to form a first material layer 200 on the surface of the semiconductor substrate 100, and the first material layer 200 has a different reflection spectrum from the semiconductor substrate 100.
[0059] Specifically, in this embodiment, the principle adopted for measuring the etching rate of the semiconductor is as follows: different materials have different reflection spectra. By collecting the reflection spectra of the measured materials, the thickness of the materials can be calculated. Since the semiconductor substrate 100 does not have a reflective film layer, the thickness of the semiconductor substrate 100 cannot be directly measured by the reflection spectroscopy method. Therefore, in this embodiment, through the first material layer 200, the subsequent etching process, and the filling process of the second material layer 400, a part of the material of the semiconductor substrate 100 can be replaced, so that the etching rate of the semiconductor substrate 100 can be accurately obtained by using the replacement method in combination with the reflection spectroscopy method.
[0060] Among them, the first material layer 200 needs to have a different reflection spectrum from the semiconductor substrate 100, that is, the first material layer 200 needs to use a different material from the semiconductor substrate 100. The selection of the first material layer 200 may include a single layer or a stack composed of one or more of a nitride doped silicon carbide (NDC) layer, a silicon oxide layer, or a silicon nitride layer, etc. In this embodiment, the first material layer 200 is preferably a nitride doped silicon carbide (NDC) layer having a large etching selectivity ratio with the semiconductor substrate 100. When performing the etching process, the NDC layer with a lower etching rate is used as a hard mask layer for subsequently etching the semiconductor substrate 100. However, the selection of the first material layer 200 is not limited thereto, and a silicon oxide layer, a silicon nitride layer, or a stack of a silicon oxide layer, a silicon nitride layer, and an NDC layer may also be used.
[0061] Next, referring to Figure 1 , Figure 3 and Figure 4 , perform step S3 to pattern the first material layer 200 to form an etching window 201 exposing the semiconductor substrate 100. Among them, forming the etching window 201 may include the following steps:
[0062] Referring to Figure 3, perform step S3-1, and form a patterned photoresist layer 300 on the surface of the first material layer 200 through processes such as coating, exposure, and development. The selection of the photoresist layer 300 may include positive photoresist or negative photoresist, and there is no excessive limitation here.
[0063] Refer to Figure 4 , perform step S3-2, use the patterned photoresist layer 300 as a hard mask layer to pattern the first material layer 200, so as to form the etching window 201 in the first material layer 200. In this embodiment, since the NDC layer is used for the first material layer 200, dry etching is preferably used to pattern the NDC layer, but the method of patterning the first material layer 200 is not limited thereto. Among them, according to needs, the step of removing the photoresist layer 300 may also be included.
[0064] Next, refer to Figure 1 and Figure 5 , perform step S4, etch the semiconductor substrate 100 to form a groove 101 in the semiconductor substrate 100, and simultaneously obtain the etching time t.
[0065] Among them, the method of etching the semiconductor substrate 100 to form the groove 101 may include wet etching or dry etching. In this embodiment, since the NDC layer is used as the hard mask layer, wet etching is preferably used to pattern the semiconductor substrate 100, that is, the silicon substrate, to form the groove 101, but the patterning method is not limited thereto. When etching the semiconductor substrate 100, record the etching time t required to form the groove 101 for subsequent calculation of the etching rate. The depth of the groove 101 after etching is denoted as Δh.
[0066] Among them, when performing wet etching, the etching solution may include, for example, an HF:HNO3 mixed solution, an NH4OH solution, or a tetramethylammonium hydroxide (TMAH) solution, etc. In this embodiment, since the semiconductor substrate 100 is a silicon substrate, and the first material layer 200 is the NDC layer, and the HF:HNO3 mixed solution has a good selective etching ratio for silicon and NDC materials, therefore, an HF:HNO3 mixed solution is preferably used as the etching solution, but the selection of the etching solution is not limited thereto.
[0067] Preferably, the etching rate of the first material layer 200 is less than that of the semiconductor substrate 100. That is, if both the first material layer 200 and the semiconductor substrate 100 can be etched during the formation of the groove 101, it is necessary to ensure that the first material layer 200 has a sufficient thickness to ensure that the surface of the semiconductor substrate 100 always has the first material layer 200 during the etching process, facilitating subsequent measurements. When the material of the first material layer 200 is selected to have an etching rate less than that of the semiconductor substrate 100, the thickness of the first material layer 200 can be relatively thin; otherwise, the first material layer 200 needs to have a sufficient thickness.
[0068] Next, refer to Figure 1 and Figure 6 , perform step S5 to form a second material layer 400 filling the groove 101, and the second material layer 400 has a different reflection spectrum from that of the semiconductor substrate 100.
[0069] Specifically, the second material layer 400 needs to have a different reflection spectrum from that of the semiconductor substrate 100, that is, the second material layer 400 and the semiconductor substrate 100 need to use different materials. The selection of the second material layer 400 may include, for example, a nitride doped silicon carbide (NDC) layer, a silicon oxide layer, or a silicon nitride layer, etc.
[0070] In this embodiment, the second material layer 400 is a silicon oxide layer, but the selection of the second material layer 400 is not limited thereto. For example, it can also be a silicon nitride layer or an NDC layer, etc. That is, the second material layer 400 can have the same or different materials as the first material layer 200, as long as it is ensured that the second material layer 400, the first material layer 200, and the semiconductor substrate 100 have different materials, facilitating subsequent measurement of the thicknesses of the second material layer 400 and the first material layer 200 by the reflection spectroscopy method to obtain the etching rate of the semiconductor substrate 100.
[0071] Next, refer to Figure 1 and Figure 7 , perform step S6 for planarization processing to make the first material layer 200 and the second material layer 400 located on the same plane, obtaining a structure to be measured.
[0072] Among them, the method of the planarization process may include one or a combination of, for example, mechanical polishing method, chemical polishing method, or dry etching method. To ensure the flatness of the plane for facilitating subsequent thickness measurement, in this embodiment, the chemical mechanical polishing (CMP) method with better planarization effect is adopted, but the method of the planarization process is not limited thereto.
[0073] Next, refer to Figure 1 and Figure 7 , perform step S7, and use the reflection spectroscopy method to measure the measurement structure to obtain the thickness H1 of the first material layer 200 and the thickness H2 of the second material layer 400. The equipment and specific operations adopted by the reflection spectroscopy method are not limited herein.
[0074] Next, perform step S8 to perform data processing to obtain the etching rate V of the semiconductor substrate 100 = (H2 - H1) / t.
[0075] Among them, according to needs, after the planarization process in step S6, the value of the thickness H1 of the first material layer 200 can also be 0, that is, after CMP, the first material layer 200 can also be completely removed, but it is necessary to ensure that the surface of the semiconductor substrate 100 is not polished during the CMP process to ensure that the depth of the groove 101 is still Δh, so as to ensure the accuracy of the etching rate V of the semiconductor substrate 100.
[0076] As an example, the semiconductor substrate 100 may include a wafer-level semiconductor substrate, such as wafers with sizes of 6 inches, 8 inches, 12 inches, etc. The specific size can be selected according to needs, so that according to needs, the above measurement method can be adopted in different regions of the wafer-level semiconductor substrate to obtain the etching rate V at different regions to understand the etching situation of the entire wafer and further improve the accuracy of the wafer etching rate.
[0077] Among them, when etching the semiconductor substrate 100, a plurality of the grooves 101 can be formed simultaneously to save the process, obtain the etching rate V at different regions, understand the etching situation of the entire wafer, and further improve the accuracy of the wafer etching rate. The values of the plurality of the grooves 101 may include, for example, 2, 3, 4, 5, etc., and are not overly limited herein.
[0078] Among them, from the center of the wafer to the edge of the wafer, the grooves 101 may be arranged periodically to regularly obtain data of each region. Among them, the distribution morphology formed by combining the plurality of the grooves 101 may include a ring shape, an S shape, or a square shape, such as Figure 8 shows that the distribution formed by combining the plurality of the grooves 101 is a ring distribution, Figure 9Schematically shows that the distribution pattern formed by combining multiple of the grooves 101 is an S-shaped distribution. Figure 10 Schematically shows a top view structural diagram of the measurement structure in which the distribution pattern formed by combining multiple of the grooves 101 is a square distribution. The specific morphology of the groove 101 and the distribution pattern formed by combining multiple of the grooves 101 are not overly limited here and can be selected as needed.
[0079] In summary, for the method for measuring the semiconductor etching rate of the present invention, grooves are etched in a semiconductor substrate, and a second material layer different from the reflection spectrum of the semiconductor substrate is filled in the grooves. By using the replacement method, the second material layer is replaced with a part of the semiconductor substrate, so that the etching rate of the semiconductor substrate can be accurately obtained by combining the reflection spectrum method; further, this measurement method can also be used to measure the etching rate of a wafer-level semiconductor substrate, so that the etching rate of each region of the wafer can be obtained as needed, thereby further improving the accuracy of the wafer etching rate.
[0080] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A method for measuring the etching rate of a semiconductor, characterized in that, It includes the following steps: Provide a semiconductor detection substrate, which includes a semiconductor substrate and a first material layer formed on the surface of the semiconductor substrate, and the first material layer has a different reflection spectrum from the semiconductor substrate, and the first material layer has an etching window exposing the semiconductor substrate; Etch the semiconductor substrate to form a groove in the semiconductor substrate and obtain the etching time t; Form a second material layer filling the groove, and the second material layer has a different reflection spectrum from the semiconductor substrate; Perform a planarization process so that the first material layer and the second material layer are on the same plane to obtain a structure to be measured; Use the reflection spectroscopy method to measure the measurement structure to obtain the thickness H1 of the first material layer and the thickness H2 of the second material layer; Perform data processing to obtain the etching rate V of the semiconductor substrate = (H2 - H1) / t.
2. The method for measuring the semiconductor etching rate according to claim 1, wherein: The method for etching the semiconductor substrate to form the groove includes wet etching or dry etching.
3. The method for measuring the semiconductor etching rate according to claim 2, wherein: When wet etching is used, the etching solution includes a HF:HNO3 mixed solution, an NH4OH solution or a TMAH solution.
4. The method for measuring the semiconductor etching rate according to claim 1, wherein: The method of the planarization process includes one or a combination of mechanical polishing, chemical polishing or dry etching.
5. The method for measuring the semiconductor etching rate according to claim 1, characterized in that: The etching rate of the first material layer is less than the etching rate of the semiconductor substrate.
6. The method for measuring the semiconductor etching rate according to claim 1, wherein: After the planarization process, the value of the thickness H1 of the first material layer includes 0.
7. The method for measuring the semiconductor etching rate according to claim 1, wherein: The semiconductor substrate includes a silicon substrate, a glass substrate, a sapphire substrate or a III-V group semiconductor substrate; the first material layer includes a laminate formed by one or a combination of an NDC layer, a silicon oxide layer or a silicon nitride layer; the second material layer includes an NDC layer, a silicon oxide layer or a silicon nitride layer.
8. The method for measuring the semiconductor etching rate according to claim 1, characterized in that: The semiconductor substrate includes a wafer-level semiconductor substrate, and a plurality of the grooves are formed when etching the semiconductor substrate.
9. The method for measuring the semiconductor etching rate according to claim 8, wherein: In the direction from the wafer center to the wafer edge, the grooves are arranged periodically.
10. The method for measuring the semiconductor etching rate according to claim 9, wherein: The distribution morphology formed by combining a plurality of the grooves includes a ring shape, an S shape or a square shape.