Characterizing power device on wafer using automated parametric system

Abstract

In some examples, the system may include a parametric system matrix coupled to one or more test and measurement instruments. Further, the system may include an adapter circuit coupled to the parametric system matrix, the adapter circuit having a voltage clamp circuit coupled to the parametric system matrix. Further, the system may include a probe circuit coupled to the adapter circuit and the power device, where the power device is placed on the wafer.

Description

[0001] Cross - reference to related applications

[0002] This application is a continuation-in-part of U.S. Non-Temporary Application No. 18 / 626,190, entitled "UNIFIED MEASUREMENT SYSTEM FOR STATIC AND DYNAMIC CHARACTERIZATION OF A DEVICE UNDER TEST", filed on April 3, 2024, which in turn claims the benefit of U.S. Provisional Patent Application No. 63 / 458,075, entitled "IMPEDANCE MEASUREMENT OF A DEVICE UNDER TEST ON A COMBINED STATIC AND DYNAMIC CHARACTERIZATION PLATFORM", filed on April 7, 2023, U.S. Provisional Patent Application No. 63 / 464,413, entitled "BODY DIODE CHARACTERIZATION ON A UNIFIED MEASUREMENT SYSTEM FOR STATIC AND DYNAMIC CHARACTERIZATION OF A DEVICE UNDER TEST", filed on May 4, 2023, and U.S. Provisional Patent Application No. 63 / 523,836, entitled "GATE CHARGE CHARACTERIZATION OF A DEVICE UNDER TEST ON A UNIFIED STATIC AND DYNAMIC TEST PLATFORM", filed on June 28, 2023; and this application is a continuation-in-part of U.S. Non-Temporary Application No. 17 / 688,733, entitled "UNIFIED MEASUREMENT SYSTEM FOR STATIC AND DYNAMIC CHARACTERIZATION OF A DEVICE UNDER TEST", filed on March 7, 2022, which in turn claims the benefit of U.S. Provisional Patent Application No. 63 / 161,382, entitled "UNIFIED MEASUREMENT SYSTEM FOR STATIC AND DYNAMIC CHARACTERIZATION OF A DEVICE UNDER TEST", filed on March 15, 2021, and U.S. Provisional Patent Application No. 63 / 260,513, entitled "HIGH POWER STATIC AND DYNAMIC DUT CHARACTERIZATION", filed on August 23, 2021.This application also claims the benefit of U.S. Provisional Application No. 63 / 620,350, entitled "SEARCH FUNCTION WITH DEVICE MODELING," filed on January 12, 2024. The disclosure of each of these applications is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to test and measurement systems, and more particularly to systems and methods for performing static and dynamic characterization of devices. Background Art

[0004] Characterization of a device under test (DUT), such as a semiconductor device, such as a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET), generally can include both static characterization (such as current / voltage (I / V) curves) and dynamic characterization (such as switching parameters). Conventional static characterization involves using a dedicated static measurement platform. Additionally, conventional dynamic characterization of a DUT involves different measurement platforms and, in some cases, dedicated custom dynamic platforms.

[0005] There are numerous products on the current market for characterizing power devices and power modules, covering tests such as dynamic evaluation (e.g., double-pulse testing, dynamic leakage, breakdown). Typically, these evaluations are performed on packaged parts or modules. Dynamic testing generally involves combining an oscilloscope with a capacitor bank to facilitate high-voltage and high-current testing.

[0006] There are challenges in combining power measurements (such as dynamic double-pulse testing) with parametric testing in an automated manner on a wafer. Currently, there is no commercially available solution that can perform production-level characterization of power devices on a wafer, combine parameter-sensitive measurements, and meet the speed requirements of a production process.

[0007] Embodiments of the disclosed apparatus and method address the disadvantages in the prior art. Brief Description of the Drawings

[0008] For a more particular description of the features summarized above, which can be understood in which manner, reference may be had to example embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings only illustrate typical example embodiments and are therefore not considered to limit their scope.

[0009] Figure 1 An example of a conventional dedicated static characterization measurement platform is shown.

[0010] Figure 2 Shows an example of a conventional dedicated dynamic characterization measurement platform.

[0011] Figure 3 Shows an embodiment of a test and measurement system according to an embodiment of the present disclosure.

[0012] Figure 4 Shows an embodiment of a characterization circuit for characterizing parameters of one or more DUTs in combination with Figure 3 a test and measurement system.

[0013] Figure 5 Shows an embodiment of a characterization circuit according to an embodiment of the present disclosure, the characterization circuit including a selection switch for independently characterizing parameters of two DUTs in combination with Figure 3 a test and measurement system.

[0014] Figure 6 Is an example schematic diagram of a characterization circuit according to an embodiment of the present disclosure, in combination with Figure 3 a test and measurement system for static and dynamic characterization of one or more DUTs.

[0015] Figure 7 Is a schematic of a solid-state bias tee that can be utilized in a characterization circuit according to an embodiment of the present disclosure, in Figure 6 , Figure 8 and Figure 9 .

[0016] Figure 8 Is an example schematic diagram of another characterization circuit according to an embodiment of the present disclosure, in combination with Figure 3 a test and measurement system for static and dynamic characterization of one or more DUTs.

[0017] Figure 9 Is an example schematic diagram of a characterization circuit according to an embodiment of the present disclosure, in combination with Figure 3 a test and measurement system for gate charge characterization and body diode characterization of one or more DUTs.

[0018] Figure 10 Shows an example of a characterization measurement platform coupled to a wafer for testing according to some examples.

[0019] Figure 11 Shows an embodiment of a test and measurement system according to an embodiment of the present disclosure.

[0020] Figure 12 Is a flowchart for testing power devices on a wafer using Figure 11 a test and measurement system according to some examples.

[0021] For ease of understanding, wherever possible, the same reference numerals have been used to denote the same elements common to the figures. It is contemplated that elements of one example may be beneficially incorporated into other examples. Detailed Description

[0022] Various features will be described hereinafter with reference to the figures. It should be noted that the figures may or may not be drawn to scale, and throughout the figures, elements of similar structure or function are denoted by like reference numerals. It should be noted that the figures are merely intended to facilitate the description of features. They are not intended as an exhaustive description of the specification or as a limitation on the scope of the claims. Additionally, the illustrated examples need not have all aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example, even if not so illustrated or not so explicitly described.

[0023] Conventionally, high-power characterization of a device under test (DUT) typically involves a static measurement platform. Figure 1 An example of such a platform 10 is shown. In this example, the platform includes test and measurement equipment 12, a test fixture 14 to which one or more DUTs (not shown) are connected, and a power expander 16.

[0024] Performing dynamic power characterization requires a separate platform, which is either a large floor model platform or a custom platform. Figure 2 An example of such a platform 20 is shown, and the platform 20 may include some or all of the components shown. The test and measurement equipment 22 may actually include one or more test and measurement devices, such as an oscilloscope and an impedance analyzer. The test and measurement equipment 22 is connected to a test board 26 and a DUT via a high-voltage probe 24. The test board 26 may have a driver board 28, typically for stably turning on and off a power switch and possibly providing power protection. The DC circuit 32 may include a DC link capacitor, a DC voltage source, and a load inductor. A current sensor 30 and a signal generator 34 are connected to the test board to allow the board to be tested.

[0025] Generally, characterizing a device statically or dynamically requires separate large instruments and fixture platforms. The embodiments herein provide a combined characterization system having two components, an interactive test and measurement device, such as an oscilloscope, an impedance analyzer, a combination of both, or one or more of many other test and measurement devices. For simplicity, this discussion refers to this test component as the test and measurement equipment. The other component is a power delivery and measurement front end having a DUT interface for mounting a test board, which may also be referred to as a fixture in the present disclosure. The embodiments herein generally relate to two separate components, but they may also be mounted in one housing.

[0026] As used herein, the term "high voltage" refers to any voltage equal to and above 42 volts.

[0027] The embodiments herein provide a dual-purpose characterization platform with several advantages. The system, meaning both the test equipment and the fixture, is sized to allow transportation by an individual. For safety, the fixture encloses all high-voltage circuits and may have an interlock device that prevents improper operation of the high-voltage system that may be caused by a fault in the system. The system simplifies installation because the user only needs to place the DUT into the fixture. The two components in the system are connected by a simple cable, so the system does not require rewiring between various tests. The automated switching of the measurement configuration allows the user to obtain all the parameters required for the test. The fixture may also include heating and / or cooling equipment, as well as a protective barrier around the equipment to prevent damage to the equipment.

[0028] Figure 3 An embodiment of a test and measurement system 300 is shown, which may also be referred to as a platform, having a test and measurement device 40, such as an oscilloscope or other test and measurement device. For ease of discussion, device 40 may be referred to as the test and measurement device. Another part of the system is the static and dynamic power and measurement device 50. These terms are not intended to limit the capabilities of either device and should not imply such a limitation.

[0029] The test and measurement device 40 may have many different components, including a user interface 44 that allows the user to interact with various menus. The user interface 44 allows the user to make selections for the tests to be run, set parameters, etc., such as through a display with a touch screen or various buttons and knobs. The test and measurement device 40 has one or more processors 46 that receive user input and send parameters and other selections to the measurement device, and may receive outputs from the power and measurement device 50 and generate outputs for the user based on the data. The test and measurement device 40 includes a measurement unit 47 that performs tests and measures DUT parameters. A remote device 42, such as a computing device, such as a personal computing device or a smart phone, may also access the test and measurement system 300 through the test and measurement device 40 or the power and measurement device 50 for remote operation. The term "processor" as used herein means any electronic component capable of receiving instructions and performing actions, such as a microcontroller, a field-programmable gate array (FPGA), and an application-specific integrated circuit (ASIC), which will be discussed in more detail below.

[0030] The test and measurement device 40 communicates with the power and measurement device 50 through a direct connection 48 such as a cable. The two measurement devices 40, 50 and the direct connection 48 are configured to be portable and transportable by an individual. The direct connection 48 is connected to each device through a connection circuit (not shown), and this connection circuit allows the measurement devices 40, 50 to switch test configurations without having to rewire.

[0031] The power and measurement device 50 may also have several different components. These components may include one or more processors 52, a high-voltage circuit 56 that provides high voltage to one or more devices under test ((one or more) DUTs) 70, and an interlock device 54 that serves as a high-voltage circuit protection. Depending on the test configuration of the test and measurement device 40 and the power and measurement device 50, the (one or more) DUTs 70 may include one or more individual DUTs. The interlock device 54 is designed to prevent equipment damage under any hazardous conditions caused by the high voltage generated by the high-voltage circuit 56. The (one or more) DUTs 70 are mounted to a DUT interface 58, which may be a general DUT interface for mounting the DUT and which allows the (one or more) DUTs 70 to be connected to various components in the power and measurement device 50.

[0032] The operation of the high-voltage circuit 56 and the operation of the (one or more) DUTs 70 may generate heat, and / or the (one or more) DUTs 70 may require a specific temperature range for operation. The power and measurement device 50 may thus include a temperature control circuit 62 to control the temperature of the (one or more) DUTs 70. One or more processors 52 monitor the temperature and operate the temperature control circuit 62, and the temperature control circuit 62 may include items such as fans, switchable heat sinks, cooling systems, heaters, etc. The power and measurement device 50 may also include a barrier 64 to protect the power and measurement device 50 from damage by the (one or more) DUTs 70. The power and measurement device 50 may also include a switching circuit 60 that controls the operation of various components within the power and measurement device 50 to test and measure the characteristics of the (one or more) DUTs 70.

[0033] Generally, in operation, the user provides inputs remotely or directly through a user interface 44 to control the operation of the power and measurement device 50, thereby statically or dynamically characterizing the (one or more) DUTs 70. Typically, a half-bridge circuit (such as Figure 4 the characterization circuit 400 in the embodiment shown in

[0034] The characterization circuit 400 includes a half-bridge circuit formed by two DUTs (DUT_top and DUT_bot), which two DUTs correspond to the (one or more) DUTs 70 illustrated in Figure 3 the test and measurement system 300. In this description, the DUT DUT_top may be referred to as the top device DUT_top, and the DUT DUT_bot is referred to as the bottom device DUT_bot. A method of performing dynamic characterization (herein referred to as the double-pulse method) uses the half-bridge circuit. The double-pulse method or “double-pulse test” is discussed in more detail below with reference to Figure 6 In the characterization circuit 400, the top device DUT_top and the bottom device DUT_bot of the half-bridge circuit are coupled in series between a supply voltage node and a reference voltage node. In Figure 4 an example embodiment of, each of the devices DUT_bot, DUT_top is a field effect transistor (FET), and more specifically an N-channel MOSFET.

[0035] In general operation, the bottom device DUT_bot is turned on to obtain a desired current through the test inductor Test_L. Subsequently, the bottom device DUT_bot is turned off, and the top device DUT_top is turned on, which causes the inductor current to circulate through the top device DUT_top from the Test_L inductor. Alternatively, if only one (one or more) DUT 70 is being tested, the top device DUT_top may be replaced by a diode. After a specified time depending on the characteristics of the top device DUT_top and the bottom device DUT_bot, the top device DUT_top is turned off, and the bottom device DUT_bot is turned on again. Desired data for testing and characterizing the top device DUT_top and the bottom device DUT_bot may be collected during these transitions and operations of the top device DUT_top and the bottom device DUT_bot, and energy losses may be calculated. Based on the control of the voltage and current through the devices DUT DUT_top, DUT_bot, the same platform may be used to extract static parameters.

[0036] Replacing the top device DUT_top with a diode or a short allows for gate control of the bottom device DUT_bot, which in turn allows for the extraction of the static current-voltage (I / V) curve. When the top device DUT_top is available or present, additional methods for extracting static data can be used. These can include independent gate / drain potential pulses at the bottom device DUT_bot. To this end, the system will control the voltage at the gate of the bottom device DUT_bot to allow for proper transfer characteristic measurements of the device. Static I / V device characterization does not require the test inductor Test_L, but the inclusion or presence of the test inductor Test_L allows the same circuit to perform both static and dynamic characterization. If both the top device DUT_top and the bottom device DUT_bot are present in the characterization circuit 20 and are of the same device type, the maximum power will be divided between the top device DUT_top and the bottom device DUT_bot. If a full-power test of one of the devices DUT_top, DUT_bot is desired, the other device will be replaced with a short.

[0037] Figure 4 Also shown are several measurement points or channels in the characterization circuit 400 at which power is associated with the measurement device 50 detecting or sensing electrical parameters, i.e., voltage or current, of the devices DUT_top, DUT_bot during testing and characterization of the top device DUT_top and the bottom device DUT_bot. Each measurement channel is indicated by an angled arrow and an associated descriptor that indicates the parameter sensed at that measurement channel. For example, as shown, the characterization circuit 400 includes a first current-sensing resistor R1 coupled in series with the test inductor Test_L, and second and third current-sensing resistors R2 and R3 coupled in series with the top device DUT_top and the bottom device DUT_bot, respectively. A measurement channel detects the current passing through resistor R1, which corresponds to the current Inductor_i passing through the test inductor Test_L. Another measurement channel detects the current passing through resistor R2, which corresponds to the drain current Drain_i into the top device DUT_top. A third measurement channel detects the current passing through resistor R3, which corresponds to the source current Source_i passing through the bottom device DUT_bot.

[0038] The characterization circuit 400 includes additional measurement channels for detecting voltage and current at various points in the characterization circuit, all of which allow the power and measurement device 50 to capture operation data for the top device DUT_top and the bottom device DUT_bot and utilize the captured operation data to perform the characterization of one or both of the top device DUT_top and the bottom device DUT_bot. Similar measurement channels are in Figures 5 to 8is shown in the schematic diagrams and will not be discussed in more detail with respect to these diagrams as the functionality of these test points or channels will be understood in accordance with the description above with respect to Figure 4 the measurement channels.

[0039] Figure 5 An embodiment of a characterization circuit 500 is shown which includes a half-bridge switching circuit formed by a top device DUT_top and a bottom device DUT_bot and which includes a switch SW1 that is used to allow selection between the top device DUT_top and the bottom device DUT_bot. This selection can be entered into the power and measurement device 50 ( Figure 3 ) via a user interface 44 on the test and measurement device 40 of Figure 3 , and this selection is transmitted to the power and measurement device 50 via a direct connection 48. In the case where the switch SW1 is added, if both the top device DUT_top and the bottom device DUT_bot are installed, then both the DUT_top and the DUT_bot can be characterized in both static and dynamic configurations. Figure 5 The configuration of the characterization circuit 500 shown in Figure 3 shows the bottom device DUT_bot being selected for testing or characterization. In operation, the user selects static or dynamic characterization and selects one of the top device DUT_top and the bottom device DUT_bot via a user interface 44 on the test and measurement device 40 in the test and measurement system 300 of

[0040] An embodiment of a test and measurement system in accordance with the present disclosure includes Figure 4 and Figure 5 one or both of the characterization circuits 400, 500 of

[0041] and provides the ability to combine static and dynamic measurements without the need to use multiple setups and instrumentation or even rewire for a particular configuration. The test and measurement system outputs desired characterization data for the DUT being tested or characterized. This data can be generated on the user interface 44 of the test and measurement device 40 and / or can be output to a file for further analysis, such as a file for an analysis software package. This can be achieved by one or more processors 46, 52 in the power and measurement device 50 or the test and measurement device 40.Embodiments of the present disclosure relate to a characterization circuit for a test and measurement system that eliminates the need to perform static and dynamic characterization of a DUT using a conventional bias tee. As described in more detail below, a solid-state bias tee includes a DUT and a gate drive voltage generator that provides a DC pulse signal and an AC signal to the gate of the DUT to cause the DUT to provide a required current and voltage signal to another DUT to be characterized. The characterization circuit operates in different modes, which enables the functions of the DUT in the solid-state bias tee and the DUT to be characterized to be reversed, and in this way, enables the dynamic and static characterization of two DUTs without using a conventional bias tee. Eliminating the need for a conventional bias tee is advantageous because such a conventional bias tee must be designed for a specific voltage and frequency range and typically includes discrete inductance, capacitance, and resistance components, which complicates the integration of the conventional bias tee into a dynamic characterization platform. Conventional bias tees also have current and frequency limitations that restrict the impedance measurements that can be performed on the DUT to be characterized. Further embodiments of the present disclosure relate to a characterization circuit coupled to a first DUT and a second DUT that can simultaneously generate gate charge characterization parameters for one DUT and body diode characterization for the other DUT.

[0042] Figure 6 is a schematic diagram of an example characterization circuit 600 for performing static and dynamic characterization of one or more DUTs (DUT_top, DUT_bot) in conjunction with Figure 3 a test and measurement system 300 in accordance with embodiments of the present disclosure. The characterization circuit 600 implements both static and dynamic characterization of the DUTs (DUT_top and DUT_bot). In the following description, reference is made to Figure 6 as well as reference to Figure 7 and Figure 8 In the DUTs of, the DUTs (DUT_top and DUT_bot) may again be referred to as the top device DUT_top and the bottom device DUT_bot. In an example embodiment of Figure 6 each of the top device DUT_top and the bottom device DUT_bot is an N-channel MOSFET. Further embodiments may include other types of power transistors. Each DUT will be described as including drain, source, and gate nodes, which is applicable to embodiments where each DUT is a MOSFET, but these nodes are also intended to apply to equivalent nodes associated with different types of transistors.

[0043] In Figure 6In the characterization circuit 600, the top device DUT_top and the bottom device DUT_bot form a half-bridge circuit, and this half-bridge circuit is serially coupled with a current sense resistor RS1 between a supply voltage node SVN and a reference voltage node RVN. An adjustable DC power supply voltage source DC_adj with a supply resistor R_sup is coupled across the voltage nodes SVN and RVN to supply a desired DC voltage across these nodes. The capacitor C can include one or more capacitors, which filter the noise across the voltage nodes SVN and RVN.

[0044] A switching node SN is defined at the interconnection between the source and drain of the top device DUT_top and the bottom device DUT_bot, and a test inductor TEST_L is serially coupled with a current sense resistor RS2 between the switching node SN and the supply voltage node SVN. The test inductor TEST_L enables the characterization circuit 600 to provide a desired current through one of the top device DUT_top and the bottom device DUT_bot as a source element across the other of the top device DUT_top and the bottom device DUT_bot, or a voltage across the other of the top device DUT_top and the bottom device DUT_bot, as part of dynamically characterizing the other of the top device DUT_top and the bottom device DUT_bot. In this specification, one of the top device DUT_top and the bottom device DUT_bot to be characterized can also be referred to as the element to be measured. The gate drive voltage generator GD and the amplifier AMP operate in combination to provide a gate drive signal including a DC pulse and an AC signal to the bottom device DUT_bot and detect the gate current of the bottom device DUT_bot as part of measuring the gate-source capacitance Cgs of the bottom device DUT_bot.

[0045] Figure 6Illustrates the configuration of characterization circuit 600, where the top device DUT_top serves as the source element, and the bottom device DUT_bot is the element to be measured (i.e., the device to be characterized). The top and bottom devices DUT_top and DUT_bot are controlled such that desired AC and DC voltages are applied to the bottom device DUT_bot to measure the desired dynamic and static parameters of the bottom device DUT_bot and thereby characterize the bottom device DUT_bot. Static current and voltage device characterization of devices DUT_top, DUT_bot do not require the test inductor Test_L, but the presence of the inductor allows the same characterization circuit 600 to perform both static and dynamic characterizations. In operation, the top device DUT_top is initially turned off, and the bottom device DUT_bot is initially turned on to provide a desired inductor current IL as the desired drain current through the bottom device DUT_bot. When the current through the test inductor TEST_L reaches the desired value, the bottom device DUT_bot is turned off, and the inductor current IL recirculates through the body diode (not shown) of the top device DUT_top. The gate drive generator GD provides DC and AC signals to devices DUT_bot, DUT_top such that static parameters of the bottom device DUT_bot, as well as dynamic parameters such as gate-source capacitance Cgs, gate-drain capacitance Cgd, and drain-source capacitance Cds, can be measured.

[0046] Characterization circuit 600 can characterize each of the top device DUT_top and the bottom device DUT_bot by switching the connection of the test inductor TEST_L and switching the coupling of the amplifier AMP. To configure the bottom device DUT_bot as the source element and the top device DUT_top as the element to be measured and characterized, the terminals of the test inductor TEST_L coupled to the supply voltage node SVN will instead be coupled to the reference voltage node RVN. Additionally, the amplifier AMP will be coupled to the gate of the top device DUT_top in the same manner as Figure 6 shown for the bottom device DUT_bot, or alternatively, the characterization circuit 600 can include an additional amplifier (not shown) coupled to the gate of the top device DUT_top.

[0047] The characterization circuit 600 includes a number of measurement points or channels Chan1-Chan6, at which the power and measurement device 50 detects or senses the electrical parameters, i.e., voltage or current, of the top device DUT_top and the bottom device DUT_bot during testing and characterization. By sensing the parameters at the measurement channels Chan1-Chan6, the power and measurement device 50 captures the operation data for one of the top device DUT_top and the bottom device DUT_bot being characterized. The power and measurement device 50 uses the captured operation data to characterize the corresponding device DUT_top, DUT_bot. The first measurement channel Chan1 senses the drain voltage Drain_bot of the bottom device DUT_bot with respect to the reference voltage node srcB. The drain current passing through the bottom device DUT_bot is sensed through the measurement point Chan2, and the gate-source voltage Vgs of the bottom device DUT_bot is sensed at the measurement channel Chan3. The measurement channel Chan4 measures the inductor current IL passing through the test inductor TEST_L, the test channel Chan5 measures the gate-source voltage Vgs of the top device DUT_top, and the test channel Chan6 measures the drain voltage Drain_top of the top device DUT_top.

[0048] In the characterization circuit 600, one of the devices DUT_top, DUT_bot can be configured to implement the equivalent operation of a source bias tee during a double pulse test. The double pulse test is a test methodology for measuring the dynamic characteristics, such as switching parameters, of a power switching element, such as a power FET. The top device DUT_top is the source element and its function is equivalent to Figure 6 the source bias tee in the configuration. In this configuration, the top device DUT_top provides the required DC voltage and the necessary AC signal to properly stimulate the element being measured, which in this case is the bottom device DUT_bot being characterized.

[0049] Figure 6Embodiments show a configuration for current-mode driving a device by modulating the gate-source voltage Vgs of a top device DUT_top. In this way, the top device DUT_top acts as a source element for characterizing a bottom device DUT_bot. Due to the quadratic relationship between the gate-source voltage Vgs and the drain current ID of the top device DUT_top, where the top device DUT_top is a FET (i.e., ID = f(Vgs2)), the AC signal component provided by the gate drive voltage generator GD is generally provided at half the desired measurement frequency. Due to the doubling of frequency caused by this squaring of the AC signal component, a drain current ID is generated at twice the frequency of the AC signal component applied to the gate. This AC signal component generates an AC signal superimposed on the DC bias current (i.e., the drain current ID through the device DUT_bot). The impedance measurement of the bottom device DUT_bot for determining the gate-source capacitance Cgs and the drain-source capacitance Cds is made by performing a vector division on the applied AC voltage (measured by channel Chan1) and measuring the AC current Gate_i of the bottom device DUT_bot (provided by the amplifier AMP) and the source current (Source_i) of the bottom device DUT_bot (measured at channel Chan2), where the applied AC voltage is provided by the top device DUT_top at the drain (Drain_bot) of the bottom device DUT_bot.

[0050] In the characterization circuit 600, the top device DUT_top can be used as a controlled current source for characterizing the bottom device DUT_bot at a specified drain current ID through the bottom device DUT_bot. Additionally, the top device DUT_top can be used to set a specified voltage at the drain (Chan1) of the bottom device DUT_bot. In an embodiment of the characterization circuit 600, the use of the top device DUT_top as a controlled current source or for setting the specified drain voltage can be controlled in a scanning or pulsed mode to measure the characteristics of the bottom device DUT_bot over a wide range of specified parameters. In instances where applying a DC signal at the desired value may damage or destroy the bottom device DUT_bot being characterized, the value of the controlled current or voltage can be scanned or varied within a range of values and pulsed.

[0051] The gate drive voltage generator GD that drives the gates of the top device DUT_top and the bottom device DUT_bot provides the characterization circuit 600 with the ability to characterize both the top device DUT_top and the bottom device DUT_bot. Additionally, the ability to measure the gate and source currents of each of the top device DUT_top and the bottom device DUT_bot relative to an AC signal applied to the drain of the bottom device DUT_bot (i.e., the DUT being characterized) enables the measurement of all impedances associated with the bottom device DUT_bot. These measurement capabilities, along with the ability to switch source and measurement elements, enable the characterization circuit 600 to fully characterize each of the top device DUT_top and the bottom device DUT_bot.

[0052] Figure 7 is a schematic of a solid-state bias tee 700 that can be utilized in the characterization circuits 600, 800, and 900 according to embodiments of the present disclosure. The solid-state bias tee 700 can be used in other characterization circuits, including those not configured to perform double-pulse testing, as well as the characterization circuits 600, 800, and 900. The solid-state bias tee 700 includes an FET 702 and a gate drive voltage generator GD that provides a DC pulse signal and an AC signal to the gate of the FET 702. In Figure 6 , Figure 8 and Figure 9 the example embodiment, the FET is an N-channel FET, but in other embodiments can be other types of transistors. The bias tee 700 includes a first node 704, a second node 706, and a third node 708 that are coupled to the gate, drain, and source of the FET 702, respectively. In operation, the gate drive voltage generator GD provides a drive signal at the first node 704 that includes appropriate AC and DC pulse components to control the FET 702 to act as a controlled current source to provide a desired drain current ID or to set a specified voltage at the source of the FET 702. In this manner, the gate drive voltage generator GD and the FET 702 act as a bias tee to provide a desired voltage or current with desired AC and DC components at the source S of the FET 702. In Figure 7 the example embodiment, the gate drive voltage generator GD and the top device DUT_top correspond to Figure 6 an example implementation of the bias tee 700 of Figure 7 .

[0053] Figure 8 is a schematic of another example characterization circuit 800 for static and dynamic characterization of one or more DUTs in accordance with embodiments of the present disclosure, in combination with Figure 3 the test and measurement system 300. The components in the characterization circuit 800 are the same as Figure 6The corresponding components in the characterization circuit 600 are the same. In contrast to the characterization circuit 600, the characterization circuit 800 includes a voltage feedback from the Drain_top through the voltage feedback resistor R_vf to control the gate drive voltage generator GD that drives the gate of the top device DUT_top, where the top device DUT_top acts as the source element in the illustrated example embodiment. In the characterization circuit 800, the frequency of the modulation or AC signal provided by the gate drive voltage generator GD is the same as the desired frequency of the drain current ID provided to the bottom device DUT_bot to be characterized.

[0054] Both the characterization circuits 600 and 800 can be used to measure Cgd and Cds. To measure the gate-source capacitance Cgs, the gate drive voltage generator GD provides an appropriate DC bias signal and a desired AC stimulus signal to the gate of the bottom device DUT_bot, where the impedance is measured using the gate current Gate_i sensed by the amplifier AMP and the gate voltage measurement at Channel Chan3.

[0055] Figure 9 is according to an embodiment of the present disclosure, in combination with Figure 3 A schematic diagram of an example characterization circuit 900 of a test and measurement system 300 for gate charge characterization and body diode characterization of one or more DUTs. Conventional methods for measuring the gate charge curve of an FET involve a source measurement unit (SMU) or other equivalent device that supplies a constant current to the gate of the FET and measures the resulting gate-source voltage Vgs over time. In addition, the SMU or equivalent device simultaneously provides the desired drain voltage and drain current to the FET. This method requires a dedicated device in the form of an SMU to generate the gate charge curve and provide a static characterization of the FET.

[0056] Characterization circuit 900 enables the characterization of the gate charge curves of each of the top device DUT_top and the bottom device DUT_bot without the need to rewire the connections between each device and the external test equipment. The top device DUT_top and the bottom device DUT_bot are coupled in series with a switching node SN defined at their interconnection. A test inductor TEST_L is coupled in series with a first current sense resistor R1 between a switch SW and the switching node SN. An adjustable DC supply voltage source DC_adj is coupled across voltage nodes SVN, RVN to supply a desired DC voltage across these nodes, and a capacitor C filters the noise across the voltage nodes. To measure the currents I_top, I_bot through the top device DUT_top and the bottom device DUT_bot respectively, a second current resistor R2 is coupled between the supply voltage node SVN and the drain of the top device DUT_top, and a third current sense resistor R3 is coupled between the source of the bottom device DUT_bot and the reference voltage node RVN. In Figure 9 the switch SW is shown in a position that makes the bottom device DUT_bot the element to be measured or the device to be characterized and makes the top device DUT_top the source element.

[0057] In the operation of the characterization circuit 900, the gate charge characteristics of the bottom device DUT_bot can be determined using the following process. First, the power supply DC_adj is set to a desired starting DC voltage level for the drain-source test voltage of the bottom device DUT_bot. Initially, both the top device DUT_top and the bottom device DUT_bot are turned off. The bottom device DUT_bot is then turned on for a period of time to allow a desired inductor current IL to flow through the test inductor TEST_L. The current IL through the inductor TEST_L can be calculated (di / dt = V / L) or continuously measured and then determined based on the expiration of a specific time or the measured inductor current reaching a desired current threshold.

[0058] When the inductor current IL reaches the desired current threshold, the bottom device DUT_bot is turned off. At this time, the inductor current IL will continue to flow through the inductor TEST_L and will also flow through the body diode BD_top of the top device DUT_top. The top device DUT_top can be turned on at this time to reduce the decay of the current IL due to the losses in the body diode BD_top. Then a delay time is waited to ensure that the bottom device DUT_bot is fully turned off. If the top device DUT_top is turned on, the top device DUT_top is turned on and then a delay time is waited to ensure before the bottom device DUT_bot is turned on again.

[0059] At this time, the gate drive voltage generator GD provides an initial desired voltage Vg_bot on the gate of the bottom device DUT_bot. This initial voltage is typically zero volts, but other levels may also be desired. The gate drive voltage generator GD then supplies a constant current to the gate of the bottom device DUT_bot. In an embodiment, the constant current source of the gate drive voltage generator GD can be replaced with a voltage source in series with a resistor. Then, the voltage Vg_bot at the gate of the bottom device DUT_bot is continuously measured or sampled over time.

[0060] The measured gate voltage Vg_bot and current, or the calculated current if the gate drive voltage generator GD includes a voltage source with a resistor, are used to obtain the complete gate charge characteristics of the bottom device DUT_bot for a set drain current and an initial drain voltage Drain_bot. Then, if desired, this entire process can be repeated at different drain-source VDS voltages for the bottom device DUT_bot and at different desired levels or values of the drain current ID through the bottom device DUT_bot. This process will provide gate charge parameters for the bottom device DUT_bot at different current and voltage levels. To obtain these same gate charge parameters for the top device DUT_top, the switch SW is switched to the bottom position so that the associated terminal of the test inductor TEST_L is connected to the reference voltage node RVN instead of the supply voltage node SVN. Now, if the operation of the top device DUT_top and the bottom device DUT_bot is reversed or switched from that described above, the gate charge curve characteristics of the top device DUT_top can be measured. This operation of the characterization circuit 900 to characterize the gate charge parameters of both the top device DUT_top and the bottom device DUT_bot assumes that the gate control and measurement capabilities of the characterization circuit are the same for both the top device DUT_top and the bottom device DUT_bot.

[0061] In addition to the gate charge curve parameters of the top device DUT_top and the bottom device DUT_bot, the characterization circuit 900 enables the measurement of the dynamic characteristics of the body diodes BD_top and BD_bot of the top device DUT_top and the bottom device DUT_bot. These body diode parameters are typically measured by a double-pulse test. The characterization circuit 900 can measure the body diode parameters through the following process. Initially, the adjustable DC supply voltage source DC_adj is set to a desired starting DC voltage level, and both the top device DUT_top and the bottom device DUT_bot are turned off. The bottom device DUT_bot is then turned on for a period of time to reach a desired current threshold for the current IL through the inductor TEST_L. As previously described, the value of the current IL can be calculated based on the time the bottom device DUT_bot is turned on, or can be continuously measured.

[0062] Once the current IL through the inductor TEST_L reaches the desired threshold, the bottom device DUT_bot is turned off. At this time, the inductor current IL will now flow through the body diode BD_top of the top device DUT_top. During this period, the current and voltage parameters of the body diode BD_top can be extracted during the stationary segment of the current through the body diode, and the dynamic parameters can be extracted during the transition of this current. Thereafter, the bottom device DUT_bot is turned on, and a delay time is provided to adjust the inductor current IL to the next desired value or level. Thereafter, the bottom device DUT_bot is turned off, and the body diode parameters of the body diode BD_top are measured again at the new level of the inductor current. Then, the process is repeated at different DC voltage levels provided by the adjustable DC supply voltage source DC_adj, and the turn-on timing of the bottom device DUT_bot is adjusted accordingly to account for changes in the rate of change of the inductor current IL through the inductor IL, or the current is directly measured until the threshold is reached. The entire process can be repeated at different gate-source voltages Vgs, which are supplied to the gate drive voltage generator GD coupled to the gate of the top device DUT_top.

[0063] Through the above process, the characterization circuit 900 extracts or measures the body diode parameters of the body diode BD_top of the top device DUT_top. When the configuration of the switch SW is set at Figure 9When at the first position shown, this process can be executed. To extract or measure the same parameters of the body diode BD_bot of the bottom device DUT_bot, the switch SW only needs to be set to the second position, that is, to couple the associated terminal of the inductor TEST_L to the reference voltage node RVN instead of the supply voltage node SVN. Once the switch SW is set to the second position, the top device DUT_top and the bottom device DUT_bot described above are controlled and measured to extract or measure the parameters of the body diode BD_bot of the bottom device DUT_bot.

[0064] The characterization circuit 900 eliminates the need for a negative power supply voltage source to perform a complete body diode characterization on both the top device DUT_top and the bottom device DUT_bot. In addition, in an embodiment of the characterization circuit 900, the gate charge curve parameters of the other device can be measured while measuring the body diode parameters of one of the top device DUT_top and the bottom device DUT_bot. For example, as described above, when measuring the gate charge curve characteristics of the bottom device DUT_bot, the characteristics of the body diode BD_top of the top device DUT_top can be measured during part of the gate charge curve characterization process when the bottom device DUT_bot is disconnected. This parameter extraction occurs at the same time or simultaneously during the operation of the characterization circuit 900, which reduces the time required to characterize the gate charge curve of one of the devices DUT_top, DUT_bot and the body diode characteristics of the other device DUT_bot, DUT_top.

[0065] In Figure 9 In an embodiment, the top DUT DUT_top and the bottom DUT DUT_bot are shown as MOSFETs, each including a corresponding body diode BD. However, the embodiments of the characterization circuit 900 are not limited to characterizing MOSFETs or other types of FETs that include body diodes, such as SiC MOSFETs. More generally, the characterization circuit 900 can characterize the reverse current path in FETs that do not include body diodes (such as gallium nitride (GaN) FETs). In an embodiment of the characterization circuit 900 in which the top DUT DUT_top and the bottom DUT DUT_bot are FETs that do not include the body diode BD (such as GaN FETs), the characterization circuit will operate as described above, except that when measuring the reverse conduction condition of one of the top and bottom GaN FETs to be characterized, the characterization circuit 900 will apply a desired gate voltage to the GaN FET to be characterized. This desired gate voltage will be applied during the time when the inductor current IL is expected to circulate as a reverse current through the GaN FET to be characterized.

[0066] Embodiments of the present disclosure relate to a characterization circuit for a test and measurement system used for parametric testing on a wafer. As described in more detail below, the present disclosure describes a system for performing production-level characterization of power devices on a wafer, which combines parametric sensitive measurements and meets the speed requirements of the production process. The present disclosure relates to a solution to these challenges by combining a parametric system or semiconductor characterization system with power device measurements. The present disclosure relates to a solution to these challenges by including on a probe card some pins for low voltage and / or low current measurements and other pins for power device evaluation, which may involve high voltage and / or high current measurements. The present disclosure relates to a solution to these challenges by replacing an oscilloscope with an ultrafast pulse measurement unit (PMU), which allows short and fast voltage pulses and also measures transients, serving the role of a gate drive function for both dynamic testing and measurement, effectively replacing the oscilloscope. The central components of the present disclosure need to employ circuits that perform functions such as voltage clamping, voltage division, and protection against 3 kV potential.

[0067] The integration of these components solves the challenges mentioned above, presenting an unparalleled and unique solution. This solution brings several different capabilities. For example, the PMU can be used as a test and measurement instrument within the characterization system. Software on the characterization system can be used to run customized and adaptive tests, enabling data analysis and parameter extraction, including dynamic double-pulse, breakdown, leakage, and threshold voltage measurements. The extracted data is then transmitted to the system for comprehensive data reporting.

[0068] Figure 10 An example of a characterization measurement platform coupled to a wafer for testing is shown according to some examples.

[0069] The test and measurement system 1000 includes a test and measurement instrument 1002, a parametric system matrix 1004, an adapter circuit 1006, a probe circuit 1008, and a wafer 1010. As Figure 10 illustrated, the test and measurement instrument 1002 is coupled to the parametric system matrix 1004. The parametric system matrix 1004 is coupled to both the adapter circuit 1006 and the probe circuit 1008. The adapter circuit 1006 is in turn also coupled to the probe circuit 1008. The probe circuit 1008 is coupled to one or more DUTs 1012 of the wafer 1010.

[0070] The test and measurement instrument 1002 can be any test and measurement instrument used to test the wafer 1010. For example, the test and measurement instrument 1002 can be a pulse measurement unit (PMU), a source measurement unit (SMU), or a digital multimeter. In some examples, the test and measurement instrument 1002 can be the test and measurement device 12, the test and measurement device 22, or the test and measurement device 40. In some examples, any number of test and measurement instruments 1002 can be coupled to the parameter system matrix 1004. Additional details regarding the test and measurement instrument 1002 are described herein with reference to Figure 11 are described.

[0071] The parameter system matrix 1004 is a switching network coupled to the test and measurement instrument 1002. In some examples, the parameter system matrix 1004 can be coupled to any number of test and measurement instruments 1002 and can be coupled to other devices, such as a ground power supply. The parameter system matrix 1004 is configured to link the test and measurement instrument 1002 to the adapter circuit 1006 and, in some examples, to the probe circuit 1008. Additional details regarding the parameter system matrix 1004 are described herein with reference to Figure 11 are described.

[0072] As mentioned, the adapter circuit 1006 is coupled between the parameter system matrix 1004 and the probe circuit 1008. In some examples, the adapter circuit 1006 includes features of the characterization circuit 400, the characterization circuit 500, the characterization circuit 600, the characterization circuit 800, or the characterization circuit 900. The adapter circuit 1006 can be any circuit used to characterize the DUT 1012 of the wafer 1010. Additional details regarding the adapter circuit 1006 are described herein with reference to Figure 11 are described.

[0073] As mentioned, the probe circuit 1008 is coupled between the adapter circuit 1006 and the wafer 1010. In some examples, the probe circuit 1008 can be the DUT interface 58. The probe circuit 1008 can be any circuit used to couple the output 1114 of the adapter circuit 1006 and / or the parameter system matrix 1004 to the DUT 1012 of the wafer 1010. Additional details regarding the probe circuit 1008 are described herein with reference to Figure 11 are described.

[0074] The wafer 1010 may include any number of DUTs 1012. In some examples, the DUT may be a transistor. The DUTs 1012 of the wafer 1010 may include all the same type of power devices, and in other cases, the DUTs 1012 of the wafer 1010 may include multiple types of power devices. In some examples, the probe circuit 1008 is coupled to any number of DUTs 1012 on the wafer 1010. The DUTs 1012 of the wafer 1010 as described in this disclosure are not cut or packaged. Instead, this disclosure relates to testing the DUTs 1012 before cutting and packaging the DUTs 1012.

[0075] Figure 11 An embodiment of a test and measurement system in accordance with an embodiment of the present disclosure is shown. Specifically, in some examples, Figure 11 Additional details and examples of a characterization measurement platform coupled to a wafer for testing are provided. Although Figure 11 the test and measurement system 1100 of Figure 10 illustrates two DUTs 1012 on the wafer 1010 of Figure 11 it, the test and measurement system is coupled to the DUTs 1012 and the wafer 1010 via the probe circuit 1008, although not so illustrated in

[0076] As Figure 11As illustrated, parameter system matrix 1004 is coupled to test and measurement instrument 1002. Test and measurement instrument 1002 includes, but is not limited to, a PMU, an SMU, a ground power supply, and a digital multimeter. Accordingly, parameter system matrix 1004 includes inputs for one or more test and measurement instruments 1002. Parameter system matrix 1004 also includes outputs 1112, 1114 that are coupled to adapter circuit 1006 (and in some examples, are coupled to probe circuit 1008). In some examples, parameter system matrix 1004 is configured to output signals from at least one of test and measurement instruments 1002. For example, parameter system matrix 1004 is configured to provide a first set of signals from one test and measurement instrument 1002 to output 1112 that is coupled to adapter circuit 1006, and a second set of signals from another test and measurement instrument 1002 to output 1114 that is coupled to probe circuit 1008. Accordingly, in such an example, test and measurement system 1000 can perform multiple tests simultaneously. Although test and measurement system 1000 shows parameter system matrix 1004 coupled to only one adapter circuit 1006 and only one other DUT 1012 via outputs 1112, 1114, respectively, test and measurement system 1000 can include any number of adapter circuits 1006 and any number of outputs 1112, 1114 to test any number of DUTs 1012 on wafer 1010.

[0077] As mentioned, adapter circuit 1006 is coupled between parameter system matrix 1004 and probe circuit 1008. Adapter circuit 1006 includes voltage divider 1124, clamping circuit 1126, and at least one buffer circuit 1128. In some examples, adapter circuit 1006 also includes blocking diode 1116, current limiter 1118, replaceable load circuit 1120, capacitor bank 1122, and sense resistor 1130. As Figure 11As illustrated, adapter circuit 1006 includes an input coupled to the output 1112 of parameter system matrix 1004, and the input of adapter circuit 1006 couples the output of the parameter system to blocking diode 1116, voltage divider 1124, clamping circuit 1126, and buffer circuit 1128. Blocking diode 1116 is in turn coupled to current limiter 1118, and current limiter 1118 is coupled to replaceable load circuit 1120 and capacitor bank 1122. Replaceable load circuit 1120 is coupled to the output of adapter circuit 1006. In some examples, replaceable load circuit 1120 includes an inductor and a diode. In other examples, replaceable load circuit 1120 may include other components such that capacitor bank 1122 is coupled to sense resistor 1130 and clamping circuit 1126. Sense resistor 1130 is coupled to the output of adapter circuit 1006 and buffer circuit 1128. Voltage divider 1124 of adapter circuit 1006 is coupled to the clamping circuit and the output of adapter circuit 1006. As mentioned, clamping circuit 1126 is coupled to the input of adapter circuit 1006, voltage divider 1124, and sense resistor 1130, and clamping circuit 1126 is coupled to the output of adapter circuit 1006. As mentioned, buffer circuit 1128 is coupled to the sensing circuit and is also coupled to the output of adapter circuit 1006. In some examples, adapter circuit 1006 also includes another buffer circuit 1128 that is coupled between the input of adapter circuit 1006 and the output of adapter circuit 1006. In some examples, adapter circuit 1006 includes a path directly from the input of adapter circuit 1006 to the output of adapter circuit 1006.

[0078] In some examples, buffer circuit 1128 of adapter circuit 1006 provides protection against high voltages. For example, buffer circuit 1128 of adapter circuit 1006 may protect adapter circuit 1006 from a 3 kV potential. In additional examples, buffer circuit 1128 may provide protection against high voltages by providing a high impedance. In some examples, voltage divider 1124 of adapter circuit 1006 divides the incoming voltage from output 1112 of parameter system matrix 1004 into a smaller voltage for testing DUT 1012. For example, voltage divider 1124 feeds a high voltage (1 kV) from the drain to a PMU that can measure up to 40 V, and thus voltage divider 1124 divides the high voltage from the drain by 25 to feed to the PMU. In some examples, clamping circuit 1126 is configured to clamp the voltage entering clamping circuit 1126, and in such examples, clamping circuit 1126 may clamp the voltage based on a predetermined condition. For example, clamping circuit 1126 clamps the voltage at 30 V.

[0079] In some examples, the clamp circuit 1126 of the adapter circuit 1006 is coupled to the GND power supply and supplies the GND power supply to the remaining circuits inside the adapter circuit 1006. In such examples, the test and measurement system 1100 includes a high-current and low-voltage path between the terminals of the DUT 1012, through the probe circuit 1008 and through the sense resistor 1130 to the GND power supply in the adapter circuit 1006. Similarly, in some examples, the test and measurement system 1100 includes a high-current and high-voltage path between the terminals of the DUT 1012, through the probe circuit 1008, through the replacement load circuit 1120, and through the capacitor bank 1122 to the GND power supply in the adapter circuit 1006. In some examples, the test and measurement system 1100 includes a high-voltage path from the terminals of the DUT 1012 to the voltage divider 1124 and the clamp circuit 1126 of the adapter circuit 1006. In some examples, the test and measurement system 1100 also includes a high-voltage path from one of the outputs 1112 of the parameter system matrix 1004 coupled to the blocking diode 1116, through the blocking diode 1116, through the current limiter 1118, to the node between the replaceable load circuit 1120 and the capacitor bank 1122.

[0080] The probe circuit 1008 includes an input coupled to the output 1114 of the adapter circuit 1006 and the parameter system matrix 1004. The probe circuit 1008 includes ports and / or connections of the DUT 1012 configured to be coupled to the wafer 1010. The signal path of the probe circuit 1008 allows the test and measurement system 1100 to connect to the DUT 1012 for testing. For example, the probe circuit 1008 allows the output 1114 of the parameter system matrix 1004 to be connected to the terminals of the DUT 1012. Similarly, the probe circuit 1008 allows the output of the adapter circuit 1006 to be connected to the terminals of the DUT 1012.

[0081] In some examples, the DUT 1012 has terminals coupled to the terminals DF and DS of the probe circuit 1008. The DUT includes a terminal coupled to the terminal G of the probe circuit 1008, and terminals coupled to the terminals SS and SF of the probe circuit 1008.

[0082] The test and measurement system 1100 as described herein can be used to perform various tests on a DUT 1012 located on a wafer 1010. As previously mentioned, the wafer 1010 is not diced or packaged, and thus the probe circuit 1008 is directly coupled to the DUT 1012 on the wafer 1010. Depending on the tests to be applied to the DUT 1012, the test and measurement instrument 1002 works by performing tests on the DUT 1012 through the parameter system matrix 1004 and the adapter circuit 1006. The tests can include determining dynamic tests for double pulse, breakdown, leakage, and threshold voltage measurements. The tests performed on the DUT 1012 comply with the Joint Electron Device Engineering Council (JEDEC) standards.

[0083] Figure 12 is a flowchart of testing a power device on a wafer using a test and measurement system according to some examples. This flowchart shows a process 1200 with operations 1202 and 1204. Operation 1202 of process 1200 involves coupling a test and measurement system (e.g., Figure 11 the test and measurement system 1100) to a DUT (e.g., DUT 1012) of a wafer (e.g., wafer 1010). In some examples, coupling the test and measurement system to the DUT involves coupling the probe circuit of the test and measurement system to the terminals of the DUT. Figure 11 Operation 1204 of process 1200 involves performing tests on the DUT using the test and measurement system. As previously mentioned, the DUT to which the test and measurement system is coupled is not separated from the rest of the wafer. That is, the DUT is not diced or packaged, and thus when performing any tests on the DUT, the test and measurement system needs to carefully apply test signals to the DUT under test without affecting other devices on the wafer. The tests can include determining dynamic

[0084] tests for double pulse, breakdown, leakage, and threshold voltage measurements. This disclosure relates to combining a parameter system and / or a semiconductor characterization system with power device measurements. This disclosure also relates to including dedicated pins for low voltage and / or low current measurements and other pins for power device evaluation on the probe circuit. In some examples, the probe circuit includes at least two low current and low voltage input pins. This disclosure relates to replacing an oscilloscope with a PMU from a characterization system, which allows for fast voltage transient forcing and measurement, and which implements the gate drive function for both dynamic testing and measurement.

[0085]

[0086] ​Aspects of the present disclosure may operate on specially created hardware, firmware, digital signal processors, or general-purpose computers that are specially programmed to include a processor operating in accordance with programming instructions. As used herein, the terms controller or processor are intended to include microprocessors, microcomputers, application specific integrated circuits (ASICs), and dedicated hardware controllers. One or more aspects of the present disclosure may be embodied in computer-usable data and computer-executable instructions, such as in one or more program modules, and executed by one or more computers, including monitoring modules, or other devices. In general, program modules include routines, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types when executed by a processor or other device in a computer. Computer-executable instructions may be stored on a non-transitory computer-readable medium, such as a hard disk, optical disk, removable storage medium, solid state memory, random access memory (RAM), etc. As will be appreciated by those skilled in the art, the functionality of program modules may be combined or distributed as desired in various aspects. In addition, the functionality may be embodied in whole or in part in firmware or hardware equivalents, such as integrated circuits, FPGAs, etc. Particular data structures may be used to more effectively implement one or more aspects of the present disclosure, and such data structures are considered to be within the scope of the computer-executable instructions and computer-usable data described herein.

[0087] In some instances, the disclosed aspects may be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried or stored on one or more non-transitory computer-readable media, which may be read and executed by one or more processors. Such instructions may be referred to as a computer program product. As discussed herein, computer-readable media means any media that can be accessed by a computing device. By way of example and not limitation, computer-readable media may include computer storage media and communication media.

[0088] Computer storage media means any media that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital video disc (DVD) or other optical disc storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, and any other volatile or non-volatile, removable or non-removable media implemented in any technology. Computer storage media does not include signals per se and transient forms of signal transmissions.

[0089] A communication medium means any medium that can be used for the transmission of computer-readable information. By way of example and not limitation, a communication medium can include coaxial cable, fiber optic cable, air, or any other medium suitable for transmitting electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals.

[0090] In addition, the written description refers to specific features. It should be understood that the disclosure in this specification includes all possible combinations of those specific features. For example, where a specific feature is disclosed in the context of a particular aspect, that feature can also be used, to the extent possible, in the context of other aspects.

[0091] In addition, when referring in this application to a method having two or more defined steps or operations, the defined steps or operations can be implemented in any order or simultaneously, unless the context excludes those possibilities.

[0092] Examples

[0093] Illustrative examples of the disclosed technology are provided below. Embodiments of the technology can include one or more of the following examples and any combination of the following examples.

[0094] Example 1 is a system for characterizing a power device, including: a parameter system matrix coupled to one or more test and measurement instruments; an adapter circuit coupled to the parameter system matrix, the adapter circuit including a voltage clamping circuit coupled to the parameter system matrix; and a probe circuit coupled to the adapter circuit and the power device, wherein the power device is located on a wafer.

[0095] Example 2 is the system of Example 1, wherein the parameter system matrix is coupled to the probe circuit.

[0096] Example 3 is the system of Example 1 or Example 2, wherein the wafer can include multiple power devices, and the power device is one of the multiple power devices on the wafer.

[0097] Example 4 is the system of any one of Examples 1 to 3, wherein the adapter circuit can include a first plurality of inputs and a first plurality of outputs, wherein the first plurality of inputs are coupled to a second plurality of outputs from the parameter system matrix, and the first plurality of outputs are coupled to a second plurality of inputs of the probe circuit.

[0098] Example 5 is the system of any one of Examples 1 to 4, wherein one or more of the test and measurement instruments can include a pulse measurement unit configured to generate pulses and perform dynamic current and voltage measurements.

[0099] Example 6 is the system of any one of Examples 1 to 5, wherein the adapter circuit is configured to determine the dynamic drain-source on-resistance for the power device.

[0100] Example 7 is a system of any one of Examples 1 to 6, wherein the adapter circuit may include a voltage divider circuit and one or more voltage protection circuits.

[0101] Example 8 is a system of any one of Examples 1 to 7, wherein the probe circuit may include at least two low-current and low-voltage input pins.

[0102] Example 9 is a system of any one of Examples 1 to 8, wherein the adapter circuit may include a blocking diode, a current limiter, a replaceable load circuit, a capacitor, and a sense resistor.

[0103] Example 10 is a system of any one of Examples 1 to 9, wherein the replaceable load circuit is coupled to the power device through the probe circuit, and the replaceable load circuit is serially coupled to the current limiter and the blocking diode.

[0104] Example 11 is a system of any one of Examples 1 to 10, wherein the capacitor and the sense resistor are serially coupled to the power device through the probe circuit.

[0105] Example 12 is a system of any one of Examples 1 to 11, wherein a voltage clamping circuit is coupled to the sense resistor, and the sense resistor is coupled to the power device through the probe circuit, wherein the availability and functionality of the voltage clamping circuit enable accurate dynamic drain-source on-resistance measurement.

[0106] Example 13 is a system of any one of Examples 1 to 12, wherein the system is configured to run at least one test on a wafer, and the at least one test may include a dynamic drain-source on-resistance test, a double-pulse test, a breakdown test, a leakage test, or a threshold voltage test.

[0107] Example 14 is a system of any one of Examples 1 to 13, wherein the power device is a first power device, the parameter system matrix is coupled to a second power device of the wafer, and the system is configured to perform a first test on the first power device and a second test on the second power device simultaneously.

[0108] Example 15 is a system of any one of Examples 1 to 14, wherein the power device is a transistor.

[0109] Example 16 is a system of any one of Examples 1 to 15, wherein the adapter circuit is configured to perform tests on the power device using Joint Electron Device Engineering Council (JEDEC) standards.

[0110] Example 17 is a system of any one of Examples 1 to 16, further including a parameter system having a parameter system matrix.

[0111] Example 18 is a system of any one of Examples 1 to 17, wherein the parameter system is configured to implement data analysis and parameter extraction using an adapter circuit and a probe circuit.

[0112] Example 19 is a method for testing a power device, including: coupling a probe circuit to a power device of a wafer, wherein the probe circuit is coupled to an adapter circuit, and the adapter circuit is coupled to a parameter system matrix; and performing a test on the power device by sending a signal through the parameter system matrix and through the adapter circuit to the probe circuit.

[0113] Example 20 is the method of Example 19, wherein the test can include a dynamic drain-source on-resistance test, a double-pulse test, a breakdown test, a leakage test, or a threshold voltage test.

[0114] The foregoing description has been presented only to illustrate the example embodiments of the present disclosure and is not intended to be limiting. Since modifications to the disclosed embodiments that incorporate the substance of the present invention can be envisioned by those skilled in the art, the present invention should be construed to cover all such modifications within the scope of the present invention.

[0115] The previously described versions of the disclosed subject matter have many advantages, which have been described or are obvious to those of ordinary skill in the art. Nevertheless, these advantages or features are not required in all versions of the disclosed apparatus, system, or method.

[0116] Additionally, the written description refers to specific features. It should be understood that all features disclosed in the specification (including the claims, abstract, and drawings), as well as all steps in any method or process disclosed, can be combined in any combination, except for combinations in which at least some of such features and / or steps are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in the specification (including the claims, abstract, and drawings) can be replaced by an alternative feature for the same, equivalent, or similar purpose.

[0117] Furthermore, when referring in this application to a method having two or more defined steps or operations, the defined steps or operations can be implemented in any order or simultaneously, unless the context excludes those possibilities.

[0118] Although specific examples of the present disclosure have been illustrated and described for purposes of illustration, it will be understood that various modifications can be made without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure should not be limited except as by the appended claims.

Claims

1. A system for characterizing a power device, comprising: A parameter system matrix coupled to one or more test and measurement instruments; An adapter circuit coupled to the parameter system matrix, the adapter circuit including a voltage clamping circuit coupled to the parameter system matrix; And A probe circuit coupled to the adapter circuit and the power device, wherein the power device is located on a wafer.

2. The system according to claim 1, wherein the parameter system matrix is coupled to the probe circuit.

3. The system according to claim 1, wherein the wafer includes a plurality of power devices, and the power device is one of the plurality of power devices on the wafer.

4. The system according to claim 1, wherein the adapter circuit includes a first plurality of inputs and a first plurality of outputs, wherein the first plurality of inputs are coupled to a second plurality of outputs from the parameter system matrix, and the first plurality of outputs are coupled to a second plurality of inputs for the probe circuit.

5. The system according to claim 1, wherein the one or more test and measurement instruments include a pulse measurement unit configured to generate pulses and perform dynamic current and voltage measurements.

6. The system according to claim 1, wherein the adapter circuit is configured to determine the dynamic drain-source on-resistance of the power device.

7. The system according to claim 1, wherein the adapter circuit includes a voltage divider circuit and one or more voltage protection circuits.

8. The system according to claim 1, wherein the probe circuit includes at least two low-current and low-voltage input pins.

9. The system according to claim 1, wherein the adapter circuit includes a blocking diode, a current limiter, a replaceable load circuit, a capacitor, and a sense resistor.

10. The system according to claim 9, wherein the replaceable load circuit is coupled to the power device through the probe circuit, and the replaceable load circuit is serially coupled to the current limiter and the blocking diode.

11. The system according to claim 9, wherein the capacitor and the sense resistor are serially coupled to the power device through the probe circuit.

12. The system according to claim 9, wherein the voltage clamping circuit is coupled to the sense resistor, and the sense resistor is coupled to the power device through the probe circuit, and the availability and functionality of the voltage clamping circuit enable accurate dynamic drain-source on-resistance measurement.

13. The system according to claim 1, wherein the system is configured to perform at least one test on the wafer, wherein the at least one test includes a dynamic drain-source on-resistance test, a double-pulse test, a breakdown test, a leakage test, or a threshold voltage test.

14. The system according to claim 1, wherein the power device is a first power device, the parameter system matrix is coupled to a second power device on the wafer, and the system is configured to perform a first test on the first power device and a second test on the second power device simultaneously.

15. The system according to claim 1, wherein the power device is a transistor.

16. The system according to claim 1, wherein the adapter circuit is configured to perform tests on the power device using Joint Electron Device Engineering Council (JEDEC) standards.

17. The system according to claim 1 further includes a parameter system having the parameter system matrix.

18. The system according to claim 17, wherein the parameter system is configured to perform data analysis and parameter extraction using the adapter circuit and the probe circuit.

19. A method for testing a power device, comprising: coupling a probe circuit to a power device of a wafer, wherein the probe circuit is coupled to an adapter circuit, and the adapter circuit is coupled to a parameter system matrix; and performing a test on the power device by sending a signal through the parameter system matrix and through the adapter circuit to the probe circuit.

20. The method according to claim 19, wherein the test includes a dynamic drain-source on-resistance test, a double-pulse test, a breakdown test, a leakage test, or a threshold voltage test.

Images