MEMS deformable mirror based on double-layer electrode cooperative etching and its preparation method

Abstract

The present invention discloses a MEMS deformable mirror based on double-layer electrode cooperative etching and a preparation method thereof, which belongs to the micro-nano processing technology of deformable mirror structure. The preparation method is realized by the following steps: etching alignment marks on the back of the substrate; depositing a silicon nitride insulating layer on the front of the silicon wafer substrate, opening the back solution etching window; completing the cooperative etching of the double-layer polysilicon electrode in sequence, and synchronously forming interdigitated electrodes, honeycomb stress holes and spiral guide grooves; achieving lossless structure release through mechanical thinning and back hole directional etching; finally, sputtering a metal reflective layer and implementing an annealing process after vacuum bonding and packaging. The present invention solves the problems of low etching solution diffusion efficiency and high structural adhesion rate in traditional processes by optimizing the electrode etching coordination and the post-reflector process, and introducing back hole release technology, thereby significantly improving the mirror surface roughness and release yield, and is suitable for the manufacture of high-precision adaptive optical systems.

Description

Technical Field

[0001] The present invention relates to a micro-nano processing technology for a deformable mirror structure, and in particular to a MEMS deformable mirror based on double-layer electrode cooperative etching and a preparation method thereof. Background Art

[0002] The manufacturing technology of microelectromechanical system (MEMS) deformable mirrors is a core challenge in the field of adaptive optics, and its performance directly affects the accuracy of beam wavefront correction. Traditional processes use step-by-step deposition and etching methods to prepare multilayer electrode structures. The main processes include substrate cleaning, insulating layer deposition, electrode photolithography, sacrificial layer release, and reflective mirror coating. However, this type of process has the following technical defects: during the wet etching process, the reflective layer is exposed to the etching liquid environment for a long time, resulting in an increase in residual surface defects, increased mirror roughness, and a significant attenuation of optical reflection performance; the difference in thermal expansion coefficients between the electrode material and the reflective layer causes interfacial stress accumulation, and the mirror deformation error increases after annealing; the single-channel backhole design limits the diffusion efficiency of the etching liquid, resulting in frequent adhesion problems of the movable structure. At the same time, the preparation of multilayer electrodes requires multiple photolithography mask alignments, which is highly complex and seriously restricts the mass production yield.

[0003] While existing improvements attempt to mitigate these issues by adjusting sacrificial layer materials or optimizing etching processes, they still face challenges such as insufficient synergy between electrode etching and backhole release, low precision in controlling stress-release hole morphology, and reduced solution transfer efficiency. Furthermore, while the simultaneous annealing of the reflective and electrode layers can reduce thermal stress deformation, etching solution penetration increases the density of mirror defects, making it difficult to meet the stringent optical surface quality requirements of high-power laser systems.

[0004] The above technical bottlenecks indicate that there is an urgent need for a MEMS deformable mirror manufacturing method that can achieve coordinated control of electrode morphology, backhole directional etching, and low-temperature and high-reliability packaging integration, so as to break through the balance limitations of existing processes between optical performance and structural reliability. Summary of the Invention

[0005] Purpose of the invention: In response to the above problems, the purpose of the present invention is to provide a MEMS deformable mirror based on double-layer electrode collaborative etching and a preparation method thereof, and to achieve a dual improvement in optical performance and structural reliability by optimizing the electrode etching synchronization, back hole directional etching and mirror post-process.

[0006] Technical solution: On one hand, the present invention provides a MEMS deformable mirror based on double-layer electrode cooperative etching, comprising:

[0007] A silicon wafer substrate, a silicon nitride insulating layer arranged on the silicon wafer substrate, a first interdigital electrode arranged on the silicon nitride insulating layer, an in-situ doped polysilicon layer arranged on the first interdigital electrode, a second interdigital electrode, stress relief holes and solution diversion grooves are etched on the in-situ doped polysilicon layer, a polysilicon support structure is arranged on the second interdigital electrode, and a gold-based reflective mirror is arranged on the polysilicon support structure.

[0008] Furthermore, the thickness of the silicon nitride insulating layer is 200-500 nanometers.

[0009] Furthermore, the thickness of the first interdigital electrode is 0.5-1.5 microns.

[0010] Furthermore, the stress release holes are a honeycomb array with a pore diameter of 10 to 30 microns.

[0011] Furthermore, the width of the solution diversion groove is 2 to 5 microns.

[0012] Furthermore, the polysilicon support structure is a columnar array with a diameter of 10 to 20 microns and a support density of 50 to 200 per mm².

[0013] Another aspect of the present invention provides a method for preparing a MEMS deformable mirror based on double-layer electrode cooperative etching, comprising the following steps:

[0014] Step 1: Clean the silicon wafer substrate and etch alignment marks on the back side of the silicon wafer substrate;

[0015] Step 2: depositing a silicon nitride insulating layer on the front side of the silicon wafer substrate and opening a backside solution etching window;

[0016] Step 3: depositing a polysilicon layer on the front surface of the silicon nitride insulating layer, and patterning it after thinning and ion implantation to form a first interdigitated electrode;

[0017] Step 4: depositing a first phosphosilicate glass sacrificial layer on the front surface of the first interdigital electrode and performing a thinning process;

[0018] Step 5: depositing an in-situ doped polysilicon layer on the front surface of the first phosphosilicate glass sacrificial layer, thinning it, and then simultaneously etching it to form a second interdigitated electrode, stress relief holes, and solution diversion grooves;

[0019] Step 6: depositing a second sacrificial layer of phosphosilicate glass on the front surface of the in-situ doped polysilicon layer, and selectively removing the lead area;

[0020] Step 7, depositing and patterning a polysilicon support structure on the front surface of the second phosphosilicate glass sacrificial layer;

[0021] Step 8, mechanically thinning the back side of the silicon wafer substrate to a target thickness;

[0022] Step 9, etching the silicon wafer substrate to the first phosphosilicate glass sacrificial layer deposited on the front surface of the first interdigital electrode in step 4 according to the position of the back solution etching window formed in step 2;

[0023] Step 10, removing the first phosphosilicate glass sacrificial layer and the second phosphosilicate glass sacrificial layer to complete the structure release;

[0024] Step 11: sputter a metal reflective layer on the front of the polysilicon support structure and pattern it to form a gold-based reflective mirror surface, perform an annealing process, and perform vacuum bonding and packaging.

[0025] Furthermore, the thickness of the first phosphosilicate glass sacrificial layer and the second phosphosilicate glass sacrificial layer are both 1 to 3 microns.

[0026] Furthermore, the cone angle of the solution-etched window in step 2 is 54.7°±2°.

[0027] Furthermore, in step 9, anisotropic wet etching is performed using a TMAH solution with a mass fraction of 20% to 30%, and the etching temperature is 70 to 90° C.

[0028] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages:

[0029] 1. The present invention uses a double-layer electrode collaborative etching technology to simultaneously form interdigitated electrodes, honeycomb stress holes, and spiral guide grooves, reducing the number of photolithography mask alignments from 7 to 4, increasing the mass production yield to over 92%, improving the etching solution diffusion efficiency by 60%, and reducing the structural adhesion rate to less than 5%;

[0030] 2. This invention adopts the method of sputtering a metal reflective layer followed by an annealing process and vacuum bonding packaging. The mirror surface roughness RMS is stable at 0.2-0.3nm, the surface residual particle density is less than 10 particles / cm², and the reflectivity attenuation is less than 3%, breaking through the bottleneck of high-power laser optical surface quality.

[0031] 3. The present invention innovatively combines mechanical thinning to 200-400μm with TMAH directional etching to a cone angle of 54.7°±2° to achieve precise control of the distance between the backhole end and the sacrificial layer to less than 10μm. Combined with the polysilicon support column array, the curvature deviation of the mirror after packaging is less than 0.8%;

[0032] 4. The present invention utilizes a sacrificial layer of phosphosilicate glass in combination with gaseous hydrogen fluoride etching, which improves etching uniformity by 35%, reduces stress accumulation in the electrode layer by 80%, and reduces the fracture rate of the support structure from 15% to 0.5%. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of the structure of the MEMS deformable mirror;

[0034] Figure 2 Schematic diagram of the silicon wafer substrate pretreatment structure in step 1;

[0035] Figure 3 Schematic diagram of the silicon nitride insulating layer and back hole forming structure in step 2;

[0036] Figure 4 This is a schematic diagram of the first interdigitated electrode structure in step 3;

[0037] Figure 5 Schematic diagram of the phosphosilicate glass sacrificial layer processing structure in step 4;

[0038] Figure 6 Schematic diagram of the collaborative etching structure in step 5;

[0039] Figure 7 Schematic diagram of the phosphosilicate glass sacrificial layer structure in step 6;

[0040] Figure 8 This is a schematic diagram of the polysilicon support structure in step 7;

[0041] Figure 9 Schematic diagram of the silicon wafer substrate thinning structure in step 8;

[0042] Figure 10 Schematic diagram of the back hole etching structure in step 9;

[0043] Figure 11 Release diagram for the structure of step 10.

[0044] In the figure, 1 is the silicon wafer substrate; 2 is the silicon nitride insulating layer; 3 is the first interdigitated electrode; 4 is the first phosphosilicate glass sacrificial layer; 5 is the in-situ doped polysilicon layer; 6 is the second phosphosilicate glass sacrificial layer; 7 is the polysilicon support structure; and 8 is the gold-based reflective mirror. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of this application more clear, this application is further described in detail below with reference to the accompanying drawings and embodiments.

[0046] Example 1

[0047] Combine Figure 1 As shown, the MEMS deformable mirror based on double-layer electrode cooperative etching described in this embodiment includes:

[0048] A silicon wafer substrate 1, a silicon nitride insulating layer 2 arranged on the silicon wafer substrate 1, a first interdigitated electrode 3 arranged on the silicon nitride insulating layer 2, an in-situ doped polysilicon layer 5 arranged on the first interdigitated electrode 3, a second interdigitated electrode, stress relief holes and solution diversion grooves are etched on the in-situ doped polysilicon layer 5, a polysilicon support structure 7 is arranged on the second interdigitated electrode, and a gold-based reflective mirror 8 is arranged on the polysilicon support structure 7.

[0049] Furthermore, the thickness of the silicon nitride insulating layer is 200-500 nanometers.

[0050] Furthermore, the thickness of the first interdigital electrode is 0.5-1.5 microns.

[0051] Furthermore, the stress release holes are a honeycomb array with a pore diameter of 10 to 30 microns.

[0052] Furthermore, the width of the solution diversion groove is 2 to 5 microns.

[0053] Furthermore, the polysilicon support structure is a columnar array with a diameter of 10 to 20 microns and a support density of 50 to 200 per mm².

[0054] Example 2

[0055] The method for preparing a MEMS deformable mirror based on double-layer electrode cooperative etching described in this embodiment includes the following steps:

[0056] Combine Figure 2 , step 1, clean the silicon wafer substrate 1, and etch an alignment mark on the back side of the silicon wafer substrate 1.

[0057] A 6-inch double-sided polished n-type silicon wafer can be used. After treatment with a specially formulated cleaning solution, the surface particle density is less than 10 particles / cm². Deep reactive ion etching is then used to form alignment marks with a depth of 5 to 15 μm on the backside. A fluorine-based mixed gas is used as the etching gas, and the sidewall steepness is controlled at 88° ± 2°.

[0058] Combine Figure 3 , step 2, depositing a silicon nitride insulating layer 2 on the front side of the silicon wafer substrate 1, and opening a back side solution etching window.

[0059] A 200-500nm thick silicon nitride insulating layer (2) with a dielectric strength greater than 10 MV / cm is deposited on the front of a silicon wafer substrate (1) using plasma-enhanced chemical vapor deposition. An anisotropic wet etchant is used to form a solution channel window with a cone angle of 54.7°±2° on the back of the silicon wafer substrate (1). The etching endpoint is monitored in real time using an optical interferometer.

[0060] Combine Figure 4In step 3, a polysilicon layer is deposited on the front surface of the silicon nitride insulating layer 2, and patterned to form a first interdigitated electrode 3 after thinning and ion implantation.

[0061] After depositing a 2~3μm polysilicon layer on the front of the silicon nitride insulating layer 2, a special polishing solution is used for chemical mechanical polishing to thin it to 0.5~1.5μm. Then, boron ion implantation is performed with a dose of After annealing, an interdigitated electrode array with a square resistance of less than 50Ω / sq is formed.

[0062] Combine Figure 5 In step 4, a first phosphosilicate glass sacrificial layer 4 is deposited on the front surface of the first interdigitated electrode 3 and thinned.

[0063] A 2-4 μm first phosphosilicate glass sacrificial layer 4 is grown on the front surface of the first interdigitated electrode 3 using low-pressure chemical vapor deposition. The phosphorus doping concentration is optimized to enhance etch selectivity. Chemical mechanical polishing is then used to thin the layer to 1-3 μm, with a thickness uniformity of less than ±3%. The thickness of the first phosphosilicate glass sacrificial layer is 1-3 μm.

[0064] Combine Figure 6 In step 5, an in-situ doped polysilicon layer 5 is deposited on the front of the first phosphosilicate glass sacrificial layer 4, and after thinning, a second interdigitated electrode, a stress release hole and a solution diversion groove are formed by simultaneous etching.

[0065] A 2-5 μm thick in-situ doped polysilicon layer 5 is deposited on the front surface of the first phosphosilicate glass sacrificial layer 4. Deep reactive ion etching (DRE) is then used to simultaneously etch the second interdigitated electrode, honeycomb stress holes, and spiral guide grooves. The etching selectivity is controlled within the range of 20:1 to 40:1 using a specific gas ratio. The honeycomb hole aspect ratio is 1:3 to 1:5, and the guide groove helix angle is 30° to 60°. The etching endpoint is monitored in real time using optical emission spectroscopy. The honeycomb stress holes have a diameter of 10-30 μm, and the spiral guide grooves have a width of 2-5 μm.

[0066] Combine Figure 7 , step 6, depositing a second phosphosilicate glass sacrificial layer 6 on the front of the in-situ doped polysilicon layer 5, and selectively removing the lead area.

[0067] A second phosphosilicate glass sacrificial layer 6 is deposited on the front surface of the in-situ doped polysilicon layer 5 using low-pressure chemical vapor deposition (LPCVD). The layer is then thinned to 1-3 μm using reactive ion etching (RIE). The etching selectivity is greater than 50:1, and the surface roughness Ra is less than 5 nm. The thickness of the second phosphosilicate glass sacrificial layer is 1-3 μm.

[0068] Combine Figure 8 , step 7, depositing and patterning a polysilicon support structure 7 on the front side of the second phosphosilicate glass sacrificial layer 6.

[0069] A polysilicon support column array with a diameter of 10-20 μm is photolithographically formed on the front side of the second phosphosilicate glass sacrificial layer 6, with a support density of 50-200 columns / mm², a height consistency error of less than ±5%, and a Young's modulus of 160-180 GPa.

[0070] Combine Figure 9 In step 8, mechanical thinning is performed on the back side of the silicon wafer substrate 1 to a target thickness.

[0071] The back side of the silicon wafer substrate 1 is roughly ground to 200-400 μm using a diamond grinding wheel, and then subjected to chemical mechanical polishing to reduce the surface roughness Ra to less than 10 nm and the surface damage layer to less than 50 nm.

[0072] Combine Figure 10 Step 9: etching the silicon wafer substrate to the first phosphosilicate glass sacrificial layer 4 deposited on the front side of the first interdigital electrode in step 4 according to the back solution etching window position formed in step 2;

[0073] Use 20-30wt% TMAH solution at a temperature of 70-90°C to etch the back hole of the silicon wafer substrate with a flow rate of 5-15mL / min. Monitor the etching end point with an infrared sensor to ensure that the end is less than 10μm from the phosphosilicate glass sacrificial layer.

[0074] Combine Figure 11 , step 10, removing the first phosphosilicate glass sacrificial layer 4 and the second phosphosilicate glass sacrificial layer 6 to complete the structure release.

[0075] The first phosphosilicate glass sacrificial layer 4 and the second phosphosilicate glass sacrificial layer 6 are completely removed by etching with gaseous hydrogen fluoride at 40-60 sccm and 80-100° C., with an etching uniformity greater than 95% and a release time of 30-60 minutes.

[0076] Combine Figure 1 In step 11, a metal reflective layer is sputtered on the front of the polysilicon support structure 7 and patterned to form a gold-based reflective mirror 8, an annealing process is performed, and vacuum bonding and packaging are performed.

[0077] On the front side of the polysilicon support structure 7, a 150-300nm gold-based reflective layer is magnetron sputtered, including a 5-10nm transition layer, and annealed at 300-400℃ to form a mirror with an RMS of less than 0.3nm. Wafer-level bonding is completed under a vacuum degree of Pa.

[0078] Example 3

[0079] The method for preparing a MEMS deformable mirror based on double-layer electrode cooperative etching described in this embodiment differs from that in the second embodiment in that:

[0080] (1) Substrate specifications: 8-inch silicon wafer, backhole taper angle controlled to 54.7°±1.5°;

[0081] (2) Sacrificial layer material: boron phosphosilicate glass with boron / phosphorus doping concentration of 2~5wt%;

[0082] (3) Etching process: Step 5 uses time-modulated deep reactive ion etching, and the etching rate ratio is increased to 35:1;

[0083] (4) Packaging optimization: The bonding temperature is increased to 220~250℃ and the pressure is controlled at 5~10MPa.

[0084] Example 4

[0085] The method for preparing a MEMS deformable mirror based on double-layer electrode cooperative etching described in this embodiment differs from that in the second embodiment in that:

[0086] (1) Electrode material: The first interdigital electrode adopts a polysilicon / tungsten composite structure with a thickness of 0.8~1.2μm;

[0087] (2) Design of flow guide groove: fractal groove is used instead of spiral structure, the groove width is 1.5~3μm, and the number of fractal iterations is 3~5 times;

[0088] (3) Detection technology: In step 9, electronic speckle pattern interferometry technology is introduced to reconstruct the etching stress distribution in real time through laser speckle pattern displacement field analysis;

[0089] (4) Optimization of the reflective layer: Au / ITO composite reflective layer is used, and the reflectivity in the visible light band is greater than 99%.

Claims

1. A method for preparing a MEMS deformable mirror based on double-layer electrode cooperative etching, characterized in that: The following steps are involved: Step 1: Clean the silicon wafer substrate and etch alignment marks on the back side of the silicon wafer substrate; Step 2: depositing a silicon nitride insulating layer on the front side of the silicon wafer substrate and opening a solution etching window on the back side; the cone angle of the solution etching window is 54.7°±2°; Step 3: depositing a polysilicon layer on the front surface of the silicon nitride insulating layer, and patterning it after thinning and ion implantation to form a first interdigitated electrode; Step 4: depositing a first phosphosilicate glass sacrificial layer on the front surface of the first interdigital electrode and performing a thinning process; Step 5: depositing an in-situ doped polysilicon layer on the front surface of the first phosphosilicate glass sacrificial layer, thinning it, and then simultaneously etching it to form a second interdigitated electrode, stress relief holes, and solution diversion grooves; Step 6: depositing a second sacrificial layer of phosphosilicate glass on the front surface of the in-situ doped polysilicon layer, and selectively removing the lead area; Step 7, depositing and patterning a polysilicon support structure on the front surface of the second phosphosilicate glass sacrificial layer; Step 8: Mechanically thinning the back side of the silicon wafer substrate to 200-400 μm; Step 9, etching the silicon wafer substrate to the first phosphosilicate glass sacrificial layer deposited on the front surface of the first interdigital electrode in step 4 according to the position of the back solution etching window formed in step 2; Step 10, removing the first phosphosilicate glass sacrificial layer and the second phosphosilicate glass sacrificial layer to complete the structure release; Step 11: sputter a metal reflective layer on the front of the polysilicon support structure and pattern it to form a gold-based reflective mirror surface, perform an annealing process, and perform vacuum bonding and packaging.

2. The method for preparing a MEMS deformable mirror based on double-layer electrode cooperative etching according to claim 1, characterized in that: The thickness of the first phosphosilicate glass sacrificial layer and the second phosphosilicate glass sacrificial layer are both 1-3 microns.

3. The method for preparing a MEMS deformable mirror based on double-layer electrode cooperative etching according to claim 1, characterized in that: In step 9, anisotropic wet etching is performed using a TMAH solution with a mass fraction of 20% to 30% at an etching temperature of 70 to 90° C.

4. A MEMS deformable mirror manufactured according to the method for manufacturing a MEMS deformable mirror based on double-layer electrode cooperative etching according to any one of claims 1 to 3, characterized in that: include: A silicon wafer substrate, a silicon nitride insulating layer arranged on the silicon wafer substrate, a first interdigital electrode arranged on the silicon nitride insulating layer, an in-situ doped polysilicon layer arranged on the first interdigital electrode, a second interdigital electrode, stress relief holes and solution diversion grooves are etched on the in-situ doped polysilicon layer, a polysilicon support structure is arranged on the second interdigital electrode, and a gold-based reflective mirror is arranged on the polysilicon support structure.

5. The MEMS deformable mirror according to claim 4, wherein: The thickness of the silicon nitride insulating layer is 200~500 nanometers.

6. The MEMS deformable mirror according to claim 4, wherein: The thickness of the first interdigital electrode is 0.5-1.5 microns.

7. The MEMS deformable mirror according to claim 4, wherein: The stress relief holes are a honeycomb array with a pore size of 10 to 30 microns.

8. The MEMS deformable mirror according to claim 4, wherein: The width of the solution diversion groove is 2~5 microns.

9. The MEMS deformable mirror according to claim 4, wherein: The polysilicon support structure is a columnar array with a diameter of 10 to 20 microns and a support density of 50 to 200 per mm².

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