PLC system control method, device and storage medium based on dynamic address allocation

Abstract

The application relates to the technical field of industrial automation, in particular to a PLC system control method, device and storage medium based on dynamic address allocation, which comprises the following steps: S1: a CPU module acquires the physical ID of an IO module; S2: a unique logical address is generated for each physical ID, and a mapping database is established; S3: the CPU module performs handshaking by taking the physical ID of the IO module as a communication identifier, and distributes the corresponding logical address to the corresponding IO module as a dynamic address; and S4: in the running process, the CPU module monitors the online state of the IO module through a heartbeat detection mechanism, releases the dynamic logical address of the offline IO module and updates the mapping database, and if a new IO module is online, the CPU module allocates an unoccupied logical address to the new IO module according to the physical ID number of the new IO module. The application generates a unique logical address for the physical ID, improves the safety of the IO module, re-distributes the dynamic address after the online of the new IO module, improves the address allocation flexibility, releases the physical ID and the dynamic address of the offline IO module, and saves the limited address resources.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of industrial automation, and in particular to a PLC system control method, device and storage medium based on dynamic address allocation. BACKGROUND

[0002] PLC (Programmable Logic Controller) is an industrial control device that has developed rapidly and been widely applied since the 1960s. It is one of the three pillars of modern industrial automation. It uses programmable memory to store user instructions and completes certain logic, sequence, timing, counting, arithmetic and certain functions through digital or analog input / output to control various types of mechanical equipment or production processes. The functional modules in the PLC system are designed in a modular manner, and the CPU and IO modules communicate through a backplane bus. The IO modules need to be assigned module addresses through the backplane bus communication mode in order to realize data communication between the CPU module and the IO module.

[0003] The prior art has made many attempts on PLC address allocation. In the application with the application publication number CN114935909A and the name of "PLC system and hand-in-hand configuration method", the controller and the IO module communicate through an IO for hand-in-hand configuration. The IO module accumulates the address after receiving the message sent by the previous IO module, but this method needs to arrange an additional configuration IO line on the hardware, and the address allocation is accumulated one by one, which is fixed. When a certain IO module fails, the address allocation of all subsequent IO modules fails.

[0004] In the application with the application publication number CN108897277B and the name of "PLC independent IO module address automatic allocation method and structure", each slot of the bottom plate has a fixed address, and the address of each IO module is allocated through a hardware method. This method limits the flexibility of backplane communication. SUMMARY

[0005] The purpose of the present application is to solve the problems existing in the prior art, and to provide a PLC system control method based on dynamic address allocation, comprising the following steps:

[0006] S1: After the PLC system is powered on, the CPU module obtains the unique physical ID of the ARM chip of the IO module through the communication bus, and stores the physical ID in the central database;

[0007] S2: The CPU module calls a true random number generator to generate a unique logical address for each physical ID, establishes a mapping database of the physical ID and the logical address, and records information such as address state, last communication timestamp and unresponsive number counter;

[0008] S3: The CPU module performs handshake with the IO module through the communication bus, taking the physical ID of the IO module as the communication identifier, and assigns the corresponding logical address as a dynamic address to the corresponding IO module, thereby completing address binding and communication handshake.

[0009] S4: During system operation, the CPU module monitors the online state of the IO module through a heartbeat detection mechanism. If an IO module goes offline, the dynamic logical address of the offline IO module is released and the mapping database is updated. If a new IO module goes online, the CPU module assigns an unoccupied logical address to the new IO module according to its physical ID number, and updates the central database, the mapping database, and the communication binding.

[0010] Preferably, in step S2, the CPU module calls a true random number generator to generate a unique logical address for each physical ID, further comprising:

[0011] The CPU module calls a true random number generator to generate a random number for each physical ID.

[0012] The CPU module checks whether the newly generated random number has been assigned by traversing the mapping database. If it has not been assigned, it is assigned. If it has been assigned, it is handled through an exception handling mechanism.

[0013] When the generated random number meets the uniqueness requirement, the physical ID is associated with the corresponding logical address, the mapping database is updated, and the address state is recorded as assigned and the current last communication timestamp.

[0014] Preferably, in step S4, the CPU module monitors the online state of the IO module through a heartbeat detection mechanism, including:

[0015] The CPU module periodically sends a heartbeat request to the IO module. If a certain IO module returns a response within a specified time, the CPU module resets the non-response count counter of the IO module to 0 and updates the last communication timestamp of the module in the database. If a certain IO module does not return a response within a specified time, the CPU module increments the non-response count counter of the module by 1.

[0016] The CPU module checks the value of the continuous non-response count counter of the IO module. If the non-response count counter value exceeds a preset threshold, it is determined to be offline. When a new IO module accesses the system, the IO module sends a registration request of its physical ID to the CPU module through the communication bus. After the CPU module receives the registration request, the CPU verifies the ID legality and determines it to be a new IO module.

[0017] Preferably, in step S4, the dynamic address of the offline IO module is released and the database is updated, including:

[0018] The CPU module queries the mapping database according to the physical ID number of the offline IO module, finds the corresponding logical address and related records;

[0019] The address state of the record is updated to a recyclable state, and after a preset delay period, if the IO module has not recovered online, the CPU module deletes the entry from the mapping database, releases the corresponding logical address resource, so as to be subsequently reassigned to a newly accessed IO module.

[0020] Preferably, in step S4, when the new IO module is online, the CPU module allocates an unoccupied logical address according to its physical ID number, and updates the central database, the mapping database and the communication binding, including:

[0021] First, an unoccupied random number is reused from the released address pool, that is, if the address pool is not empty, an unoccupied logical address is selected from the released address pool, the state of the logical address is updated from the recyclable state to the allocated state, the physical ID of the new IO module is associated with the logical address, the current time is recorded as the last communication timestamp, and the non-response number counter is initialized to 0;

[0022] If the address pool is empty, a new 32-bit random number is generated as a candidate logical address by calling a hardware true random number generator, and uniqueness verification is performed;

[0023] The CPU module assigns the logical address to the corresponding IO module through the communication bus, and after the IO module receives the logical address, the communication binding between the IO module and the CPU module based on the logical address is completed, and subsequent data interaction between the two parties can be performed through the logical address.

[0024] Preferably, the exception handling mechanism comprises:

[0025] Detecting the state of the random number generator, if the random number generator fails or the output does not meet the random characteristics, then performing random number generator processing;

[0026] During the generation of the random number, if an address conflict is detected, then performing address conflict processing;

[0027] After the address allocation, if the communication times out or the data verification device fails when the CPU module sends the logical address to the IO module, then performing communication failure processing;

[0028] The communication failure processing includes recording a communication failure event into a system log, the communication failure event information includes information such as the physical ID of the target IO module, the allocated logical address, a timestamp, and a failure cause, marking the logical address as a temporary conflict state, suspending the use of the address, and re-allocating a new logical address for the IO module, and if multiple communication failures occur, determining that the IO module is abnormal, triggering a disconnection processing procedure, and releasing the address resource.

[0029] Preferably, the random number generator processing includes:

[0030] The CPU module monitors the working state of the hardware true random number generator in real time when the hardware true random number generator is called, and if a hardware failure, an unrecoverable error, or a generated random number that does not meet the true random characteristic is detected, it is determined that the random number generator is invalid.

[0031] The CPU module triggers the abnormality processing mechanism, extracts the physical ID of the IO module to be allocated, performs a hash operation on the physical ID using a preset hash function to generate a fixed-length hash value as a candidate logical address, verifies the uniqueness of the hash value by traversing the database or a Bloom filter, if there is an address conflict, performs the address conflict processing, and if the logical address is unique, the CPU module binds it with the physical ID of the IO module and updates the information in the mapping database, including the address state and the last communication timestamp.

[0032] Preferably, the address conflict processing includes:

[0033] In the process of generating a random number, if it is found that the newly generated random number already exists in the database, there is an address conflict, and if an address conflict is detected, a conflict event is recorded into a system log, and information including the conflict address, the physical ID of the IO module involved, and a timestamp is recorded.

[0034] The CPU module will re-call the true random number generator to generate a new random number as the logical address, and traverse the mapping database again to verify the uniqueness of the newly generated random number. This re-generation and verification process will be repeated until the generated random number meets the uniqueness requirement or reaches a preset maximum number of retries. If the maximum number of retries is reached and a unique random number is still not found, an address allocation failure event is recorded into a system log, and abnormality processing measures such as issuing an alarm and suspending address allocation are taken.

[0035] Based on the same concept, the present application also provides a computer device comprising a memory and a processor, the memory storing computer readable instructions, and the computer readable instructions being executed by the processor to make the processor execute the steps of the PLC system control method based on dynamic address allocation as described in any of the embodiments.

[0036] The application also provides a storage medium storing computer readable instructions, which, when executed by one or more processors, causes the one or more processors to perform the steps of the PLC system control method based on dynamic address allocation according to any one of the embodiments.

[0037] Compared with the prior art, the application has the following beneficial effects:

[0038] The CPU module of the application obtains the unique physical ID of the ARM chip of the IO module through the communication bus, realizes the uniqueness of the physical address of the IO module, generates a unique logical address for each physical ID through a true random number generator, and establishes a mapping database of the physical ID and the logical address, thereby improving the security of the IO module.

[0039] The application performs handshaking through the communication bus, taking the physical ID of the IO module as the communication identifier, and allocates the corresponding logical address as the dynamic address to the corresponding IO module, thereby improving the flexibility of the address allocation of the IO module.

[0040] The application monitors the online state of the IO module through a heartbeat detection mechanism, releases the dynamic logical address of the offline IO module and updates the mapping database if the IO module is offline, and allocates an unoccupied logical address to the new IO module according to its physical ID number and updates the central database, the mapping database and the communication binding when the new IO module is online, thereby realizing the re-allocation of the dynamic address by the CPU module after the IO module is online, releasing the module ID and the dynamic address by the CPU module after the IO module is offline, saving the limited address resources, and effectively solving the flexibility problem of the PLC address allocation. BRIEF DESCRIPTION OF DRAWINGS

[0041] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of the preferred embodiments and are not intended to limit the scope of the application.

[0042] Figure 1 Flowchart of the PLC system control method based on dynamic address allocation of the application;

[0043] Figure 2 Flowchart of the address allocation of the IO module of the PLC system of the application;

[0044] Figure 3 Block diagram of the dynamic address allocation of the PLC system of the application;

[0045] Figure 4 Flowchart of the dynamic address release of the offline IO module of the application;

[0046] Figure 5 Flow chart for dynamic address allocation of IO module online. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application and do not limit the present application. Obviously, the described examples are part of the examples of the present application, but not all the examples. Based on the examples in the present application, all other examples obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0048] Those skilled in the art can understand that, unless specifically stated, the singular form "a", "an", "the" used herein can also include the plural form. It should be further understood that the use of the word "comprise" in the specification of the present application means that the features, integers, steps, operations, elements and / or components exist, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0049] First embodiment

[0050] Referring to Figure 1 , Figure 2 and Figure 3 , the PLC system control method based on dynamic address allocation provided by the present embodiment comprises the following steps:

[0051] S1: After the PLC system is powered on, the CPU module obtains the unique physical ID of the ARM chip of the IO module through the communication bus, and stores the physical ID in the central database. Specifically, in the present embodiment, the unique physical ID of the IO module 1 is the chip exclusive identification ID1, the unique physical ID of the IO module 2 is the chip exclusive identification ID2, the unique physical ID of the IO module 3 is the chip exclusive identification ID3, and the unique physical ID of the IO module 4 is the chip exclusive identification ID4.

[0052] Further, when the PLC system is powered on, the CPU module first completes its own initialization and activates the backplane communication bus. At this time, the CPU module starts to scan all IO modules on the bus and establishes a communication connection with each IO module.

[0053] The CPU module sends a physical ID query instruction to each IO module through the bus. After receiving the instruction, the ARM chip of each IO module reads its own built-in unique physical ID (usually the serial number or exclusive hardware identification fixed at the time of factory shipment of the ARM chip), and feeds back the physical ID to the CPU module through the bus.

[0054] The CPU module collates the unique identification information and stores the collated information in a central database of the system after receiving the physical IDs of all the IO modules.

[0055] S2: The CPU module calls an ARM true random number generator to generate a unique logical address for each physical ID. For example, for any device (physical ID 0x123456789), the TRNG generates a 32-bit random number (assuming 0x4861598754679431) as the logical address thereof, establishes a mapping database of the physical ID and the logical address, and records information (i.e., relevant record information) including the address state, the last communication timestamp, and the unresponsive count. Specifically, in this embodiment, the ARM true random number generator is a hardware random number generator provided with the ARM, a 32-bit random number is obtained according to random noise, and the mapping database is a storage unit established in the CPU, which is used to store the correspondence between the random number (i.e., the logical address) and the physical ID number. The ARM true random number generates ID1 according to TRNG1, ID2 according to TRNG2, ID3 according to TRNG3, and ID4 according to TRNG4.

[0056] Preferably, in step S2, the CPU module calls the ARM true random number generator to generate a unique logical address for each physical ID, and further includes:

[0057] The CPU module calls the ARM true random number generator to generate a random number for each physical ID. For example, after starting the ARM true random number generator TRNG, a 32-bit random number can be obtained by accessing the data register TRNG_DATA. Specifically, in this embodiment, based on the ARM true random number generator, the address allocated to each IO module by the CPU has true randomness.

[0058] The CPU module checks whether the newly generated random number has been allocated by traversing the mapping database. If not, the allocation is performed. If yes, the processing is performed through an exception handling mechanism.

[0059] When the generated random number meets the uniqueness requirement, the physical ID and the corresponding logical address are associated, the mapping database is updated, and the address state is recorded as allocated and the current last communication timestamp.

[0060] S3: The CPU module performs handshaking with the physical ID of the IO module as the communication identifier through the communication bus, allocates the corresponding logical address as a dynamic address to the corresponding IO module, and completes the address binding and the communication handshaking.

[0061] Further, first, the CPU module traverses all IO module physical IDs stored in the central database, and for each physical ID, the following operations are performed: selecting an unoccupied logical address from the dynamic address pool, and then sending an address allocation instruction to the IO module corresponding to the physical ID through the communication bus, the instruction containing the logical address to be allocated and communication parameters;

[0062] After the IO module receives the instruction, it responds to the verification with its own physical ID as the identifier, and after confirming that the target object of the instruction is consistent with itself, it writes the allocated logical address into the internal register and returns a handshake success signal to the CPU through the bus. After receiving the confirmation signal, the CPU immediately establishes the binding relationship between the physical ID and the logical address in the mapping database, thereby completing the address allocation and the establishment of the communication link. In the entire process, the physical ID ensures that the instruction is accurately delivered to the target module, and the dynamic address allocation enables flexible configuration regardless of hardware, so that the system can automatically complete the re-allocation and binding of the address through the above process when the module is hot-plugged or replaced, thereby ensuring the continuous and stable operation of industrial control.

[0063] S4: During system operation, the CPU module monitors the online state of the IO module through a heartbeat detection mechanism. If the IO module is offline, the dynamic logical address of the offline IO module is released and the mapping database is updated. If a new IO module is online, the CPU module allocates an unoccupied logical address to the new IO module according to its physical ID number, and updates the central database, the mapping database, and the communication binding.

[0064] Preferably, in step S4, the CPU module monitors the online state of the IO module through a heartbeat detection mechanism, including:

[0065] The CPU module periodically sends a heartbeat request to the IO module. If a certain IO module returns a response within a specified time, the CPU module resets the non-response count counter of the IO module to 0 and updates the last communication timestamp of the module in the database. If a certain IO module does not return a response within a specified time, the CPU module increments the non-response count counter of the module by 1.

[0066] The CPU module checks the value of the continuous non-response count counter of the IO module. If the non-response count counter value exceeds a preset threshold, it is determined that the IO module is offline. When a new IO module is connected to the system, the IO module sends a registration request for its physical ID to the CPU module through the communication bus. After receiving the registration request, the CPU module verifies the ID legality and determines that it is a new IO module.

[0067] Please refer to Figure 4 In step S4, the dynamic address of the offline IO module is released and the database is updated, including:

[0068] The CPU module queries the mapping database according to the physical ID number of the offline IO module, finds the corresponding logical address and related records, and specifically, in this embodiment, the related records are physical id, logical address, address state, last communication timestamp and non-response times counter (records the number of consecutive heartbeat timeout times);

[0069] The address state of the record is updated to a recyclable state, and after a preset delay period, if the IO module has not recovered online, the CPU module deletes the entry from the mapping database and releases the corresponding logical address resource, so as to be subsequently allocated to a newly accessed IO module.

[0070] Referring to Figure 5 As shown in FIG. 4, in step S4, when the new IO module is online, the CPU module allocates an unoccupied logical address according to the physical ID number thereof, and updates the central database, the mapping database and the communication binding, including:

[0071] First, an unoccupied random number is reused from the released address pool, that is, if the address pool is not empty, an unoccupied logical address is selected from the released address pool, the state of the logical address is updated from the recyclable state to the allocated state, the physical ID of the new IO module is associated with the logical address, the current time is recorded as the last communication timestamp, and the non-response times counter is initialized to 0. Specifically, in this embodiment, the way of selecting an unoccupied logical address can be in the order of release, or a random selection strategy can be used.

[0072] If the address pool is empty, a new 32-bit random number is generated as a candidate logical address by calling a hardware ARM true random number generator, and uniqueness verification is performed. Specifically, in this embodiment, the uniqueness verification is performed by traversing the mapping database or using a Bloom filter to verify whether the newly generated random number has been allocated to other IO modules.

[0073] The CPU module distributes the allocated logical address to the corresponding IO module through the communication bus, and after the IO module receives the logical address, the communication binding between the IO module and the CPU module based on the logical address is completed, and subsequent data interaction between the two parties can be performed through the logical address.

[0074] Preferably, the abnormality processing mechanism includes:

[0075] Detecting the state of the random number generator, and if the random number generator fails or the output does not meet the random characteristics, performing random number generator processing;

[0076] If an address conflict is detected during the generation of the random number, address conflict processing is performed;

[0077] After the address allocation, if the CPU module sends a logical address to the IO module and the communication times out or the data is not verified, the communication failure processing is performed;

[0078] The communication failure processing includes recording a communication failure event in a system log, the communication failure event information including the physical ID of the target IO module, the allocated logical address, a timestamp, and failure cause, marking the logical address as a temporary conflict state, suspending the use of the address, and re-allocating a new logical address for the IO module. If the communication fails multiple times, it is determined that the IO module is abnormal, and a disconnection processing flow is triggered to release the address resource.

[0079] Preferably, the random number generator processing includes:

[0080] When the CPU module calls the hardware ARM true random number generator, it monitors the working state in real time. If a hardware failure, an unrecoverable error, or a generated random number that does not meet the true random characteristics is detected, it is determined that the random number generator is invalid.

[0081] The CPU module triggers an exception processing mechanism, extracts the physical ID of the IO module to be allocated, uses a preset hash function to perform a hash operation on the physical ID, generates a fixed-length hash value as a candidate logical address, verifies the uniqueness of the hash value by traversing the database or a Bloom filter, if there is an address conflict, address conflict processing is performed, if the logical address is unique, the CPU module binds it with the physical ID of the IO module, and updates the information in the mapping database, including the address state, the last communication timestamp.

[0082] Preferably, the address conflict processing includes:

[0083] In the process of generating a random number, if it is found that the newly generated random number already exists in the database, there is an address conflict. If an address conflict is detected, a conflict event is recorded in the system log, and information including the conflict address, the physical ID of the IO module involved, and the timestamp is recorded.

[0084] The CPU module will re-call the ARM true random number generator to generate a new random number as a logical address, and traverse the mapping database again to verify the uniqueness of the newly generated random number. This re-generation and verification process will be repeated until the generated random number meets the uniqueness requirement or reaches the preset maximum number of retries. If the maximum number of retries is reached and a unique random number is still not found, an address allocation failure event is recorded in the system log, and abnormal processing measures including issuing an alarm and suspending address allocation are taken.

[0085] Second embodiment

[0086] In some embodiments of the present application, a computer device is also provided, comprising a memory and a processor, wherein the memory stores computer readable instructions, and the computer readable instructions are executed by the processor to make the processor execute the steps of the PLC system control method based on dynamic address allocation in the first embodiment of the present application.

[0087] The present application also provides a storage medium storing computer readable instructions, and the computer readable instructions are executed by one or more processors to make the one or more processors execute the steps of the PLC system control method based on dynamic address allocation in the first embodiment of the present application.

[0088] It can be understood that, for the aforementioned PLC system control method based on dynamic address allocation, if each is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to make a computer device (which can be a personal computer server, or a network device, etc.) execute all or part of the steps of the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0089] The computer readable storage medium can include a data signal carried in the baseband or as part of a carrier wave, wherein the readable program code is carried. Such a propagated data signal can take various forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The readable storage medium can also be any readable medium other than the readable storage medium, which can send, propagate or transmit programs for use by or in conjunction with an instruction execution system, device or apparatus. The program code contained on the readable storage medium can be transmitted by any suitable medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the above.

[0090] The above is only the preferred embodiments of the present application, and the protection scope of the present application is not limited to the above-mentioned embodiments. Any technical solutions falling within the concept of the present application shall be considered as falling within the protection scope of the present application. It should be noted that, for ordinary skilled persons in the art, some improvements and refinements without departing from the principles of the present application shall also be considered as falling within the protection scope of the present application.

Claims

1. A PLC system control method based on dynamic address assignment, characterized by, The method comprises the following steps: S1: after the PLC system is powered on, the CPU module obtains the unique physical ID of the ARM chip of the IO module through the communication bus, and stores the physical ID in the central database; S2: the CPU module calls a true random number generator to generate a unique logical address for each physical ID, establishes a mapping database of the physical ID and the logical address, and records information such as address state, last communication timestamp and non-response number counter; S3: the CPU module performs handshake through the communication bus with the physical ID of the IO module as the communication identifier, allocates the corresponding logical address to the corresponding IO module as a dynamic address, and completes address binding and communication handshake; S4: during system operation, the CPU module monitors the online state of the IO module through a heartbeat detection mechanism, if the IO module is offline, the dynamic logical address of the offline IO module is released and the mapping database is updated, and if a new IO module is online, the CPU module allocates an unused logical address according to the physical ID number of the new IO module, and updates the central database, the mapping database and the communication binding.

2. The PLC system control method based on dynamic address allocation according to claim 1, characterized in that, In step S2, the CPU module calls a true random number generator to generate a unique logical address for each physical ID, further comprising: The CPU module calls a true random number generator to generate a random number for each physical ID; The CPU module checks whether the newly generated random number has been allocated by traversing the mapping database, if not, the allocation is performed, if yes, the processing is performed through an exception handling mechanism; When the generated random number meets the uniqueness requirement, the physical ID and the corresponding logical address are associated, the mapping database is updated, and the address state is recorded as allocated and the current last communication timestamp.

3. The dynamic address allocation based PLC system control method according to claim 2, wherein In step S4, the CPU module monitors the online state of the IO module through a heartbeat detection mechanism, comprising: The CPU module periodically sends a heartbeat request to the IO module, if a certain IO module returns a response within a specified time, the CPU module resets the non-response number counter of the IO module to 0 and updates the last communication timestamp of the module in the database, if a certain IO module does not return a response within a specified time, the CPU module increments the non-response number counter of the module by 1; The CPU module checks the value of the continuous non-response number counter of the IO module, if the value of the non-response number counter exceeds a preset threshold, it is determined that the IO module is offline, when a new IO module accesses the system, the IO module sends a registration request of the physical ID to the CPU module through the communication bus, and the CPU module receives the registration request, then the CPU verifies the ID legality and determines that it is a new IO module.

4. The PLC system control method based on dynamic address allocation according to claim 3, characterized by, In step S4, the dynamic address of the offline IO module is released and the database is updated, comprising: The CPU module queries the mapping database according to the physical ID number of the offline IO module, finds the corresponding logical address and related records; The recorded address state flag is updated to a recyclable state, and after a preset delay period, if the IO module still does not recover online, the CPU module deletes the entry from the mapping database, releases the corresponding logical address resource, and reassigns the logical address to a newly accessed IO module.

5. The dynamic address allocation based PLC system control method according to claim 4, wherein, In step S4, when the new IO module is online, the CPU module assigns an unoccupied logical address to the new IO module according to the physical ID number of the new IO module, and updates the central database, the mapping database, and the communication binding, including: First, an unoccupied random number is reused from the released address pool, that is, if the address pool is not empty, an unoccupied logical address is selected from the released address pool, the state of the logical address is updated from the recyclable state to the assigned state, the physical ID of the new IO module is associated with the logical address, the current time is recorded as the last communication timestamp, and the non-response count counter is initialized to 0; If the address pool is empty, a new 32-bit random number is generated as a candidate logical address by calling a hardware true random number generator, and uniqueness verification is performed; The CPU module assigns the logical address to the corresponding IO module through the communication bus, and after the IO module receives the logical address, the communication binding between the IO module and the CPU module based on the logical address is completed, and subsequent data interaction between the two parties can be performed through the logical address.

6. The dynamic address allocation based PLC system control method according to claim 5, wherein, The exception handling mechanism includes: Detecting the state of the random number generator, and if the random number generator fails or the output does not meet the random characteristics, performing random number generator processing; In the process of generating a random number, if an address conflict is detected, address conflict processing is performed; After address allocation, if communication times out or data verification fails when the CPU module sends a logical address to the IO module, communication failure processing is performed; The communication failure processing includes recording the communication failure event in the system log, the communication failure event information includes the physical ID of the target IO module, the assigned logical address, the timestamp, and the failure reason, the logical address is marked as a temporary conflict state, the address is temporarily suspended, a new logical address is allocated to the IO module, and if the communication fails multiple times, the IO module is determined to be abnormal, triggering the offline processing procedure to release the address resource.

7. The dynamic address allocation based PLC system control method according to claim 6, wherein, The random number generator processing includes: The CPU module monitors the working state of the hardware true random number generator in real time when calling the hardware true random number generator, and if a hardware failure, an unrecoverable error, or a generated random number that does not meet the true random characteristics is detected, the random number generator is determined to be invalid; The CPU module triggers the exception handling mechanism, extracts the physical ID of the IO module to be assigned, performs a hash operation on the physical ID using a preset hash function to generate a fixed-length hash value as a candidate logical address, verifies the uniqueness of the hash value by traversing the database or using a Bloom filter, and if there is an address conflict, the address conflict processing is performed, and if the logical address is unique, the CPU module binds the logical address to the physical ID of the IO module and updates the address state and the last communication timestamp in the mapping database.

8. The dynamic address allocation based PLC system control method according to claim 7, wherein, The address conflict processing includes: In the process of generating random numbers, if it is found that the newly generated random number already exists in the database, there is an address conflict, the address conflict is detected, and the conflict event is recorded to the system log, including the information of the conflict address, the physical ID of the involved IO module, and the timestamp; The CPU module will re-call the true random number generator to generate a new random number as the logical address, and traverse the mapping database again to check the uniqueness of the newly generated random number. This re-generation and checking process will be repeated until the generated random number meets the uniqueness requirement or reaches the preset maximum retry number. If the maximum retry number is reached and a unique random number is still not found, an address allocation failure event is recorded to the system log, and abnormal handling measures such as issuing an alarm and suspending address allocation are taken.

9. A computer device, comprising: The computer readable instructions, when executed by one or more processors, cause the one or more processors to perform the steps of the PLC system control method based on dynamic address allocation as claimed in any one of claims 1 to 8.

10. A storage medium storing computer readable instructions, wherein, The computer readable instructions, when executed by one or more processors, cause the one or more processors to perform the steps of the PLC system control method based on dynamic address allocation as claimed in any one of claims 1 to 8.

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