Power supply circuit with linearly reduced output voltage

Abstract

The invention discloses a power supply circuit with linearly reduced output voltage. The circuit comprises a trigger and pulse generation circuit, an integration and level shifting circuit and a power driving circuit, the trigger and pulse generation circuit is connected with the integration and level shifting circuit, and the integration and level shifting circuit is connected with the power driving circuit. The circuit controls the re-triggering monostable trigger D1A to output a positive pulse by pressing the switch S1, the re-triggering monostable trigger D1A inputs a pulse signal to the integration and level shifting circuit for signal processing, and the processed electric signal is input to the power driving circuit to complete linearly reduced voltage output. The method is composed of simple hardware, does not need software, and is easy to popularize and apply.

Description

Technical Field

[0001] The present invention relates to the technical field of power supplies, and particularly to a power supply circuit with a linearly decreasing output voltage. Background Art

[0002] In engineering applications, sometimes it is required that the output voltage of a power supply linearly decreases from a certain value. Currently, the output voltage of power supplies is almost stable. To change the output voltage, generally, it is achieved by a manual knob or by voltage setting digital keys. However, this method cannot make the output voltage linearly change and cannot meet the requirements of engineering applications. Although some power supplies with linearly changing voltage can achieve a linearly decreasing output voltage, because they include a single-chip microcomputer and require software development and program compilation, this limits their applications. The present invention is entirely composed of simple hardware, does not require program compilation, and is easy to promote and use. Summary of the Invention

[0003] A power supply circuit with a linearly decreasing output voltage proposed by the present invention can solve at least one of the technical problems in the background art.

[0004] To achieve the above object, the present invention adopts the following technical solutions:

[0005] A power supply circuit with a linearly decreasing output voltage includes: a trigger and pulse generation circuit, an integration and level shift circuit, and a power drive circuit;

[0006] The trigger and pulse generation circuit is connected to the integration and level shift circuit, and the integration and level shift circuit is connected to the power drive circuit;

[0007] Among them, the trigger and pulse generation circuit includes a switch S1, a retriggerable monostable flip-flop D1A, resistors R1, R2, R3, R4, capacitors C1, C2;

[0008] One end of the switch S1 is connected to a +5V voltage source, and the other end is connected to the common end of the resistor R1 and the resistor R4; the other end of the resistor R1 is connected to port two of the retriggerable monostable flip-flop D1A, and the other end of the resistor R4 is grounded;

[0009] One end of the resistor R2 is connected to +5V, and the other end is connected to port three of D1A; port one and port fourteen of the retriggerable monostable flip-flop D1A are grounded;

[0010] The capacitor C1 is connected between port fourteen and port fifteen of the retriggerable monostable flip-flop D1A;

[0011] One end of the resistor R3 is connected to +5V, and the other end is connected to port fifteen of the retriggerable monostable flip-flop D1A;

[0012] The sixteenth port of the retriggerable monostable flip-flop D1A is connected to the +5V voltage source; the eighth port of the retriggerable monostable flip-flop D1A is grounded; the capacitor C2 is connected between the sixteenth port and the eighth port of D1A, and the fourth port of D1A is connected to one end of the resistor R8 of the integration and level shift circuit.

[0013] Further, the integration and level shift circuit of the present invention includes an operational amplifier N1B, resistors R5, R6, R7, R8, R9, R10, a capacitor C5, and a switch S2;

[0014] One end of the resistor R5 is connected to the +5V voltage source, and the other end is connected to the common end of the resistors R6 and R7; the other end of the resistor R6 is grounded, and the other end of the resistor R7 is connected to the non-inverting input terminal of the operational amplifier N1B;

[0015] One end of the resistor R8 is connected to the inverting input terminal of the operational amplifier N1B, and the other end is connected to the thirteenth port of D1A of the trigger and pulse generation circuit;

[0016] One end of the resistor R9 is connected to the inverting input terminal of the operational amplifier N1B, and the other end is connected to the output terminal of the operational amplifier N1B;

[0017] One end of the resistor R10 is connected to the output terminal of the operational amplifier N1B, and the other end is connected to one end of the switch S2; the capacitor C5 is connected in parallel across the resistor R9; one end of the switch S2 is connected to the inverting input terminal of the operational amplifier N1B, and the other end is connected to one end of the resistor R10; the output terminal of the operational amplifier N1B is connected to one end of the resistor R11 of the power drive circuit.

[0018] Further, the power drive circuit of the present invention includes an operational amplifier N1A, resistors R11, R12, R13, R14, capacitors C4, C3, and a Darlington transistor V1;

[0019] The resistor R11 is connected to the non-inverting input terminal of the operational amplifier N1A; one end of the resistor R12 is connected to the output terminal of N1A, and the other end is connected to the base of the Darlington transistor V1; one end of the resistor R13 is connected to the inverting input terminal of N1A, and the other end is grounded; one end of the resistor R14 is connected to the inverting input terminal of the operational amplifier N1A, and the other end is connected to the emitter of V1; the collector of V1 is connected to +15V. One end of the capacitor C3 is connected to the positive power supply terminal of the operational amplifier N1A, and the other end is grounded; one end of the capacitor C4 is connected to the negative power supply terminal of the operational amplifier N1A, and the other end is grounded.

[0020] As can be seen from the above technical solutions, the present invention is composed of simple hardware, does not require software, and is easy to promote and apply; compared with the output voltage of the switching power supply which is stable and unchanged, the output voltage of the present invention can linearly decrease. Description of the Drawings

[0021] Figure 1Schematic diagram of the power supply circuit with linearly decreasing output voltage of the present invention;

[0022] Figure 2 Output waveform of the trigger and pulse formation circuit of the present invention;

[0023] Figure 3 Output waveform of the integration and level shift circuit of the present invention;

[0024] Figure 4 Output waveform of the power drive circuit of the present invention. Detailed implementation manners

[0025] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention.

[0026] As Figure 1 shown, the power supply circuit with linearly decreasing output voltage described in this embodiment includes a trigger and pulse generation circuit, an integration and level shift circuit, and a power drive circuit;

[0027] The trigger and pulse generation circuit is connected to the integration and level shift circuit, and the integration and level shift circuit is connected to the power drive circuit.

[0028] The trigger and pulse generation circuit includes a switch S1, a retriggerable monostable flip-flop D1A, resistors R1, R2, R3, R4, capacitors C1, C2;

[0029] One end of the switch S1 is connected to the +5V voltage source, and the other end is connected to the common end of the resistor R1 and the resistor R4; the other end of the resistor R1 is connected to port two of the retriggerable monostable flip-flop D1A, and the other end of the resistor R4 is grounded;

[0030] One end of the resistor R2 is connected to +5V, and the other end is connected to port three of D1A; port one and port fourteen of the retriggerable monostable flip-flop D1A are grounded;

[0031] The capacitor C1 is connected between port fourteen and port fifteen of the retriggerable monostable flip-flop D1A;

[0032] One end of the resistor R3 is connected to +5V, and the other end is connected to port fifteen of the retriggerable monostable flip-flop D1A;

[0033] Port sixteen of the retriggerable monostable flip-flop D1A is connected to the +5V voltage source; port eight of the retriggerable monostable flip-flop D1A is grounded; the capacitor C2 is connected between port sixteen and port eight of D1A, and port four of D1A is connected to one end of the resistor R8 of the integration and level shift circuit.

[0034] The integration and level shift circuit includes operational amplifier N1B, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, capacitor C5, and switch S2;

[0035] One end of resistor R5 is connected to the +5V voltage source, and the other end is connected to the common end of resistor R6 and resistor R7; the other end of resistor R6 is grounded, and the other end of resistor R7 is connected to the non-inverting input terminal of operational amplifier N1B;

[0036] One end of resistor R8 is connected to the inverting input terminal of operational amplifier N1B, and the other end is connected to port thirteen of D1A in the triggering and pulse generation circuit;

[0037] One end of resistor R9 is connected to the inverting input terminal of operational amplifier N1B, and the other end is connected to the output terminal of operational amplifier N1B;

[0038] One end of resistor R10 is connected to the output terminal of operational amplifier N1B, and the other end is connected to one end of switch S2; capacitor C5 is connected in parallel across resistor R9; one end of switch S2 is connected to the inverting input terminal of operational amplifier N1B, and the other end is connected to one end of resistor R10; the output terminal of operational amplifier N1B is connected to one end of resistor R11 in the power drive circuit.

[0039] The power drive circuit includes operational amplifier N1A, resistor R11, resistor R12, resistor R13, resistor R14, capacitor C4, capacitor C3, and Darlington transistor V1;

[0040] Resistor R11 is connected to the non-inverting input terminal of operational amplifier N1A; one end of resistor R12 is connected to the output terminal of N1A, and the other end is connected to the base of Darlington transistor V1; one end of resistor R13 is connected to the inverting input terminal of N1A, and the other end is grounded; one end of resistor R14 is connected to the inverting input terminal of operational amplifier N1A, and the other end is connected to the emitter of V1; the collector of V1 is connected to +15V. One end of capacitor C3 is connected to the positive power supply terminal of operational amplifier N1A, and the other end is grounded; one end of capacitor C4 is connected to the negative power supply terminal of operational amplifier N1A, and the other end is grounded.

[0041] The method for regulating the power supply voltage with the output voltage linearly decreasing is as follows:

[0042] Press switch S1, so that the level of port two of the retriggerable monostable flip-flop D1A changes from low to high, then port thirteen Q of the retriggerable monostable flip-flop D1A will output a positive pulse, and the waveform is as Figure 2 shown. The low level of this pulse is 0V, the high level is about 5V, and the width of the pulse is approximately equal to 0.33×R3×C1. It is calculated that the width of the pulse output by the circuit is about 1.8 seconds.

[0043] In the trigger and pulse generation circuit, C1 and R3 determine the width of the output pulse; R1 and R2 are current-limiting resistors; R4 is a grounding resistor; C2 is a power supply filtering capacitor.

[0044] The pulse signal output from port 13 of the retriggerable monostable flip-flop D1A is input to the integration and level shift circuit. After integration and level shift, it becomes a waveform that linearly decreases from approximately 13.2V to approximately 0V within 0 to 1.8 seconds. The waveform is as Figure 3 shown.

[0045] In the integration circuit, R8 and C5 determine the slope of the integration waveform; R9 adjusts the linearity of the waveform; R7 is a bias resistor; S2 and R10 are used to discharge the integration capacitor C5.

[0046] R5, R6 and the +5V power supply provide voltage for level shift, moving the integration waveform upward.

[0047] The output signal of the integration circuit is input to the power drive circuit. At the output terminal VOUT of the power drive circuit, a voltage that linearly decreases from 13.2V to 0V within 0 to 1.8 seconds can be obtained. The waveform is as Figure 4 shown, and the power drive circuit output terminal can output several amperes of current. The power drive circuit consists of an operational amplifier N1A and a Darlington transistor V1 to form a non-inverting amplifier circuit, and V1 operates in the emitter follower form. The output voltage at the VOUT terminal is approximately equal to (1 + R14 / R13)V R11 , V R11 is the input voltage at the left end of R11, that is, the output voltage of the integration and level shift circuit.

[0048] In the power drive circuit, R11 and R12 are current-limiting resistors; R13 and R14 determine the voltage gain of the power drive; the function of V1 is power drive.

[0049] Each time it is triggered, the VOUT terminal outputs a voltage that linearly decreases starting from 13.3V. The switch S2 and R14 are used to discharge and reset the capacitor C5. After discharging, it can be triggered again through S1.

[0050] By changing the resistance value of R3 or the capacitance value of C1, the duration of the linearly changing voltage can be changed; by changing the resistance values of R5 and R6, the amplitude of the level shift can be changed; by changing the resistance values of R8 and C5, the speed of the linear change of the output voltage can be adjusted.

[0051] In summary, the present invention is composed of simple hardware, does not require software, and is easy to promote and apply; compared with the output voltage of the switching power supply being stable and unchanged, the output voltage of the present invention can linearly decrease.

[0052] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising said element.

[0053] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and reference can be made to the relevant parts of the method embodiments for the relevant content.

[0054] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power supply circuit with a linearly decreasing output voltage, characterized in that, It includes: A trigger and pulse generation circuit, an integration and level shift circuit, and a power drive circuit; The trigger and pulse generation circuit is connected to the integration and level shift circuit, and the integration and level shift circuit is connected to the power drive circuit; Among them, the trigger and pulse generation circuit includes a switch S1, a retriggerable monostable flip-flop D1A, resistors R1, R2, R3, R4, capacitors C1, C2; One end of the switch S1 is connected to the +5V voltage source, and the other end is connected to the common end of the resistor R1 and the resistor R4; the other end of the resistor R1 is connected to port two of the retriggerable monostable flip-flop D1A, and the other end of the resistor R4 is grounded; One end of the resistor R2 is connected to +5V, and the other end is connected to port three of D1A; port one and port fourteen of the retriggerable monostable flip-flop D1A are grounded; The capacitor C1 is connected between port fourteen and port fifteen of the retriggerable monostable flip-flop D1A; One end of the resistor R3 is connected to +5V, and the other end is connected to port fifteen of the retriggerable monostable flip-flop D1A; Port sixteen of the retriggerable monostable flip-flop D1A is connected to the +5V voltage source; port eight of the retriggerable monostable flip-flop D1A is grounded; the capacitor C2 is connected between port sixteen and port eight of D1A; port four of D1A is connected to one end of the resistor R8 of the integration and level shift circuit.

2. The power supply circuit with a linearly decreasing output voltage according to claim 1, characterized in that, The integration and level shift circuit includes an operational amplifier N1B, resistors R5, R6, R7, R8, R9, R10, a capacitor C5, and a switch S2; One end of the resistor R5 is connected to the +5V voltage source, and the other end is connected to the common end of the resistor R6 and the resistor R7; the other end of the resistor R6 is grounded, and the other end of the resistor R7 is connected to the non-inverting input terminal of the operational amplifier N1B; One end of the resistor R8 is connected to the inverting input terminal of the operational amplifier N1B, and the other end is connected to port thirteen of D1A of the trigger and pulse generation circuit; One end of the resistor R9 is connected to the inverting input terminal of the operational amplifier N1B, and the other end is connected to the output terminal of the operational amplifier N1B; One end of the resistor R10 is connected to the output terminal of the operational amplifier N1B, and the other end is connected to one end of the switch S2; the capacitor C5 is connected in parallel across the resistor R9; one end of the switch S2 is connected to the inverting input terminal of the operational amplifier N1B, and the other end is connected to one end of the resistor R10; the output terminal of the operational amplifier N1B is connected to one end of the resistor R11 of the power drive circuit.

3. The power supply circuit with linearly decreasing output voltage according to claim 1, wherein The power drive circuit includes an operational amplifier N1A, resistors R11, R12, R13, R14, capacitors C4, C3, and a Darlington transistor V1; The resistor R11 is connected to the non-inverting input terminal of the operational amplifier N1A; one end of the resistor R12 is connected to the output terminal of N1A, and the other end is connected to the base of the Darlington transistor V1; one end of the resistor R13 is connected to the inverting input terminal of N1A, and the other end is grounded; one end of the resistor R14 is connected to the inverting input terminal of the operational amplifier N1A, and the other end is connected to the emitter of V1; the collector of V1 is connected to +15V; One end of the capacitor C3 is connected to the positive power supply terminal of the operational amplifier N1A, and the other end is grounded; one end of the capacitor C4 is connected to the negative power supply terminal of the operational amplifier N1A, and the other end is grounded.

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