CPU micro-architecture parameter exploration method based on Bayesian optimization

Abstract

The invention provides a Bayesian optimization-based CPU micro-architecture parameter exploration scheme, and aims to realize end-to-end CPU design space exploration and optimization by constructing a multi-confidence CPU micro-architecture parameter exploration device, and the scheme integrates the advantages of simulation tools with different confidence degrees, and has the advantages of being simple in structure, convenient to use and high in efficiency. According to the technical scheme, low-cost accurate calibration of low-confidence simulation is achieved, more accurate feedback information is provided for the multi-confidence Bayesian optimization device, in addition, an appropriate confidence simulation tool is selected according to the real-time distribution characteristics of the data samples, and therefore the optimal balance of the accuracy and efficiency of CPU design parameter exploration is achieved. In general, the scheme effectively coordinates the contradiction of different confidence simulation tools in the aspects of accuracy and time consumption, and remarkably improves the exploration efficiency of the CPU micro-architecture design parameters.

Description

Technical Field

[0001] The present invention relates to a method for exploring design parameters of a general - purpose processor micro - architecture. Specifically, it relates to the field of central processing unit (CPU) design. More specifically, it relates to a method for exploring CPU micro - architecture parameters based on Bayesian optimization. Background Art

[0002] In CPU micro - architecture design, core parameters such as the register file size, cache capacity, and arithmetic unit configuration are key factors affecting the performance and energy efficiency of the CPU. Due to the high cost of tape - out, simulation tools are usually used in the CPU design stage to evaluate the performance and power consumption metrics of specific CPU design parameters, so as to guide the design and fabrication of the CPU.

[0003] In the prior art, low - confidence simulation tools or high - confidence simulation tools are usually used for simulating CPU design parameters. Among them, low - confidence simulation tools achieve efficient performance evaluation through high - level abstraction. Taking the Gem5 architecture simulator as an example, this simulator is a low - confidence simulation tool for simulating processor behavior. It is written in high - level and highly abstract programming languages (such as C / C++, Python) and can run on ordinary computers. Generally speaking, the simulator mostly focuses on simulating the behavior of CPU components and does not go down to the register transfer level. In addition, since the chips of mainstream X86 and ARM instruction sets are not open - source, researchers cannot obtain the hardware description language codes of these chips, and it is impossible to perform register transfer - level and gate - level simulations. Therefore, most CPU micro - architecture design space explorations are carried out at the architecture level using low - confidence simulation tools or prediction models. In addition, low - confidence simulation usually achieves higher simulation efficiency by ignoring more circuit details. High - confidence simulation tools mainly focus on register transfer - level or gate - level or even circuit - level simulations. With the development of open - source chips, researchers can more easily obtain chip design codes to facilitate micro - architecture exploration using high - confidence simulation. However, high - confidence simulation takes a long time and can only be explored and evaluated within a limited design space. In addition, the problem of high - confidence simulation time - consuming becomes more serious as the CPU design scale increases. Therefore, the exploration of micro - architecture design parameters for large - scale processor cores becomes more challenging.

[0004] The existing CPU microarchitecture parameter exploration solutions mainly focus on using and improving a single simulation tool, neglecting to attempt to combine simulation tools with different confidence levels. Using a single simulation tool cannot effectively balance the efficiency and accuracy of simulation. Specifically, although high-confidence simulation has high precision, its computational cost is high and it is difficult to be applied on a large scale. While low-confidence simulation is efficient, its precision is insufficient and it is difficult to meet the requirements of design optimization. In addition, due to the low accuracy of the prediction results of low-confidence simulation tools, how to improve the accuracy of low-confidence simulation data has also become a key problem faced by current technologies. In recent years, although there are some solutions involving combining two or more simulation tools, they often collect data through high-confidence simulation in the early stage, then train a model based on the collected data, and still use low-confidence simulation tools for simulation in the later stage. Although this method utilizes the high-precision simulation results of high-confidence simulation, it still only relies on low-confidence simulation tools in the subsequent optimization process and fails to fully utilize the advantages of the two simulation tools. For solutions that combine multiple simulation tools, how to effectively combine simulation tools with different confidence levels and achieve the best balance between efficiency and accuracy in the optimization process is also a problem that current technologies need to solve.

[0005] In summary, most of the existing CPU design parameter exploration solutions focus on the use and improvement of a single simulation tool, while ignoring the potential of combining simulation tools with different confidence levels. Although some studies have attempted to integrate multiple simulation tools, these studies usually only use high-confidence simulation to collect data for training models in the initial stage, and the subsequent optimization process still relies on the simulation results of low-confidence simulation tools, failing to fully explore the synergistic advantages of the two simulation tools. All in all, the existing CPU design parameter exploration solutions are difficult to achieve a balance between efficiency and accuracy, especially in improving the accuracy of low-confidence simulation data. Therefore, there is an urgent need for a CPU microarchitecture design parameter exploration solution that can integrate the advantages of low-confidence and high-confidence simulation tools and achieve an accurate trade-off between efficiency and accuracy.

[0006] It should be noted that: This background technology is only used to introduce relevant information of the present invention to facilitate understanding of the technical solution of the present invention, but it does not mean that the relevant information is necessarily prior art. Without evidence indicating that the relevant information was publicly available before the filing date of the present invention, the relevant information should not be regarded as prior art. Summary of the Invention

[0007] Therefore, the object of the present invention is to overcome the above-mentioned defects of the prior art and provide a CPU microarchitecture parameter exploration solution based on Bayesian optimization.

[0008] The object of the present invention is achieved by the following technical solutions:

[0009] According to a first aspect of the present invention, a method for exploring CPU microarchitecture parameters based on Bayesian optimization is proposed, which is used to explore multiple CPU design parameters that meet performance requirements from a preset CPU design parameter space. The method includes multiple rounds of iteration, where each round of iteration includes: Step S1, using a pre-constructed Bayesian optimization device to select a CPU design parameter sample with the optimal performance index from the CPU design space according to the performance indexes of all CPU design parameters in the CPU design space; Step S2, using a preset low-confidence simulation tool to simulate the CPU design parameter sample selected in Step S1 to obtain the low-confidence performance index and microarchitecture events of the CPU design parameter sample; Step S3, using a preset error prediction model to predict the simulation error of the CPU design parameter sample selected in Step S1 and output the uncertainty of the predicted simulation error, where the simulation error is the difference between the performance indexes obtained when using a preset high-confidence simulation tool and a preset low-confidence simulation tool to simulate the same CPU design parameter sample; Step S4, obtaining the final performance index of the CPU design parameter sample selected in Step S1 in a preset manner based on the uncertainty of the simulation error obtained in Step S3, and updating the Bayesian optimization device and the preset error prediction model, and retaining the design parameters in the CPU design parameter sample obtained in the current iteration when the final performance index meets the required performance requirements.

[0010] Preferably, the pre-constructed Bayesian optimization device includes a surrogate model and an acquisition function. The surrogate model is a random forest model constructed based on the prior distribution of the objective function and used to fit the posterior distribution of the objective function. The surrogate model is updated based on the CPU design parameter samples and their final performance indexes in each round of iteration. The objective function is a mapping between the CPU design parameter samples and the performance indexes constructed based on prior knowledge. The acquisition function selects a CPU design parameter sample with the optimal performance from the CPU design space based on the posterior distribution of the objective function fitted by the surrogate model updated in each round.

[0011] Preferably, the acquisition function is the Expected Pareto Hypervolume Improvement function.

[0012] Preferably, the preset error prediction model is a prediction model constructed based on a random forest model or a Gaussian process probability model, which is configured to: predict the simulation error of the CPU design parameter sample to be predicted and output the uncertainty of the predicted simulation error based on the CPU design parameter sample to be predicted, the microarchitecture events of the CPU design parameter sample, and the performance index derivative features derived by using a preset method.

[0013] Preferably, the preset method includes: Step T1, selecting multiple CPU design parameter samples from a preset CPU design space in advance, and simulating all the selected CPU design parameter samples using a preset low-confidence simulation tool to obtain the low-confidence performance indices of each CPU design parameter sample; Step T2, calculating the maximum value, minimum value, and average value of all the obtained low-confidence performance indices; Step T3, calculating the differences between the low-confidence performance index of the CPU design parameter sample to be predicted and the maximum value, minimum value, and average value obtained in Step T2, and using the calculated differences as the performance index derivative features of the CPU design parameter sample.

[0014] Preferably, the preset manner is as follows: When the uncertainty meets the constraint condition, correcting the low-confidence performance index obtained in Step S2 based on the simulation error predicted in Step S3, and using the corrected low-confidence performance index as the final performance index of the CPU design parameter sample selected in Step S1, and updating the Bayesian optimization device based on the CPU design parameter sample and its final performance index; When the uncertainty does not meet the constraint condition, simulating the CPU design parameter sample selected in Step S1 using a preset high-confidence simulation tool to obtain the high-confidence performance index of the CPU design parameter sample, and using this as the final performance index of the CPU design parameter sample, and updating the Bayesian optimization device based on the CPU design parameter sample and its final performance index, and using the CPU design parameter sample as the feature data and the difference between the high-confidence performance index of the CPU design parameter sample and the low-confidence performance index obtained in Step S2 as the label to update the error prediction model.

[0015] Preferably, the constraint condition is that the uncertainty output by the error prediction model in the current iteration round is less than the uncertainty threshold configured in the current iteration round.

[0016] Preferably, the uncertainty threshold for each iteration round is configured in any of the following ways: Method 1, configuring the uncertainty threshold in each round of iteration as a fixed value in advance; Method 2, configuring the uncertainty threshold for each round of iteration in the following way:

[0017] ,

[0018] where, represents the uncertainty threshold for the th round of iteration, represents the initial uncertainty threshold, represents the The proportional parameter for round iteration, wherein for each execution of a loop iteration for a preset number of times, the initial uncertainty threshold is reduced by a first preset value, and in a continuous preset number of iteration rounds, if the uncertainty output by the error prediction model shows an upward trend, the proportional parameter is increased by a second preset value, and if the uncertainty output by the error prediction model shows a downward trend, the proportional parameter is increased by a second preset value.

[0019] Preferably, the method includes: for each execution of a loop iteration for a preset number of times, randomly collecting multiple CPU design parameter samples from historical loop iterations as feature data, and using the difference between the final performance index and the low-confidence performance index of each collected CPU design parameter sample as the label of the CPU design parameter sample to train a preset error prediction model.

[0020] Preferably, the performance index includes the power consumption of the CPU and the instructions per clock cycle.

[0021] Compared with the prior art, the advantages of the present invention are as follows:

[0022] By integrating the advantages of different confidence simulation tools, the present invention realizes low-cost and accurate calibration of low-confidence simulations, and further provides more accurate feedback information for the multi-confidence Bayesian optimization device. In addition, according to the real-time distribution characteristics of data samples, this solution intelligently selects appropriate confidence simulations, thereby achieving the optimal balance between accuracy and efficiency in the optimization process. Generally speaking, the present invention effectively coordinates the contradiction between different confidence simulation tools in terms of accuracy and time consumption, and significantly improves the exploration efficiency of CPU microarchitecture design parameters. Description of the Drawings

[0023] The following further describes the embodiments of the present invention with reference to the drawings, wherein:

[0024] Figure 1 It is a schematic diagram of a method for exploring CPU microarchitecture parameters based on Bayesian optimization according to an embodiment of the present invention. Detailed Embodiments

[0025] In order to make the purpose, technical solutions and advantages of the present invention clearer, the following further details the present invention through specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0026] As mentioned in the background section, in summary, most of the existing CPU design parameter exploration schemes focus on the use and improvement of a single simulation tool, while ignoring the potential of combining simulation tools with different confidence levels. In addition, although some schemes attempt to integrate multiple simulation tools, they usually only use high-confidence simulations to collect data for training models at the initial stage, and the subsequent optimization process still relies on the simulation results of low-confidence simulation tools, failing to fully exploit the synergistic advantages of the two simulation tools. The existing CPU design parameter exploration schemes are difficult to achieve a balance between efficiency and accuracy, especially in improving the accuracy of low-confidence simulation data.

[0027] To solve the above problems, the present invention proposes a CPU microarchitecture parameter exploration scheme based on Bayesian optimization. This scheme is used to screen out CPU design parameters that meet the performance requirements from a preset CPU design space during the CPU design stage to guide the CPU microarchitecture design, thereby reducing the cost in the CPU tape-out stage. Specifically, this scheme constructs a multi-confidence CPU microarchitecture parameter exploration device based on a Bayesian optimization device to achieve end-to-end exploration of the CPU design space. This device integrates the advantages of simulation tools with different confidence levels, realizes low-cost and accurate calibration of low-confidence simulations, and thus provides more accurate feedback information for the multi-confidence Bayesian optimization device. In addition, this scheme intelligently selects appropriate confidence-level simulations according to the real-time distribution characteristics of data samples, thereby achieving the best balance between accuracy and efficiency during the optimization process. Generally speaking, this scheme can effectively balance the contradiction between the accuracy and time consumption of simulation tools with different confidence levels and efficiently explore CPU design parameters.

[0028] To better understand the present invention, the present invention will be described in detail below with reference to specific embodiments.

[0029] According to an embodiment of the present invention, a CPU microarchitecture parameter exploration method based on Bayesian optimization is proposed. This method uses a multi-round iterative approach to explore CPU design parameters that meet the performance requirements from a preset CPU design parameter space. Among them, the steps of each round of iteration are as Figure 1As shown in the figure, the steps shown in the figure include: Step S1, using a pre-constructed Bayesian optimization device, selecting a CPU design parameter sample with the optimal performance index from the CPU design space according to the performance indices of all CPU design parameters in the CPU design space; Step S2, using a preset low-confidence simulation tool to simulate the CPU design parameter sample selected in Step S1 to obtain the low-confidence performance index and microarchitecture events of the CPU design parameter sample; Step S3, using a preset error prediction model to predict the simulation error of the CPU design parameter sample selected in Step S1 and output the uncertainty of the predicted simulation error, where the simulation error is the difference between the performance indices obtained when using a preset high-confidence simulation tool and a preset low-confidence simulation tool to simulate the same CPU design parameter sample; Step S4, obtaining the final performance index of the CPU design parameter sample selected in Step S1 in a preset manner based on the uncertainty of the simulation error obtained in Step S3, updating the Bayesian optimization device and the preset error prediction model, and retaining the design parameters in the CPU design parameter sample obtained in the current iteration when the final performance index meets the required performance requirements. It should be noted that the performance indices in the present invention include the power consumption of the CPU and the number of instructions per clock cycle. Among them, when the uncertainty meets the constraint conditions, the low-confidence performance index obtained in Step S2 is corrected based on the predicted simulation error in Step S3 to obtain the final performance index of the CPU design parameter sample selected in Step S1. On the contrary, when the uncertainty does not meet the constraint conditions, a preset high-confidence simulation tool is used to simulate the CPU design parameter sample selected in Step S1 to obtain the high-confidence performance index of the CPU design parameter sample.

[0030] According to an embodiment of the invention, in the present invention, the preset CPU design parameter space is pre-configured by the user according to requirements, which includes various CPU microarchitecture design parameters and multiple optional values for each CPU microarchitecture design parameter. Among them, the types of CPU microarchitecture design parameters include but are not limited to the number of registers in the register file, the size of the cache, and the configured number of arithmetic units. In Step S1 of the present invention, the Bayesian optimization device collects one optional value of each CPU microarchitecture design parameter in the preset CPU design parameter space to construct a CPU design parameter sample. It should be understood that the CPU microarchitecture design parameters in the preset CPU design parameter space are not limited to the three types listed above, and other microarchitecture parameters of CPU design can also be configured in the preset CPU design parameter space.

[0031] It should be understood that the Bayesian optimization device is a device for optimizing an objective function that takes a long time to evaluate, and this device includes a surrogate model and an acquisition function. For complex problems, the objective function to be analyzed is usually unknown. Bayesian optimization treats it as a black-box function, that is, a surrogate model, and assigns a prior distribution to it. After evaluating the objective function, new data is used to form the posterior distribution of the objective function, and the posterior distribution is then used to construct an acquisition function that determines the next point to be evaluated.

[0032] According to an embodiment of the present invention, in the present invention, the surrogate model in the preset Bayesian optimization device is a random forest model constructed based on the prior distribution of the objective function for fitting the posterior distribution of the objective function. The surrogate model is updated based on the CPU design parameter samples and their final performance indices in each round of iteration. The objective function is a mapping function between the CPU design parameter samples constructed based on prior knowledge and their performance indices, where the prior knowledge is the simulation results obtained by pre-simulating with a preset low-confidence simulation tool or a preset high-confidence simulation tool, or the simulation results obtained from other existing datasets; the acquisition function selects a CPU design parameter sample with the optimal performance from the preset CPU design space based on the posterior distribution of the objective function fitted by the surrogate model updated in each round. The present invention uses the expected improvement in Pareto hypervolume (EIPV) as the acquisition function in the Bayesian optimization device. It should be noted that the expected improvement in Pareto hypervolume is a well-known technology to those skilled in the art and will not be elaborated here.

[0033] It should be understood that in the Bayesian optimization device, the acquisition function uses the output of the surrogate model to calculate the scores of each candidate point and selects a candidate point with the highest score as the data sample for the new round of iteration. According to an embodiment of the present invention, in step S1 of the present invention, the acquisition function selects a CPU design parameter sample with the optimal performance index from the preset CPU design space based on the posterior distribution of the objective function fitted by the surrogate model updated in each round, that is, the performance index corresponding to each parameter sample.

[0034] According to an embodiment of the present invention, in step S2 of the present invention, the CPU design parameter samples selected in step S1 are simulated using a low-confidence simulation tool to obtain the low-confidence performance index of the CPU design parameter samples, and the low-confidence performance index is used as a benchmark. It should be understood that since the low-confidence simulation tool focuses on simulating the behavior of the components of the CPU and does not reach the register transfer level, the low-confidence performance index of the CPU design parameter samples can be quickly obtained by utilizing the high simulation efficiency characteristic of the low-confidence simulation tool. However, since the low-confidence simulation tool cannot ensure the fidelity of the simulation results, the obtained low-confidence performance index is only used as a reference benchmark for the performance index of the CPU design parameter samples and cannot be used as the final performance index of the CPU design parameter samples.

[0035] According to an embodiment of the present invention, in step S4 of the present invention, the present invention selects the method for obtaining the final performance parameters of the CPU design parameter samples according to whether the uncertainty of the simulation error predicted by the preset error model meets the constraint conditions. Specifically, when the uncertainty meets the constraint conditions, it indicates that the reliability of the predicted simulation error is high, and the predicted simulation error can be used to correct the low-confidence performance parameters. Therefore, the present invention corrects the low-confidence performance index obtained in step S2 based on the simulation error predicted in step S3, and uses the corrected low-confidence performance index as the final performance index of the CPU design parameter samples selected in step S1, and updates the Bayesian optimization device based on the CPU design parameter samples and their final performance index; when the uncertainty does not meet the constraint conditions, it indicates that the reliability of the predicted simulation error is low, and the predicted error cannot be used to correct the low-confidence performance parameters. Therefore, the present invention uses a preset high-confidence simulation tool to simulate the CPU design parameter samples selected in step S1 to obtain the high-confidence performance index of the CPU design parameter samples, and uses this as the final performance index of the CPU design parameter samples, updates the Bayesian optimization device based on the CPU design parameter samples and their final performance index, and, using the CPU design parameter samples as feature data and the difference between the high-confidence performance index and the low-confidence performance index of the CPU design parameter samples obtained in step S2 as a label, updates the error prediction model. The present invention flexibly selects the error correction method or invokes the high-confidence simulation according to the uncertainty of the simulation error to accurately obtain the final performance index of the CPU design parameters, thereby significantly improving the accuracy of the simulation results while ensuring the simulation efficiency.

[0036] According to an embodiment of the present invention, in the present invention, the preset error prediction model is constructed based on a random forest, a Gaussian process, or other probability models. Therefore, the preset error prediction model not only predicts the simulation error, but also outputs the uncertainty of the predicted simulation error. Among them, the predicted simulation error can be the difference between the high-confidence simulation and the low-confidence simulation, or the numerical ratio of the high-confidence simulation to the low-confidence simulation. It should be understood that the uncertainty output by the error prediction model represents the fidelity of the predicted simulation error. According to the uncertainty, the reliability of the predicted simulation error can be judged, and then it can be judged whether the simulation error can be used to calibrate the low-confidence performance index.

[0037] According to an embodiment of the present invention, in the present invention, the input features of the error prediction model include: (1) CPU design parameter samples, that is, CPU design parameter samples selected by the acquisition function; (2) microarchitectural events generated during low-confidence simulation. Microarchitectural events refer to various operations and state changes at the processor microarchitecture level. These events are usually closely related to the internal components and operations of the processor and are key factors for evaluating and optimizing processor performance. For example, when the CPU executes a certain instruction, it calls a floating-point multiplication operation unit once, and this call is a microarchitectural event; when a certain instruction is fetched, the I Cache misses (the instruction is not cached in the I Cache and needs to be found in the next-level memory), which is also a microarchitectural event. According to the experience of designers, selecting representative microarchitectural events as features reflects the dynamic behavior of the CPU and is closely related to performance and power. (3) Derive a set of derived features based on the global statistics of performance and power. Specifically, the derived features are derived by the following method: Step T1, select multiple CPU design parameter samples from the preset CPU design space in advance, and use the preset low-confidence simulation tool to simulate all the collected CPU design parameter samples to obtain the low-confidence performance index of each CPU design parameter sample; Step T2, calculate the maximum value, minimum value, and average value of all the obtained low-confidence performance indexes; Step T3, calculate the difference between the performance index of the CPU design parameter sample to be predicted and the maximum value, minimum value, and average value obtained in Step T2, and use the calculated difference as the performance index derived feature of the CPU design parameter sample. It should be understood that the derived features are intended to establish the numerical relationship between the performance index of the current CPU design parameter sample and the performance indexes of other CPU parameter design samples, so as to provide a global perspective for the error prediction model. Therefore, when deriving the derived features, other numerical operation methods can also be used to construct the numerical relationship between the performance index of the CPU design parameter sample and the performance indexes of other CPU parameter design samples.

[0038] According to an embodiment of the present invention, in the present invention, the constraint condition is that the uncertainty is less than the uncertainty threshold configured in the current iteration round. Among them, there are two configuration methods for the uncertainty threshold, including: (1) The threshold value for each round is configured to be the same and fixed during the iteration process; (2) The uncertainty threshold in each round of iteration is configured in the following manner: , where represents the uncertainty threshold of the th round of iteration, represents the initial uncertainty threshold. Each time a preset number of loop iterations is executed, preferably, the preset number is 200. It should be understood that the preset number can be configured by the user according to needs. The initial uncertainty threshold is reduced by a first preset value to reduce the number of calls to high-confidence simulations. Preferably, the first preset value is default configured to 10%. It should be understood that the first preset value can also be customized and defined by the user according to needs. represents the proportionality parameter of the th round of iteration. Among them, the proportionality parameter is adjusted based on the change trend of the uncertainty. Specifically, in a continuous preset number of iteration rounds, if the uncertainty shows an upward trend, the proportionality parameter is increased by a second preset value. If the uncertainty shows a downward trend, the proportionality parameter is increased by a second preset value. Preferably, assuming that the simulation error follows a Gaussian distribution, based on the running time, number of rounds, and expected total time of a single high-confidence simulation tool, the desired running frequency is obtained, and the second preset value is configured according to the percentile of the Gaussian distribution. For example, assuming that 5-10 high-confidence simulations are desired to run in 200 rounds of iteration, then 2 standard deviations of the Gaussian distribution, that is, the 95th percentile, is selected as the second preset value. It should be understood that the second preset value is more of an empirical choice and can be configured by the user according to needs. In the present invention, based on the uncertainty output by the error prediction model and the number of iterations, the uncertainty threshold is adjusted in real time to adjust the high-confidence simulation frequency, so as to achieve the best balance between accuracy and efficiency in the process of CPU design parameter exploration.

[0039] According to an embodiment of the present invention, if the uncertainty of the simulation error output by the error prediction model in the current iteration satisfies the constraint condition, that is, the uncertainty is less than the uncertainty threshold of the current iteration, the low-confidence performance index obtained in step S2 is corrected based on the predicted simulation error in step S3. Specifically, when the predicted simulation error is the difference between the high-confidence simulation and the low-confidence simulation, the result of adding the difference to the low-confidence performance index is used as the final performance index of the CPU design parameter sample to complete the correction of the low-confidence performance index. When the predicted simulation error is the difference ratio between the high-confidence simulation and the low-confidence simulation, the product of the low-confidence performance index and the ratio is used as the final performance index of the CPU design parameter sample to complete the correction of the low-confidence performance index. In order to update the parameters of the surrogate model in the Bayesian optimization device to make the surrogate model closer to the objective function, the present invention uses the CPU design parameter sample as the feature data and uses the final performance parameter of the CPU design parameter sample as the label to update the surrogate model in the Bayesian optimization device.

[0040] According to an embodiment of the present invention, if the uncertainty of the simulation error output by the error prediction model in the current iteration does not satisfy the constraint condition, that is, the uncertainty is greater than the uncertainty threshold of the current iteration, a high-confidence simulation tool is used to simulate the CPU design parameter sample to obtain the final performance index of the CPU design parameter sample, and then the Bayesian optimization device and the error prediction model are updated based on the obtained final performance index. Specifically, the CPU design parameter sample is used as the feature data and the final performance parameter of the CPU design parameter sample is used as the label to update the surrogate model in the Bayesian optimization device, and the CPU design parameter sample is used as the feature data, and the difference between the final performance parameter of the CPU design parameter sample and the low-confidence performance index of the CPU design parameter sample is used as the label to update the error prediction model.

[0041] In the multi-confidence Bayesian optimization adopted by the present invention, there is a higher requirement for the calibration accuracy of the optimal CPU design parameter samples selected by the acquisition function in each round, while the importance of calibrating other inferior CPU design parameter samples is lower. This means that only the calibration accuracy of the CPU design parameter samples in the historical iteration rounds is concerned during the iteration process. According to an embodiment of the present invention, in the present invention, whenever a preset number of iterations is executed, preferably, the preset number is 200. It should be understood that the preset number can be configured by the user according to needs. Multiple CPU design parameter samples are randomly sampled from the historical loop iterations as feature inputs, and the difference between the final performance index of each sampled CPU design parameter sample and the low-confidence performance index is used as a label for training a preset error prediction model. Compared with the existing exploration of CPU design parameters that mainly considers the diversity and representativeness of samples in the global space, the simulation frequency of CPU design parameters is reduced, thus significantly saving the simulation cost of CPU design parameter exploration.

[0042] According to an embodiment of the invention, in the present invention, the preset low-confidence simulation tool is any one of Gem5, ZSim, GPGPU-SIM, SESC, RTSim, and Simics, and the preset high-confidence simulation tool is an EDA simulation tool. It should be understood that the above-listed low-confidence and high-confidence simulation tools are well-known technologies to those skilled in the art and will not be described here. In addition, the present invention aims to combine the high-efficiency characteristics of low-confidence simulation tools with the high-accuracy characteristics of high-confidence simulation tools to provide a method that can effectively solve the contradiction between the accuracy and time consumption of different-confidence simulation tools and can efficiently explore CPU design parameters. The high-confidence and low-confidence simulation tools adopted are not limited, and any other CPU simulation tools that can achieve low-confidence and high-confidence simulations are acceptable.

[0043] Aiming at the long-existing problem of the trade-off between efficiency and accuracy in the process of microarchitecture design space exploration, the present invention proposes a multi-confidence Bayesian optimization device based on iterative path sampling calibration. This device focuses on improving the calibration accuracy of sample points on the search path by using the iterative path sampling method, effectively reducing the complexity of the problem, achieving low-cost and high-precision calibration of low-confidence simulation. At the same time, an accurate threshold calibration mechanism is used to dynamically adjust the threshold for calling high-confidence simulation. In addition, the present invention integrates the advantages of different-confidence simulation tools to achieve efficient multi-confidence Bayesian optimization, and this technology significantly improves the efficiency and accuracy of microarchitecture design space exploration.

[0044] It should be noted that although the above steps are described in a specific order, it does not mean that the steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order, as long as the required functions can be achieved.

[0045] The present invention can be a system, a method, and / or a computer program product. The computer program product may include a computer-readable storage medium having thereon computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0046] The computer-readable storage medium can be a tangible device that retains and stores instructions for use by an instruction execution device. The computer-readable storage medium may include, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically encoded device such as a punched card or raised structures in a groove having instructions stored thereon, and any suitable combination of the foregoing.

[0047] The embodiments of the present invention have been described above. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the market, or to enable other ordinary skill in the art in the technical field to understand the embodiments disclosed herein.

Claims

1. A method for exploring CPU microarchitecture parameters based on Bayesian optimization, which is used to explore multiple CPU design parameters that meet the performance requirements from a preset CPU design parameter space, and is characterized in that The method includes multiple rounds of iteration, where each round of iteration includes: Step S1: Using a pre-constructed Bayesian optimization device, select a CPU design parameter sample with the optimal performance index from the CPU design space according to the performance indexes of all CPU design parameters in the CPU design space; Step S2: Using a preset low-confidence simulation tool to simulate the CPU design parameter sample selected in Step S1 to obtain the low-confidence performance index and microarchitecture events of the CPU design parameter sample; Step S3: Using a preset error prediction model to predict the simulation error of the CPU design parameter sample selected in Step S1 and output the uncertainty of the predicted simulation error, where the simulation error is the difference between the performance indexes obtained when using a preset high-confidence simulation tool and a preset low-confidence simulation tool to simulate the same CPU design parameter sample; Step S4: Based on the uncertainty of the simulation error obtained in Step S3, obtain the final performance index of the CPU design parameter sample selected in Step S1 in a preset manner, update the Bayesian optimization device and the preset error prediction model, and retain the design parameters in the CPU design parameter sample obtained in the current iteration when the final performance index meets the required performance requirements.

2. The method according to claim 1, wherein The pre-constructed Bayesian optimization device includes a surrogate model and an acquisition function, where The surrogate model is a random forest model constructed based on the prior distribution of the objective function and used to fit the posterior distribution of the objective function. The surrogate model is updated based on the CPU design parameter samples and their final performance indexes in each round of iteration. The objective function is a mapping between the CPU design parameter samples and the performance indexes constructed based on prior knowledge; The acquisition function selects a CPU design parameter sample with the optimal performance from the CPU design space based on the posterior distribution of the objective function fitted by the surrogate model updated in each round.

3. The method according to claim 2, wherein The acquisition function is the expected Pareto hypervolume improvement function.

4. The method according to claim 1, characterized in that, The preset error prediction model is a prediction model constructed based on a random forest model or a Gaussian process probability model, which is configured to: predict the simulation error of the CPU design parameter sample to be predicted and output the uncertainty of the predicted simulation error based on the CPU design parameter sample to be predicted, the microarchitecture events of the CPU design parameter sample, and the performance index derived features deduced by a preset method.

5. The method according to claim 4, characterized in that, The preset method includes: Step T1: Pre-select multiple CPU design parameter samples from the preset CPU design space and use a preset low-confidence simulation tool to simulate all the selected CPU design parameter samples to obtain the low-confidence performance indexes of each CPU design parameter sample; Step T2: Calculate the maximum value, minimum value, and average value of all the obtained low-confidence performance indexes; Step T3: Calculate the differences between the low-confidence performance index of the CPU design parameter sample to be predicted and the maximum value, minimum value, and average value obtained in Step T2, and use the calculated differences as the performance index derived features of the CPU design parameter sample.

6. The method according to claim 1, wherein The preset manner is: When the uncertainty satisfies the constraint condition, the low confidence performance index obtained in step S2 is corrected based on the simulation error predicted in step S3, and the corrected low confidence performance index is used as the final performance index of the CPU design parameter sample selected in step S1, and the Bayesian optimization device is updated based on the CPU design parameter sample and its final performance index; When the uncertainty does not meet the constraint conditions, the CPU design parameter sample selected in step S1 is simulated using a preset high-confidence simulation tool to obtain a high-confidence performance index of the CPU design parameter sample, and this is used as the final performance index of the CPU design parameter sample. The Bayesian optimization device is updated based on the CPU design parameter sample and its final performance index, and the error prediction model is updated using the CPU design parameter sample as feature data and the difference between the high-confidence performance index of the CPU design parameter sample and the low-confidence performance index obtained in step S2 as a label.

7. The method according to claim 6, wherein The constraint condition is that the uncertainty of the error prediction model output in the current iteration round is less than the uncertainty threshold configured in the current iteration round.

8. The method according to claim 7, characterized in that, The uncertainty threshold for each iteration is configured in one of the following ways: Method 1: Pre-configure the uncertainty threshold in each iteration to a fixed value; Method 2: The uncertainty threshold of each iteration is configured as follows: ， Among them, represents the uncertainty threshold for the round of iteration, represents the initial uncertainty threshold, represents the proportionality parameter for the round of iteration. Among them, each time a preset number of loop iterations is executed, the initial uncertainty threshold is reduced by a first preset value, and in a continuous preset number of iteration rounds, if the uncertainty output by the error prediction model shows an upward trend, the proportionality parameter is increased by a second preset value, and if the uncertainty output by the error prediction model shows a downward trend, the proportionality parameter is increased by a second preset value.

9. The method according to claim 1, characterized in that, The method comprises: Each time a preset number of loop iterations are executed, multiple CPU design parameter samples are randomly collected from historical loop iterations as feature data, and the difference between the final performance index and the low confidence performance index of each collected CPU design parameter sample is used as the label of the CPU design parameter sample to train the preset error prediction model.

10. The method according to any one of claims 1, 2, 4, 5, 6, and 9, characterized in that, The performance index includes the power consumption and the number of instructions per clock cycle of the CPU.

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