Integrated circuit post-simulation verification method and device

Abstract

The invention relates to the technical field of circuit post-simulation verification, in particular to an integrated circuit post-simulation verification method and device, and the method comprises the steps: judging whether a simulation object is a preset function iteration object or not; if the simulation object does not belong to the time sequence annotation netlist, utilizing a post-simulation verification environment to obtain delay data and netlist data corresponding to the simulation object, and reversely marking the delay data into the netlist data to obtain the time sequence annotation netlist; performing post-simulation verification operation on the time sequence labeling netlist to obtain a first verification result; a first SDF pre-compiling file in the first verification result is stored in the SDF pre-compiling device; and when the simulation object is the function iteration object, obtaining a historical SDF pre-compiled file corresponding to the simulation object from the SDF pre-compiled device by utilizing the top layer simulation environment, and performing post-simulation verification operation on the simulation object according to the historical SDF pre-compiled file to obtain a second verification result. According to the invention, the post-simulation verification efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit post - simulation verification, and in particular to an integrated circuit post - simulation verification method and device. Background Art

[0002] Post - simulation can also be called timing simulation or post - placement - and - routing simulation. It mainly targets the netlist after placement and routing, adds timing analysis, and mainly verifies the timing correctness.

[0003] Currently, the main method of post - simulation is as follows: various delay parameters on the physical wires are marked on the netlist file in the form of back - annotation, and the actual device delay behavior is simulated in the simulation to check whether there are constraint errors during synthesis constraints. However, the above - mentioned method uses too many resources. During the debug process, the RTL needs to be frequently modified. After modification, there is a large amount of repetitive work when running the simulation again, and the post - simulation efficiency is low. Summary of the Invention

[0004] The present invention provides an integrated circuit post - simulation verification method, whose main purpose is to improve the post - simulation verification efficiency.

[0005] To achieve the above - mentioned purpose, an integrated circuit post - simulation verification method provided by the present invention includes: Obtain the top - level verification environment, the top - level simulation environment, and the SDF pre - compilation device, and obtain the simulation object; Use the top - level verification environment and the SDF pre - compilation device to determine whether the simulation object is a preset function iteration object; When the simulation object is not the function iteration object, use the post - simulation macro definition pre - built in the top - level simulation environment to call the pre - built post - simulation verification environment; Use the post - simulation verification environment to obtain the delay data and netlist data corresponding to the simulation object, back - annotate the delay data to the netlist data to obtain a timing - annotated netlist, and send the timing - annotated netlist to the top - level simulation environment; Use the top - level simulation environment to perform post - simulation verification operations on the timing - annotated netlist to obtain a first verification result, where the first verification result includes a first SDF pre - compilation file, a first FSDB waveform file, and a first simulation result; Store the first SDF pre - compilation file in the first verification result in the SDF pre - compilation device; When the simulation object is the function iteration object, use the top - level simulation environment to obtain the historical SDF pre - compilation file corresponding to the simulation object from the SDF pre - compilation device, and perform post - simulation verification operations on the simulation object according to the historical SDF pre - compilation file to obtain a second verification result.

[0006] Optionally, using the top-level verification environment and the SDF pre-compilation device to determine whether the simulation object is a preset function iteration object includes: Obtain each verified simulation object in the SDF pre-compilation device; Use the top-level verification environment to parse the simulation object to obtain SDF data and RTL data; Use the top-level verification environment to perform repeated judgment operations based on SDF and RTL on the simulation object and the verified simulation objects according to the SDF data and RTL data; When there is a verified simulation object in the SDF pre-compilation device with the same SDF data as the simulation object but different RTL data, determine that the simulation object is a preset function iteration object.

[0007] Optionally, using the post-simulation verification environment to obtain the delay data and netlist data corresponding to the simulation object, and backannotating the delay data to the netlist data to obtain a timing-annotated netlist includes: Use the post-simulation verification environment to call a pre-built UTL device, use the UTL device to call a pre-built DEF device, and use the DEF device to call a pre-built SDF device; Use the UTL device to call a pre-built NETLIST device; Use the NETLIST device to obtain a NETLIST file according to the simulation object, and obtain netlist data from the NETLIST file; Use the SDF device to obtain an SDF file according to the simulation object, and obtain delay data from the SDF file; Use the UTL device to summarize the netlist data and delay data, and use the post-simulation verification environment to backannotate the delay data to the netlist data to obtain a timing-annotated netlist.

[0008] Optionally, using the SDF device to obtain an SDF file according to the simulation object includes: Obtain a component timing library; Use a pre-built timing filtering device to perform marking operations on the timings belonging to a preset low-attention timing type in the component timing library to obtain a marked timing set; When the SDF device obtains a timing set from the component timing library according to the simulation object to form an SDF file, delete the marked timing set in the timing set to obtain an SDF file.

[0009] Optionally, the post-simulation verification operation on the timing annotation netlist using the top-level simulation environment to obtain a first verification result includes: Invoking a pre-built EDA tool using the simulation instructions pre-built in the top-level simulation environment; Performing a post-simulation verification operation on the timing annotation netlist using the EDA tool to obtain a first SDF pre-compiled file, a first FSDB waveform file, and a first simulation result; Aggregating the first SDF pre-compiled file, the first FSDB waveform file, and the first simulation result to obtain a first verification result.

[0010] Optionally, the second verification result includes a second FSDB waveform file and a second simulation result.

[0011] Optionally, storing the first SDF pre-compiled file in the first verification result in the SDF pre-compilation device includes: Extracting the first SDF pre-compiled file from the first verification result; Storing the first SDF pre-compiled file in the SDF pre-compilation device according to the pre-built path storage in the top-level simulation environment.

[0012] To achieve the above object, the present invention further provides an integrated circuit post-simulation verification device, including: An object verification module, configured to obtain a top-level verification environment, a top-level simulation environment, and an SDF pre-compilation device, obtain a simulation object, and use the top-level verification environment and the SDF pre-compilation device to determine whether the simulation object is a preset function iteration object; A post-simulation verification module, configured to, when the simulation object is not the function iteration object, use the post-simulation macro definition pre-built in the top-level simulation environment to invoke the pre-built post-simulation verification environment, and use the post-simulation verification environment to obtain the delay data and netlist data corresponding to the simulation object, and back-annotate the delay data to the netlist data to obtain a timing annotation netlist, and send the timing annotation netlist to the top-level simulation environment; The top-level simulation module is used to perform post-simulation verification operations on the timing-annotated netlist using the top-level simulation environment to obtain a first verification result. The first verification result includes a first SDF pre-compiled file, a first FSDB waveform file, and a first simulation result. The first SDF pre-compiled file in the first verification result is stored in the SDF pre-compilation device. When the simulation object is the function iteration object, the historical SDF pre-compiled file corresponding to the simulation object is obtained from the SDF pre-compilation device using the top-level simulation environment, and post-simulation verification operations are performed on the simulation object based on the historical SDF pre-compiled file to obtain a second verification result.

[0013] Optionally, using the top-level verification environment and the SDF pre-compilation device to determine whether the simulation object is a preset function iteration object includes: Obtain each verified simulation object in the SDF pre-compilation device; Use the top-level verification environment to parse the simulation object to obtain SDF data and RTL data; Use the top-level verification environment to perform repeated judgment operations based on SDF and RTL on the simulation object and each of the verified simulation objects according to the SDF data and RTL data; When there is a verified simulation object in the SDF pre-compilation device with the same SDF data as the simulation object but different RTL data, determine that the simulation object is a preset function iteration object.

[0014] Optionally, using the post-simulation verification environment to obtain the delay data and netlist data corresponding to the simulation object, and backannotating the delay data to the netlist data to obtain a timing-annotated netlist includes: Use the post-simulation verification environment to call a pre-built UTL device, use the UTL device to call a pre-built DEF device, and use the DEF device to call a pre-built SDF device; Use the UTL device to call a pre-built NETLIST device; Use the NETLIST device to obtain a NETLIST file according to the simulation object, and obtain netlist data from the NETLIST file; Use the SDF device to obtain an SDF file according to the simulation object, and obtain delay data from the SDF file; Use the UTL device to summarize the netlist data and delay data, and use the post-simulation verification environment to backannotate the delay data to the netlist data to obtain a timing-annotated netlist.

[0015] To solve the above problems, the present invention also provides an electronic device, which includes: A memory for storing at least one instruction; A processor for executing the instruction stored in the memory to implement the integrated circuit post-simulation verification method described above.

[0016] To solve the above problems, the present invention also provides a computer-readable storage medium, in which at least one instruction is stored, and the at least one instruction is executed by a processor in an electronic device to implement the integrated circuit post-simulation verification method described above.

[0017] To solve the problems described in the background art, the present invention pre-verifies the SDF information of each simulation object. When the simulation object is not a function iteration object, it indicates that the simulation object is relatively novel and has not undergone a post-simulation verification process. It is possible to construct a timing annotation netlist for post-verification simulation as in the traditional post-verification method. However, in the present invention, when constructing the timing annotation netlist, the netlist data and delay data required in the timing annotation netlist are separately managed, and the delay data is recorded and monitored. When the simulation object is a function iteration object, it indicates that the simulation device has simulated a similar simulation object before. Then, the past data can be directly called from the recorded and monitored delay data without reconstructing the delay data, thereby improving the post-simulation verification efficiency. Therefore, the present invention can improve the post-simulation verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic flowchart of the integrated circuit post-simulation verification method provided by an embodiment of the present invention; Figure 2 It is a schematic structural diagram of the device of the integrated circuit post-simulation verification method provided by an embodiment of the present invention; Figure 3 It is a functional module diagram of the integrated circuit post-simulation verification device provided by an embodiment of the present invention; Figure 4 It is a schematic structural diagram of the electronic device for implementing the integrated circuit post-simulation verification method provided by an embodiment of the present invention.

[0019] DESCRIPTION OF THE REFERENCE NUMERALS: 1. Electronic device; 10. Processor; 11. Memory; 12. Bus.

[0020] The realization, functional characteristics and advantages of the object of the present invention will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0022] An embodiment of the present application provides a method for post-simulation verification of an integrated circuit. The execution subject of the method for post-simulation verification of the integrated circuit includes, but is not limited to, at least one of electronic devices such as a server, a terminal, etc. that can be configured to execute the method provided by the embodiment of the present application. In other words, the method for post-simulation verification of the integrated circuit can be executed by software or hardware installed on a terminal device or a server device, and the software can be a blockchain platform. The server includes, but is not limited to: a single server, a server cluster, a cloud server, or a cloud server cluster, etc.

[0023] Referring to Figure 1 As shown, it is a schematic flowchart of the method for post-simulation verification of an integrated circuit provided by an embodiment of the present invention. In this embodiment, the method for post-simulation verification of the integrated circuit includes: S1. Obtain a top-level verification environment, a top-level simulation environment, and an SDF pre-compilation device, and obtain a simulation object.

[0024] Among them, the top-level verification environment refers to a computing environment for supporting the judgment of the function of the function iteration object.

[0025] Among them, the top-level simulation environment refers to a working environment for supporting the EDA tool to retrieve data and execute the simulation process. The EDA (Electronic Design Automation) tool refers to electronic design automation, which is an industrial software for assisting in the design of very large-scale integrated circuits.

[0026] Among them, the SDF pre-compilation device is a device for managing SDF pre-compilation files.

[0027] Among them, the simulation object refers to an object that needs to be post-simulation verified, including the component distribution and connection information of the integrated circuit, as well as the scenarios, functional areas, etc. that need to be post-simulation verified.

[0028] Specifically, in the embodiment of the present invention, as Figure 2 shown, a post-simulation verification environment, a top-level simulation environment, and an SDF pre-compilation device are constructed. Among them, the post-simulation verification environment includes an SDF device, a DEF device, a NETLIST device, and a UTL device. Among them, the Figure 2 FSDB file and simulation result in are the output results of this solution.

[0029] Specifically, in the embodiment of the present invention, the post-simulation verification environment is enabled through post-simulation macro definition (macro definition POSTGSIM) in the top-level simulation verification environment (TB_TOP). The process is as follows: First, TB_TOP calls the UTL device through POSTGSIM. Among them, the UTL device is the overall scheduling device of the post-simulation verification environment. The UTL device divides the SDF back-annotation work of the post-simulation verification into different verification case scenarios. By setting the macro definition of the corresponding case in the top-level simulation environment, the SDF device of the corresponding case is subsequently called and integrated into the top-level simulation environment.

[0030] In the embodiment of the present invention, the UTL device can be used to simultaneously call the NETLIST device to obtain the netlist and call the DEF device to obtain the SDF file. Finally, the timing information in the SDF file is back-annotated to the netlist by the environment at a higher level of the UTL device (the top level of the overall post-simulation verification environment) to generate a netlist verification file with timing information.

[0031] Specifically, in the embodiment of the present invention, the NETLIST device is a netlist management device. During the process of compiling and verifying the environment of the EDA tool, by calling the NETLIST device, the local storage path of the NETLIST file can be obtained, and further the netlist of the integrated circuit is integrated into the post-top-level verification environment. Among them, in order to realize multi-person collaboration in the present invention, the storage path of the NETLIST file in the NETLIST device is a relative path. By defining the user address variable, the post-simulation verification is carried out in the user's local workspace. Among them, the NETLIST (netlist) is a file that converts the logic / circuit design RTL into a physical implementation, and is composed of cells, pins, ports, and Nets.

[0032] Specifically, the DEF (Define) device is a CORNER management device, and different CORNER scenarios can be called through simulation instructions, such as the maximum process corner of high temperature and high pressure, and three or more process corners can be set. Further, CORNER calls its corresponding SDF device. Among them, the CORNER (corner): there are process deviations during the chip production process. According to different temperatures, processes, and voltages, the scenarios are divided into multiple corners. Adding the corner conditions in the post-simulation is to ensure that the chip can work properly in extreme scenarios, such as high temperature, high voltage, fast transistors, and minimum capacitance x resistance.

[0033] Specifically, in the embodiments of the present invention, the SDF device is an SDF file management device. To enable multi-person collaboration, the storage path of the SDF file is also a relative path. By defining user address variables, post-simulation verification is performed in the local workspace of the user. Among them, the SDF file is set and generated by the EDA tool according to the component timing library and process requirements. The SDF (standard delay format) describes the delay data of the units and interconnection lines after the circuit layout and wiring. Its main function is to back annotate the delay information into the functional model to simulate the state of the chip during actual operation.

[0034] S2. Use the top-level verification environment and the SDF pre-compilation device to determine whether the simulation object is a preset function iteration object.

[0035] Specifically, in the embodiments of the present invention, the step of using the top-level verification environment and the SDF pre-compilation device to determine whether the simulation object is a preset function iteration object includes: Obtain each verified simulation object in the SDF pre-compilation device; Use the top-level verification environment to parse the simulation object to obtain SDF data and RTL data; Use the top-level verification environment to perform a repeated judgment operation based on SDF and RTL on the simulation object and each of the verified simulation objects according to the SDF data and RTL data; When there is a verified simulation object in the SDF pre-compilation device with the same SDF data as the simulation object but different RTL data, determine that the simulation object is a preset function iteration object.

[0036] Among them, each of the verified simulation objects refers to a set of simulation objects that have undergone the post-verification process.

[0037] Among them, the parsing refers to the process of extracting key information from the simulation object, including at least SDF data and RTL data. The RTL (Register Transfer Level) is a code used to describe the behavior of the circuit at the register transfer level and belongs to a type of hardware description language (HDL). RTL code is specifically used to describe the behavior of the circuit at the register transfer level, that is, how to transfer data between registers and when to trigger these transfers. It describes the relationship between the registers in the circuit, such as data transfer and control logic between registers.

[0038] Among them, the repeated judgment operation refers to the process of determining whether there is equivalent data for the SDF data in the SDF pre-compilation device through methods such as file structure checking and syntax checking.

[0039] Specifically, in the embodiments of the present invention, first, each verified simulation object is obtained from the SDF pre-compilation device, and then the key information of the simulation object is parsed to obtain SDF data and RTL data. Through repeated judgment operations, it is determined whether the SDF data and RTL data already exist in the SDF pre-compilation device. If neither the SDF data nor the RTL data exists, it indicates that the simulation object is relatively novel and is a brand-new type of simulation object. If both the SDF data and the RTL data exist, it indicates that the simulation object may be repeatedly post-simulated. If the SDF data exists but the RTL data does not, it indicates that the component distribution circuit of the simulation object has been recorded, but post-simulation needs to be performed on the new verification area or function.

[0040] Specifically, in the embodiments of the present invention, when there is a verified simulation object in the SDF pre-compilation device that has the same SDF data as the simulation object but different RTL data, it is determined that the simulation object is a preset function iteration object.

[0041] When the simulation object is not the function iteration object, S3. Use the pre-built post-simulation macro definition in the top-level simulation environment to call the pre-built post-simulation verification environment.

[0042] Among them, the macro definition (Macro Definition) is an important mechanism in the C language that allows programmers to define an identifier in the source code so that the identifier can be used to replace a specific value or code block in the subsequent code.

[0043] Specifically, in the embodiments of the present invention, the Figure 2 process in the post-simulation verification environment part is coded, and the post-simulation macro definition (macro definition POSTGSIM) is used for substitution.

[0044] Therefore, in the embodiments of the present invention, as long as the macro definition POSTGSIM is called in the top-level verification environment, the actions in the simulation verification environment part will be automatically executed.

[0045] S4. Use the post-simulation verification environment to obtain the delay data and netlist data corresponding to the simulation object, back-annotate the delay data to the netlist data to obtain a timing-annotated netlist, and send the timing-annotated netlist to the top-level simulation environment.

[0046] In the embodiments of the present invention, the delay data refers to the data content in the SDF file. The netlist data refers to the data content in the NETLIST file.

[0047] Among them, the back-annotation refers to the process of dynamically injecting (annotating) the actual delay information extracted in the physical design stage into the gate-level netlist file to replace the original ideal delay value.

[0048] Among them, the timing annotation netlist refers to the result of the timing marks in the delay data to the netlist data.

[0049] Specifically, in the embodiment of the present invention, the method of using the post-simulation verification environment to obtain the delay data and netlist data corresponding to the simulation object, and backannotating the delay data into the netlist data to obtain a timing annotation netlist includes: Using the post-simulation verification environment to call a pre-built UTL device, using the UTL device to call a pre-built DEF device, and using the DEF device to call a pre-built SDF device; Using the UTL device to call a pre-built NETLIST device; Using the NETLIST device to obtain a NETLIST file according to the simulation object, and obtaining netlist data from the NETLIST file; Using the SDF device to obtain an SDF file according to the simulation object, and obtaining delay data from the SDF file; Using the UTL device to summarize the netlist data and delay data, and using the post-simulation verification environment to backannotate the delay data into the netlist data to obtain a timing annotation netlist.

[0050] Specifically, in the embodiment of the present invention, referring to Figure 2 it can be known that the post-simulation verification environment calls the UTL device. One route is that the UTL device calls the DEF device, and the DEF device calls the SDF device. Another route is that the UTL device calls the NETLIST device. And the SDF device is responsible for managing the SDF file, and the NETLIST device is responsible for managing the NETLIST file. Therefore, after the SDF device and the NETLIST device are activated, the SDF file and the NETLIST file can be directly obtained, and then the key information therein can be obtained to obtain the netlist data and the delay data.

[0051] Then use the UTL device to summarize and send the netlist data and delay data to the top-level environment of the post-simulation verification environment, and backannotate the delay data into the netlist data to obtain a timing annotation netlist.

[0052] Specifically, in the embodiment of the present invention, the method of using the SDF device to obtain an SDF file according to the simulation object includes: Obtain the component timing library; Using a pre-built timing filtering device to perform a marking operation on the timings belonging to a preset low-attention timing type in the component timing library to obtain a marked timing set; When the SDF device obtains a timing set from the component timing library according to the simulation object to form an SDF file, the marked timing set in the timing set is deleted to obtain the SDF file.

[0053] Among them, the component timing library refers to the storage of the timing of all electronic components in all integrated circuits in the enterprise. Timing refers to the time length required for a signal to pass through a certain component.

[0054] Among them, the timing filtering device refers to a device that deletes the timing of some components in the SDF file, and is used to turn off the timing check of a certain component during the post-simulation process.

[0055] Among them, the low-attention timing type refers to the timing that post-simulation technicians do not care about, such as the first stage of synchronization, etc. The marked timing set refers to the set of timings marked by the low-attention timing type.

[0056] Specifically, in the embodiment of the present invention, the post-simulation verification environment may further include a timing filtering device to uniformly manage the timings that relevant technicians do not care about, such as the first stage of synchronization, and define instructions recognizable by EDA tools. In the embodiment of the present invention, during the compilation process of the top-level verification environment, through instructions, the timing filtering device is called to further obtain the component path in the timing preprocessing device, and the timing check of this component is turned off during the post-simulation verification process. The filtering device includes, but is not limited to, methods such as set_false_path and no_timing_check.

[0057] S5. Use the top-level simulation environment to perform post-simulation verification operations on the timing-annotated netlist to obtain a first verification result, where the first verification result includes a first SDF pre-compiled file, a first FSDB waveform file, and a first simulation result.

[0058] Among them, the post-simulation verification operation refers to the specific simulation working process of the EDA tool.

[0059] Among them, the first verification result refers to the post-simulation result of the simulation object that is not the object of function iteration. The first verification result includes a first SDF pre-compiled file, a first FSDB waveform file, and a first simulation result. Among them, the "first" is used to distinguish the "second" represented by the post-simulation result of the simulation object of the subsequent function iteration object type.

[0060] Among them, the SDF pre-compiled file includes the first compilation result, that is, the header file that passes the compilation check, and the header file is used to call each SDF file.

[0061] Among them, the simulation result is a record of the simulation process, including but not limited to the compilation process log, the simulation process log, and the timing violation log. The FSDB waveform file is a high-performance waveform file format dedicated to digital circuit simulation and verification.

[0062] Specifically, in the embodiment of the present invention, the post-simulation verification operation of the timing annotation netlist by using the top-level simulation environment to obtain a first verification result includes: Using the simulation instructions pre-built in the top-level simulation environment to call the pre-built EDA tool; Using the EDA tool to perform a post-simulation verification operation on the timing annotation netlist to obtain a first SDF pre-compiled file, a first FSDB waveform file, and a first simulation result; Summarizing the first SDF pre-compiled file, the first FSDB waveform file, and the first simulation result to obtain a first verification result.

[0063] Among them, the simulation instruction refers to an instruction for controlling the working state of the EDA tool.

[0064] Specifically, in the embodiment of the present invention, first, according to the simulation instruction, an EDA tool is called, and then the EDA tool is used to execute the timing annotation netlist to obtain a first SDF pre-compiled file, a first FSDB waveform file, and a first simulation result. Finally, the above three types of results are summarized to obtain a first verification result.

[0065] S6. Store the first SDF pre-compiled file in the first verification result into the SDF pre-compilation device.

[0066] Specifically, in the embodiment of the present invention, storing the first SDF pre-compiled file in the first verification result into the SDF pre-compilation device includes: Extracting the first SDF pre-compiled file in the first verification result; According to the path storage pre-built in the top-level simulation environment, storing the first SDF pre-compiled file into the SDF pre-compilation device.

[0067] Among them, the path storage refers to the storage address of the SDF pre-compiled file in the SDF pre-compilation device, which is used to quickly find the file.

[0068] Specifically, in the embodiment of the present invention, the SDF pre-compiled file is stored in the pre-compilation device according to the path specified in the post-simulation verification environment, and can be used for the simulation after subsequent RTL modification.

[0069] When the simulation object is the function iteration object, S7. Utilize the top-level simulation environment to obtain, from the SDF pre-compilation device, the historical SDF pre-compilation file corresponding to the simulation object, and based on the historical SDF pre-compilation file, perform a post-simulation verification operation on the simulation object to obtain a second verification result.

[0070] When the simulation object is the function iteration object, it indicates that the circuit structure of the current simulation object already exists and may be a device modified after product iteration. Therefore, it is possible to directly obtain the historical SDF pre-compilation file corresponding to the simulation object without performing the post-simulation verification environment.

[0071] Specifically, in the embodiment of the present invention, the second verification result includes a second FSDB waveform file and a second simulation result. Since the SDF pre-compilation file uses the historical SDF pre-compilation file, the SDF pre-compilation file in the second verification result is optional.

[0072] Specifically, in the embodiment of the present invention, for the post-simulation verification of modifying the RTL without modifying the SDF file, directly call the SDF pre-compilation device through a simulation instruction, further call the SDF pre-compilation file, and integrate the SDF pre-compilation file into the top-level simulation verification environment. Since the SDF file is not modified, the SDF compilation result in the SDF pre-compilation file can be directly called, and there is no need to recompile the SDF file, reducing the number of SDF file compilations and improving the post-simulation verification efficiency.

[0073] To solve the problems described in the background art, the present invention pre-verifies the SDF information of each simulation object. When the simulation object is not the function iteration object, it indicates that the simulation object is relatively novel and has not undergone the post-simulation verification process. Thus, a timing annotation netlist can be constructed for post-verification simulation as in the traditional post-verification method. However, in the present invention, when constructing the timing annotation netlist, the netlist data and delay data required in the timing annotation netlist are separately managed, and the delay data is recorded and monitored. When the simulation object is the function iteration object, it indicates that the simulation device has previously simulated a similar simulation object. Then, the past data can be directly called from the recorded and monitored delay data without reconstructing the delay data, thereby improving the post-simulation verification efficiency. Therefore, the present invention can improve the post-simulation verification efficiency.

[0074] As Figure 2 shown, it is a functional module diagram of an integrated circuit post-simulation verification device provided by an embodiment of the present invention.

[0075] The integrated circuit post-simulation verification device 100 according to the present invention can be installed in an electronic device. According to the functions achieved, the integrated circuit post-simulation verification device 100 can include an object verification module 101, a post-simulation verification module 102, and a top-level simulation module 103. The modules in the present invention can also be referred to as units, which refer to a series of computer program segments that can be executed by a processor of an electronic device and can complete fixed functions, and are stored in the memory of the electronic device.

[0076] The object verification module 101 is configured to obtain a top-level verification environment, a top-level simulation environment, and an SDF pre-compilation device, obtain a simulation object, and use the top-level verification environment and the SDF pre-compilation device to determine whether the simulation object is a preset function iteration object; The post-simulation verification module 102 is configured to, when the simulation object is not the function iteration object, use the post-simulation macro definition pre-built in the top-level simulation environment, call the pre-built post-simulation verification environment, and use the post-simulation verification environment to obtain the delay data and netlist data corresponding to the simulation object, and backannotate the delay data to the netlist data to obtain a timing-annotated netlist, and send the timing-annotated netlist to the top-level simulation environment; The top-level simulation module 103 is configured to use the top-level simulation environment to perform a post-simulation verification operation on the timing-annotated netlist to obtain a first verification result, where the first verification result includes a first SDF pre-compilation file, a first FSDB waveform file, and a first simulation result, and store the first SDF pre-compilation file in the first verification result in the SDF pre-compilation device, and when the simulation object is the function iteration object, use the top-level simulation environment to obtain the historical SDF pre-compilation file corresponding to the simulation object from the SDF pre-compilation device, and perform a post-simulation verification operation on the simulation object according to the historical SDF pre-compilation file to obtain a second verification result.

[0077] Specifically, each module in the integrated circuit post-simulation verification device 100 in the embodiment of the present invention uses the same technical means as those in the Figure 1 integrated circuit post-simulation verification method described above and can produce the same technical effects, which will not be elaborated here.

[0078] As Figure 4 shown, it is a schematic structural diagram of an electronic device for implementing an integrated circuit post-simulation verification method provided by an embodiment of the present invention.

[0079] The electronic device 1 may include a processor 10, a memory 11, and a bus 12, and may also include a computer program stored in the memory 11 and executable on the processor 10, such as an integrated circuit post-simulation verification method program.

[0080] Among them, the memory 11 includes at least one type of readable storage medium, and the readable storage medium includes flash memory, mobile hard disk, multimedia card, card-type memory (such as SD or DX memory, etc.), magnetic memory, magnetic disk, optical disc, etc. In some embodiments, the memory 11 may be an internal storage unit of the electronic device 1, such as the mobile hard disk of the electronic device 1. In some other embodiments, the memory 11 may also be an external storage device of the electronic device 1, such as a plug-in mobile hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. equipped on the electronic device 1. Further, the memory 11 also includes the internal storage unit of the electronic device 1 and also includes an external storage device. The memory 11 can be used not only to store application software installed on the electronic device 1 and various types of data, such as the code of the integrated circuit post-simulation verification method program, etc., but also to temporarily store data that has been output or will be output.

[0081] In some embodiments, the processor 10 may be composed of integrated circuits. For example, it may be composed of a single packaged integrated circuit, or may be composed of multiple integrated circuits with the same or different functions, including a combination of one or more Central Processing Units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips, etc. The processor 10 is the control core (Control Unit) of the electronic device, connecting various components of the entire electronic device through various interfaces and lines, and by running or executing programs or modules (such as the integrated circuit post-simulation verification method program, etc.) stored in the memory 11, and calling data stored in the memory 11, to execute various functions of the electronic device 1 and process data.

[0082] The bus 12 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This bus 12 can be divided into an address bus, a data bus, a control bus, etc. The bus 12 is set to realize the connection and communication between the memory 11 and at least one processor 10, etc.

[0083] Figure 4 Only an electronic device with components is shown. Those skilled in the art can understand that Figure 4 the shown structure does not constitute a limitation on the electronic device 1, and it may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0084] For example, although not shown, the electronic device 1 may further include a power source (such as a battery) for supplying power to each component. Preferably, the power source can be logically connected to the at least one processor 10 through a power management device, so as to implement functions such as charging management, discharging management, and power consumption management through the power management device. The power source may also include any components such as one or more DC or AC power sources, a recharge device, a power failure detection circuit, a power converter or inverter, a power status indicator, etc. The electronic device 1 may also include various sensors, a Bluetooth module, a Wi-Fi module, etc., which will not be elaborated here.

[0085] Furthermore, the electronic device 1 may further include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), which is generally used to establish a communication connection between the electronic device 1 and other electronic devices.

[0086] Optionally, the electronic device 1 may further include a user interface. The user interface may be a display, an input unit (such as a keyboard), and optionally, the user interface may also be a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch liquid crystal display, and an OLED (Organic Light-Emitting Diode) toucher, etc. Among them, the display may also be appropriately referred to as a display screen or a display unit, which is used to display the information processed in the electronic device 1 and to display a visual user interface.

[0087] The integrated circuit post-simulation verification method program stored in the memory 11 of the electronic device 1 is a combination of multiple instructions. When running in the processor 10, it can implement: Obtain a top-level verification environment, a top-level simulation environment, and an SDF pre-compilation device, and obtain a simulation object; Use the top-level verification environment and the SDF pre-compilation device to determine whether the simulation object is a preset function iteration object; When the simulation object is not the function iteration object, use the post-simulation macro definition pre-built in the top-level simulation environment to call the pre-built post-simulation verification environment; Using the post-simulation verification environment, obtain the delay data and netlist data corresponding to the simulation object, and backannotate the delay data into the netlist data to obtain a timing-annotated netlist, and send the timing-annotated netlist to the top-level simulation environment; Using the top-level simulation environment, perform a post-simulation verification operation on the timing-annotated netlist to obtain a first verification result, where the first verification result includes a first SDF pre-compiled file, a first FSDB waveform file, and a first simulation result; Store the first SDF pre-compiled file in the first verification result in the SDF pre-compilation device; When the simulation object is the function iteration object, use the top-level simulation environment to obtain the historical SDF pre-compiled file corresponding to the simulation object from the SDF pre-compilation device, and perform a post-simulation verification operation on the simulation object according to the historical SDF pre-compiled file to obtain a second verification result.

[0088] Specifically, the specific implementation method of the above instructions by the processor 10 can refer to Figures 1 to 4 the description of the relevant steps in the corresponding embodiment, which will not be elaborated here.

[0089] Furthermore, if the modules / units integrated in the electronic device 1 are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium can include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a mobile hard disk, a magnetic disk, an optical disc, a computer memory, a read-only memory (ROM, Read-Only Memory).

[0090] The present invention also provides a computer-readable storage medium, where the readable storage medium stores a computer program, and when the computer program is executed by a processor of an electronic device, it can implement: Obtain a top-level verification environment, a top-level simulation environment, and an SDF pre-compilation device, and obtain a simulation object; Use the top-level verification environment and the SDF pre-compilation device to determine whether the simulation object is a preset function iteration object; When the simulation object is not the function iteration object, use the pre-built post-simulation macro definition in the top-level simulation environment to call the pre-built post-simulation verification environment; Using the post-simulation verification environment, obtain the delay data and netlist data corresponding to the simulation object, and backannotate the delay data into the netlist data to obtain a timing-annotated netlist, and send the timing-annotated netlist to the top-level simulation environment; Using the top-level simulation environment, perform post-simulation verification operations on the timing annotation netlist to obtain a first verification result, where the first verification result includes a first SDF pre-compiled file, a first FSDB waveform file, and a first simulation result; Store the first SDF pre-compiled file in the first verification result in the SDF pre-compilation device; When the simulation object is the function iteration object, use the top-level simulation environment to obtain the historical SDF pre-compiled file corresponding to the simulation object from the SDF pre-compilation device, and perform post-simulation verification operations on the simulation object according to the historical SDF pre-compiled file to obtain a second verification result.

[0091] In several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative, and there may be other partitioning methods in actual implementation.

[0092] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0093] In addition, each functional module in various embodiments of the present invention can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above integrated unit can be implemented in the form of hardware, or in the form of a combination of hardware and software functional modules.

[0094] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. An integrated circuit post-simulation verification method, characterized in that The method includes: Obtain a top-level verification environment, a top-level simulation environment, and an SDF pre-compilation device, and obtain a simulation object; Use the top-level verification environment and the SDF pre-compilation device to determine whether the simulation object is a preset function iteration object; When the simulation object is not the function iteration object, use the post-simulation macro definition pre-constructed in the top-level simulation environment to call the pre-constructed post-simulation verification environment; Use the post-simulation verification environment to obtain the delay data and netlist data corresponding to the simulation object, and back-annotate the delay data into the netlist data to obtain a timing-annotated netlist, and send the timing-annotated netlist to the top-level simulation environment; Use the top-level simulation environment to perform a post-simulation verification operation on the timing-annotated netlist to obtain a first verification result, where the first verification result includes a first SDF pre-compilation file, a first FSDB waveform file, and a first simulation result; Store the first SDF pre-compilation file in the first verification result in the SDF pre-compilation device; When the simulation object is the function iteration object, use the top-level simulation environment to obtain the historical SDF pre-compilation file corresponding to the simulation object from the SDF pre-compilation device, and perform a post-simulation verification operation on the simulation object according to the historical SDF pre-compilation file to obtain a second verification result.

2. The integrated circuit post-simulation verification method according to claim 1, wherein The step of using the top-level verification environment and the SDF pre-compilation device to determine whether the simulation object is a preset function iteration object includes: Obtain each verified simulation object in the SDF pre-compilation device; Use the top-level verification environment to parse the simulation object to obtain SDF data and RTL data; Use the top-level verification environment to perform a repeated determination operation based on SDF and RTL on the simulation object and each of the verified simulation objects according to the SDF data and RTL data; When there is a verified simulation object in the SDF pre-compilation device with the same SDF data as the simulation object but different RTL data, determine that the simulation object is a preset function iteration object.

3. The integrated circuit post-simulation verification method according to claim 2, wherein The step of using the post-simulation verification environment to obtain the delay data and netlist data corresponding to the simulation object, and back-annotate the delay data into the netlist data to obtain a timing-annotated netlist includes: Use the post-simulation verification environment to call a pre-constructed UTL device, use the UTL device to call a pre-constructed DEF device, and use the DEF device to call a pre-constructed SDF device; Use the UTL device to call a pre-constructed NETLIST device; Use the NETLIST device to obtain a NETLIST file according to the simulation object, and obtain netlist data from the NETLIST file; Use the SDF device to obtain an SDF file according to the simulation object, and obtain delay data from the SDF file; Use the UTL device to summarize the netlist data and the delay data, and use the post-simulation verification environment to back-annotate the delay data into the netlist data to obtain a timing-annotated netlist.

4. The integrated circuit post-simulation verification method according to claim 3, wherein Using the SDF device to obtain an SDF file according to the simulation object includes: Obtaining a component timing library; Using a pre-built timing filtering device to perform a marking operation on the timings belonging to a preset low-attention timing type in the component timing library to obtain a marked timing set; When the SDF device obtains a timing set from the component timing library according to the simulation object to form an SDF file, deleting the marked timing set in the timing set to obtain an SDF file.

5. The integrated circuit post-simulation verification method according to claim 4, wherein, Using the top-level simulation environment to perform a post-simulation verification operation on the timing-annotated netlist to obtain a first verification result, including: Using the pre-built simulation instructions in the top-level simulation environment to call a pre-built EDA tool; Using the EDA tool to perform a post-simulation verification operation on the timing-annotated netlist to obtain a first SDF pre-compiled file, a first FSDB waveform file, and a first simulation result; Summarizing the first SDF pre-compiled file, the first FSDB waveform file, and the first simulation result to obtain a first verification result.

6. The integrated circuit post-simulation verification method according to claim 5, wherein The second verification result includes a second FSDB waveform file and a second simulation result.

7. The integrated circuit post-simulation verification method according to claim 6, wherein Storing the first SDF pre-compiled file in the first verification result in the SDF pre-compilation device includes: Extracting the first SDF pre-compiled file in the first verification result; Storing the first SDF pre-compiled file in the SDF pre-compilation device according to the pre-built path storage in the top-level simulation environment.

8. An integrated circuit post-simulation verification device, characterized in that, The device includes: An object verification module, configured to obtain a top-level verification environment, a top-level simulation environment, and an SDF pre-compilation device, obtain a simulation object, and use the top-level verification environment and the SDF pre-compilation device to determine whether the simulation object is a preset function iteration object; A post-simulation verification module, configured to, when the simulation object is not the function iteration object, use the pre-built post-simulation macro definition in the top-level simulation environment to call a pre-built post-simulation verification environment, and use the post-simulation verification environment to obtain delay data and netlist data corresponding to the simulation object, and back-annotate the delay data to the netlist data to obtain a timing-annotated netlist, and send the timing-annotated netlist to the top-level simulation environment; A top-level simulation module, configured to use the top-level simulation environment to perform a post-simulation verification operation on the timing-annotated netlist to obtain a first verification result, where the first verification result includes a first SDF pre-compiled file, a first FSDB waveform file, and a first simulation result, and store the first SDF pre-compiled file in the first verification result in the SDF pre-compilation device, and when the simulation object is the function iteration object, use the top-level simulation environment to obtain a historical SDF pre-compiled file corresponding to the simulation object from the SDF pre-compilation device, and perform a post-simulation verification operation on the simulation object according to the historical SDF pre-compiled file to obtain a second verification result.

9. The integrated circuit post-simulation verification device according to claim 8, wherein, Using the top-level verification environment and the SDF pre-compilation device to determine whether the simulation object is a preset function iteration object includes: Obtain each verified simulation object in the SDF pre-compilation device; Use the top-level verification environment to parse the simulation object to obtain SDF data and RTL data; Use the top-level verification environment to perform repeated judgment operations based on SDF and RTL on the simulation object and each of the verified simulation objects according to the SDF data and RTL data; When there is a verified simulation object in the SDF pre-compilation device with the same SDF data as the simulation object but different RTL data, determine that the simulation object is a preset function iteration object.

10. The integrated circuit post-simulation verification device according to claim 9, wherein Using the post-simulation verification environment to obtain the delay data and netlist data corresponding to the simulation object, and backannotating the delay data to the netlist data to obtain a timing-annotated netlist includes: Use the post-simulation verification environment to call a pre-built UTL device, use the UTL device to call a pre-built DEF device, and use the DEF device to call a pre-built SDF device; Use the UTL device to call a pre-built NETLIST device; Use the NETLIST device to obtain a NETLIST file according to the simulation object, and obtain netlist data from the NETLIST file; Use the SDF device to obtain an SDF file according to the simulation object, and obtain delay data from the SDF file; Use the UTL device to summarize the netlist data and delay data, and use the post-simulation verification environment to backannotate the delay data to the netlist data to obtain a timing-annotated netlist.

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