Layout processing method and device, electronic equipment and storage medium
By calibrating parameters and mapping layers based on functional equivalence and DRC rules, the method addresses inefficiencies in cross-platform circuit design data migration, enhancing accuracy and reducing manual adjustments.
Patent Information
- Application Number
- CN202510369757.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-26
- Publication Date
- 2025-07-15
AI Technical Summary
The migration of layout design data across process platforms takes a lot of time and manpower, and the migration efficiency is inefficient. The existing technology direct layer mapping leads to many DRC violations, which requires a lot of manual adjustments.
By obtaining the source layout, the target parameters are calibrated to match the target process design rules, and layer mapping is performed based on the principle of functional consistency, and finally DRC rules are checked to ensure that the target layout complies with the target process rules.
Improve the accuracy of data after layout migration, reduce DRC violations, save designers' adjustment time, and improve cross-process migration efficiency.
Smart Images
Figure CN120317218A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to a layout processing method, device, electronic device, and storage medium. Background Art
[0002] Currently, limited by production capacity or the need for technological iteration and update, chip design companies often design products based on the process platforms of multiple chip manufacturers at the same time. Since the design rules corresponding to different chip manufacturing process platforms are different, the design scheme across process platforms, such as the migration of layout design data, often takes a lot of time and effort.
[0003] The prior art usually adopts a direct layer mapping method to simply correspond the layers of process A with the same-name or approximate layers of process B. However, due to significant differences in Design Rule Check (DRC) among different chip manufacturers, there are a large number of DRC violation problems in the migrated layout. Engineers need to spend a lot of time manually adjusting, and the workload is close to re-design, resulting in low efficiency. Summary of the Invention
[0004] In view of this, this application is committed to providing a layout processing method, device, electronic device, and storage medium to solve the problem that the migration of layout between different process platforms in the prior art consumes a lot of manpower and material resources and has low migration efficiency.
[0005] In a first aspect, this application provides a layout processing method, including:
[0006] Obtain the source layout of the target module designed based on the source process;
[0007] Perform target parameter calibration on the source layout to make the source layout match the design rules of the target process;
[0008] Map each source layer of the source layout to the target layer with the same function in the target process;
[0009] Calibrate each of the target layers according to the DRC rules of the target process to obtain a target layout that meets the design rules of the target process.
[0010] In an optional implementation manner, the obtaining the source layout of the target module designed based on the source process includes:
[0011] Obtain the design layout of the integrated circuit designed based on the source process;
[0012] Split the design layout of the integrated circuit into multiple source layouts according to the layout area, and each source layout corresponds to a sub-module of the integrated circuit;
[0013] Respectively take each of the sub - modules as the target sub - module to obtain the source layout of the target sub - module.
[0014] In an optional implementation manner, the splitting of the design layout of the integrated circuit into multiple source layouts according to layout regions includes:
[0015] Call the Yank function of the Virtuoso software, and based on the Yank function, split the design layout of the integrated circuit into multiple source layouts according to layout regions.
[0016] In an optional implementation manner, the target parameters include grid resolution;
[0017] The calibration of the target parameters for the source layout includes:
[0018] Align the coordinates of the source layout based on the grid resolution of the target process, and correct the graphic offset caused by the difference in grid resolution between the source process and the target process.
[0019] In an optional implementation manner, mapping each source layer of the source layout to a target layer with the same function in the target process includes:
[0020] Based on the principle of consistent layer functions, match the layers of the source process with the layers of the target process one by one;
[0021] Preferably map the core function layers in the source layout to the matching target layers in the target process.
[0022] In an optional implementation manner, the layout processing method provided in the first aspect of the present application further includes: creating a target via layer in the target layout according to the design rules of the target process, where the target via layer is at the same level as the via layer in the source layout.
[0023] In an optional implementation manner, the layout processing method provided in the first aspect of the present application further includes: performing DRC detection and layout - to - circuit Figure 1 consistency LVS detection on the target layout.
[0024] In a second aspect, the present application provides a layout processing device, including:
[0025] An acquisition unit, configured to acquire the source layout of a target module designed based on a source process;
[0026] A first calibration unit, configured to perform target parameter calibration on the source layout to make the source layout match the design rules of the target process;
[0027] A mapping unit, configured to map each source layer of the source layout to a target layer with the same function in the target process;
[0028] A second calibration unit for calibrating each of the target layers according to the DRC rules of the target process to obtain a target layout that meets the target process design rules.
[0029] In a third aspect, the present application provides an electronic device, including: a memory, a processor, and a computer program stored on the memory and executed by the processor. When the processor executes the computer program, the steps of the layout processing method according to any one of the first aspects of the present application are implemented.
[0030] In a fourth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the layout processing method according to any one of the first aspects of the present application are implemented.
[0031] Based on the above content, through the layout processing method provided by the present application, after obtaining the source layout of the target module based on the source process design, the target parameters of the source layout are calibrated to make the source layout match the design rules of the target process. Further, each source layer of the source layout is respectively mapped to the target layer with the same function in the target process, and each target layer is calibrated according to the DRC rules of the target process to obtain a target layout that meets the target process design rules. It can be seen from this that the layout processing method provided by the present application calibrates the target parameters of the source layout when performing layout data migration across process platforms to make the source layout match the design rules of the target process. Further, layer mapping is also performed based on the principle of the same function, reducing the possibility of data errors caused by layer functions, and DRC rule verification is also performed after mapping. Compared with the existing layout migration method that directly performs layer mapping, the accuracy rate of the data after layout migration can be greatly improved, and there will be no large number of DRC violation problems in the migrated target layout, saving the time for designers to adjust again and improving the efficiency of layout cross-process migration. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0033] Figure 1 is a flowchart of a layout processing method provided by the present application.
[0034] Figure 2 is a schematic diagram of the effect of splitting the design layout of an integrated circuit into source layouts of multiple sub-modules.
[0035] Figure 3 It is a flowchart of another layout processing method provided by this application.
[0036] Figure 4 It is a schematic diagram showing the effect of merging the target layouts of sub-modules under the target process into an integrated circuit layout.
[0037] Figure 5 It is a structural block diagram of a layout processing device provided by this application.
[0038] Figure 6 It is a structural block diagram of another layout processing device provided by this application.
[0039] Figure 7 It is a structural block diagram of an electronic device provided by this application. Specific embodiments
[0040] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this application.
[0041] As mentioned above, in actual applications, chip design companies are often limited by production capacity or the need for technological iteration and update, and often design products based on the process platforms of multiple chip manufacturers at the same time. Since the design rules corresponding to the process platforms of different chip manufacturers are different, the design schemes across process platforms, such as the migration of layout design data, often require a lot of time and effort.
[0042] The prior art usually adopts the direct layer mapping (Layer Map) method to simply correspond the layers of process A with the same-name or approximate layers of process B. However, due to significant differences in DRC among different chip manufacturers, such as grid resolution, fin pitch, and via structure, etc., there are a large number of DRC violation problems in the migrated layout, and engineers need to spend a lot of time manually adjusting, and the workload is close to re-design, with low efficiency.
[0043] To solve the above problems, the present application provides a layout processing method, which divides the layout migration process into different stages, and performs operations such as parameter calibration of the target module, layer correspondence mapping, and DRC calibration based on the target process. By calibrating the target parameters of the source layout, the source layout is made to match the design rules of the target process. Layer mapping is performed based on the principle of the same function, reducing the possibility of data errors caused by layer functions. And after mapping, DRC rule verification is also performed. Compared with the existing layout migration method that directly performs layer mapping, the correct rate of the data after layout migration can be greatly improved, and the efficiency of cross-process layout migration can be improved.
[0044] The layout processing method provided by the present application is applied to an electronic device, which can be a notebook computer, a personal computer (PC), a tablet computer. Of course, it can also be other electronic devices that can run the application program corresponding to the physical design method provided by the present application, which will not be listed one by one here. Of course, in some cases, it can also be applied to a server on the network side.
[0045] Furthermore, in the related art, Virtuoso is a currently widely used design software, mainly used for design operations such as analog / mixed-signal design, layout design, and verification of integrated circuits, and occupies a core position especially in the design of analog circuits, radio frequency circuits, and FINFET (Fin Field-Effect Transistor) processes. More importantly, Virtuoso also provides an open secondary development interface and a very complete development language library (skill). The skill language provides rich interactive functions, and designers can develop various functions or perform specific processing on the integrated circuit layout according to their own needs. Based on this, as an optional implementation manner, the layout processing method provided by the present application can be implemented through the skill language of Virtuoso, that is, a script program corresponding to the layout processing method provided by the present application is developed through the skill language. The layout of the source process to be processed is opened in the image interface of Virtuoso, and according to the processing flow provided by the present application, the corresponding script program is used to quickly process the integrated circuit layout, convert the layout of the source process into the layout of the target process, thereby completing the layout migration work across process platforms and improving the layout processing efficiency.
[0046] Based on the above content, see Figure 1 As shown, the layout processing method provided by the present application includes the following steps.
[0047] S100. Obtain the source layout of the target module designed based on the source process.
[0048] The layout is the physical design blueprint of a chip, which precisely describes the shapes, positions, and connection relationships of components such as transistors, interconnects, and vias through geometric shapes (such as polygons, paths). The layout designed under different process platforms needs to meet the design rules of the corresponding process. When cross-process platform migration of the layout is required, it is necessary to ensure that the layout can meet the design rules of the process after migration. The layout processing method provided in this application is mainly used to achieve the migration of integrated circuit layouts between different process platforms. Based on this, the process currently corresponding to the integrated circuit layout in this application is defined as the source process. Correspondingly, the layout designed according to the source process is defined as the source layout, the process after layout migration is defined as the target process, and the layout that meets the design rules of the target process, that is, the migrated layout, is defined as the target layout.
[0049] Based on the hierarchical design concept of integrated circuits, according to different specific implementation functions, an integrated circuit can be divided into different sub-modules. The independence between sub-modules is not only reflected in the differences in specific implemented functions, but also has obvious isolation in the layout of the layout. Based on this, the design layout of an integrated circuit can be divided into the layouts of multiple sub-modules. The target sub-module mentioned in this application can be any one of the multiple sub-modules of the integrated circuit.
[0050] Based on the above content, as an optional implementation manner, it is possible to first obtain the design layout of an integrated circuit designed according to the source process. Further, based on the independence of different sub-modules in the layout, the design layout of the integrated circuit is split into multiple source layouts according to the layout areas of each sub-module. Each source layout corresponds to a sub-module of the integrated circuit. During subsequent execution, each sub-module is used as the target sub-module, and the layout cross-platform migration is performed respectively according to the layout processing method provided in this application, so as to finally complete the overall migration of the design layout of the integrated circuit.
[0051] Combined with Figure 2 As shown, the integrated circuit includes sub-module A, sub-module B, and sub-module C. After splitting by sub-module, three corresponding independent sub-modules can be obtained, and each sub-module corresponds to a source layout.
[0052] As mentioned above, the layout processing method provided in this application can be implemented based on Virtuoso. Based on this, as an optional implementation manner, the Yank function of the Virtuoso software can be called to split the design layout of the integrated circuit into multiple source layouts according to the layout area. As for the specific use process of the Yank function, it can be implemented with reference to related technologies and will not be elaborated here.
[0053] S110. Calibrate the target parameters of the source layout to make the source layout match the design rules of the target process.
[0054] In practical applications, the design rules of different processes are not the same, and there must be certain differences in the corresponding design parameters. Therefore, before performing cross-platform migration of the layout, it is necessary to first calibrate the source layout with target parameters according to the design rules of the target process to make the source layout match the design rules of the target process. It can be understood that there are many design parameters corresponding to any process. There may be some design parameters with the same meaning, function, and specific values between different processes. Such parameters can be used directly without calibration. There must also be some design parameters with different specific limitations. Such parameters must be calibrated to meet the design rules of the target process.
[0055] The target parameters mentioned in this application at least include grid resolution, gate pitch, and fin pitch. Of course, it can also include other relevant parameters that must be calibrated during the cross-platform migration of the layout. Details are not described one by one here. Beyond the core idea of this application, it also belongs to the scope protected by this application.
[0056] Taking grid resolution as an example, when calibrating the grid resolution, first align the coordinates of the source layout based on the grid resolution of the target process, and at the same time correct the pattern deviation caused by the difference in grid resolution between the source process and the target process. After calibrating the grid resolution, it can be ensured that the coordinates of each relevant element in the source layout match the coordinate system of the target process. For the calibration process of other target parameters, it can be implemented with reference to related technologies. Details are not described one by one here.
[0057] Furthermore, when implementing this method based on Virtuoso, during the process of calibrating the target parameters, the Virtuoso software will monitor whether the above-mentioned target parameter calibration process is successfully completed. If the splitting of the sub-module is unreasonable, it will cause the Virtuoso software to execute an interruption. In the case of software execution interruption, an error report will be displayed on the user interface program of the program to remind the designer that the integrated circuit needs to be split into sub-modules again to overcome the problem of unreasonable sub-module splitting. Since the layout design requires that different types of logic devices cannot be combined together and a certain isolation space needs to be reserved, when checking the splitting of the sub-module, the key can be to check whether there are different types of logic devices or logic devices of the same type but different sizes in the split sub-modules.
[0058] S120. Map each source layer of the source layout to the target layer with the same function in the target process.
[0059] A layer is a physical or logical level defined in the integrated circuit manufacturing process, corresponding to different materials and process steps in chip manufacturing, such as polysilicon layer, metal layer, doped layer, insulating layer, etc. The layout is composed of multiple layers of layers stacked on top of each other. Each layer of the layer carries a structure with a specific function. For example, in the metal layer, the metal layer pattern in the layout determines the direction of the metal wires. During manufacturing, the actual metal connections can be formed by copper plating or etching according to the metal layer pattern. For the specific functions of other functional layers, reference can be made to relevant technologies and will not be elaborated here.
[0060] In practical applications, since the manufacturing principles and processes of integrated circuits are generally the same, there are layers with the same functions between different processes. For example, both Process A and Process B include a metal layer and an insulating layer. Therefore, when migrating the layout across platforms, it is first necessary to ensure the consistency of the layer functions. Based on this, as a preferred implementation method, based on the principle of consistent layer functions, the layers of the source process can be matched one by one with the layers of the target process to determine the target layers in the target process that correspond to the same functions as the source process. Further, each original layer of the source layout is mapped to the corresponding target layer in the target process. It can be understood that since the number of layers included in the layout is numerous and the number of layers between different processes is not necessarily the same, when performing layer mapping, the core functional layers in the source layout are preferably mapped to the matching target layers in the target process. As for the source process layers that do not have corresponding target layers, they can be regenerated based on the core functional layers obtained by mapping under the target process. The specific generation process can be implemented with reference to relevant technologies and will not be elaborated here.
[0061] In an alternative implementation method, during the layer migration process, the source layout of the target sub-module can be opened through the image interface of the Virtuoso software to determine whether the migration work of all layers in the source layout has been completed in a one-by-one comparison manner. It can be understood that even for a determined integrated circuit, the layouts of different processes for implementing the integrated circuit may correspond to different numbers of layers. This difference is determined by the process rules and is also affected by the design concept. Therefore, when performing cross-platform layer migration, the above-mentioned determination of whether the migration work of all layers in the source layout has been completed mainly refers to the completion of the migration of all layers necessary to implement the logical functions of the integrated circuit, rather than requiring that each layer of the source process be physically mapped to the layer with the same function in the target process. That is to say, for the target sub-module, the source layout and the target layout may correspond to different numbers of layers.
[0062] S130. Calibrate each target layer according to the DRC rules of the target process to obtain a target layout that meets the design rules of the target process.
[0063] After obtaining the target layer, in order to ensure the correctness of the data of each target layer, it is necessary to calibrate each target layer according to the DRC rules of the target process. After all target layers pass the calibration, the target layout of the target sub-module that meets the design rules of the target process can be obtained.
[0064] In an alternative embodiment, the DRC rule file of the target process can be loaded through the DRC calibration software Calibre software, and the Calibre software is used for automatic inspection.
[0065] In summary, the layout processing method provided by this application calibrates the target parameters of the source layout when migrating layout data across process platforms, so that the source layout matches the design rules of the target process. Further, layer mapping is performed based on the principle of the same function, reducing the possibility of data errors caused by layer functions, and DRC rule verification is also performed after mapping. Compared with the existing layout migration method that directly performs layer mapping, the correct rate of the data after layout migration can be greatly improved, and there will be no large number of DRC violation problems in the migrated target layout, saving the time for designers to adjust again and improving the efficiency of layout cross-process migration.
[0066] It can be understood that for other sub-modules obtained after splitting, the layout migration between different process platforms can be carried out according to the above process, which will not be elaborated here.
[0067] Further, this application also provides another layout processing method. Refer to Figure 3 As shown, based on the foregoing embodiment, the layout processing method provided in this embodiment further includes the following steps.
[0068] S140. Create a target via layer in the target layout according to the design rules of the target process.
[0069] In the related art, different metal layers of an integrated circuit can be connected through vias. Figure 1 In the shown embodiment, the cross-process platform migration of each target layer has been completed. However, the connection relationship has not been established between the target layers. Based on this, a target via layer can be further created in the target layout according to the design rules of the target process, that is, the via layer is reconstructed according to the via size, shape and density rules of the target process, so as to connect the target layers with a connection relationship through the target process layer.
[0070] It can be understood that in order to ensure that the logical function of the integrated circuit is not affected before and after migration, the position of the target via layer should be set with reference to the layer where the via layer is located in the source layout to ensure that the target via layer is at the same layer as the via layer in the source layout. As for the specific creation process of the target via layer, it can be implemented with reference to the related art and will not be elaborated here.
[0071] So far, all the migration work of the source layout of the target sub-module is completed, and the target layout of the target sub-module under the target process is obtained.
[0072] S150. Perform DRC detection and LVS detection on the target layout.
[0073] To ensure the accuracy of the target layout, DRC detection and LVS (Layout Versus Schematics) detection can be further performed on the target layout. Figure 1 In an optional implementation manner, the corresponding detection process can also be completed based on the aforementioned Calibre software, which will not be elaborated here.
[0074] Furthermore, as shown in Figure 4 , after the layout migration work of all sub-modules is completed, the sub-modules can be further merged at the top layer, and finally the design layout of the integrated circuit under the target process is obtained.
[0075] In summary, based on the embodiment shown in Figure 1 , the layout processing method provided in this embodiment creates a target via layer in the target layout according to the layer level where the via layer is located in the source layout, realizes the connection between relevant layers in each target layer, and further performs DRC and LVS detections on the obtained target layout to ensure that the obtained target layout meets the design rules of the target process, realizes the reliable and efficient migration of the layout across process platforms, helps to shorten the design cycle of the integrated circuit, and improves the design efficiency.
[0076] Next, the layout processing device provided by the present invention will be introduced. The layout processing device provided by the present invention belongs to the same inventive concept as the layout processing method provided in the embodiments of the present application, can execute the layout processing method provided in any embodiment of the present application, and has corresponding functional modules and beneficial effects for executing the layout processing method. Technical details not described in detail in this embodiment can be referred to the layout processing method provided in the embodiments of the present application, which will not be elaborated here.
[0077] Refer to Figure 5 , the layout processing device provided by the present application includes the following constituent units:
[0078] An acquisition unit 10, configured to acquire the source layout of a target module designed based on a source process;
[0079] A first calibration unit 20, configured to perform target parameter calibration on the source layout to make the source layout match the design rules of the target process;
[0080] A mapping unit 30, configured to map each source layer of the source layout to a target layer with the same function in the target process;
[0081] A second calibration unit 40, configured to calibrate each of the target layers according to the DRC rules of the target process, so as to obtain a target layout that meets the target process design rules.
[0082] Furthermore, the present application also provides another layout processing device. Refer to Figure 6 as shown, on the basis of the embodiment shown in Figure 5 The layout processing device provided in this embodiment further includes:
[0083] A creation unit 50, configured to create a target via layer in the target layout according to the design rules of the target process, where the target via layer is at the same level as the via layer in the source layout;
[0084] A detection unit 60, configured to perform DRC detection on the target layout and layout and circuit Figure 1 consistency LVS detection.
[0085] Next, referring to Figure 7 The electronic device provided in the embodiment of the present invention will be described. The electronic device provided in this embodiment may include: at least one processor 100, at least one communication interface 200, at least one memory 300, and at least one communication bus 400;
[0086] In the embodiment of the present invention, the number of the processor 100, the communication interface 200, the memory 300, and the communication bus 400 is at least one, and the processor 100, the communication interface 200, and the memory 300 complete mutual communication through the communication bus 400; obviously, Figure 7 The communication connection schematic diagram of the processor 100, the communication interface 200, the memory 300, and the communication bus 400 shown is only optional;
[0087] Optionally, the communication interface 200 may be an interface of a communication module, such as an interface of a GSM module; the processor 100 may be a central processing unit CPU, or a specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention. The memory 300 may include a high-speed RAM memory, and may also include a non-volatile memory, such as at least one disk memory.
[0088] Wherein, the processor 100 is specifically configured to execute an application program in the memory to implement the steps of the above-mentioned layout processing method.
[0089] In some embodiments, the present embodiment further provides a computer-readable storage medium, such as a floppy disk, an optical disc, a hard disk, a flash memory, a USB flash drive, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, etc. One or more instructions for implementing the above steps are stored in the computer-readable storage medium. When the one or more instructions are executed by one or more processors, the processors execute the layout processing method described above. For the relevant specific implementation, please refer to the foregoing description, and details are not elaborated herein.
[0090] In addition to the above methods and devices, an embodiment of the present application may also be a computer program product, which includes computer program instructions. When the computer program instructions are run by a processor, the processor executes the steps in the layout processing method according to various embodiments of the present application described in the above content of this specification.
[0091] The computer program product can be written in any combination of one or more programming languages to write program code for performing the operations of the embodiments of the present application. The programming languages include object-oriented programming languages, such as Java, C++, etc., and also include conventional procedural programming languages, such as the "C" language or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, executed as an independent software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.
[0092] Those skilled in the art can understand that the content disclosed in the present disclosure can have various variations and improvements. For example, the various devices or components described above can be implemented by hardware, or by software, firmware, or some or all of the combinations of the three.
[0093] In addition, although the present disclosure makes various references to certain units in the system according to the embodiments of the present disclosure, however, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.
[0094] Flowcharts are used in the present disclosure to illustrate the steps of the methods according to the embodiments of the present disclosure. It should be understood that the previous or subsequent steps do not necessarily need to be carried out precisely in sequence. On the contrary, they can be carried out in reverse order or various steps can be processed simultaneously. At the same time, other operations can also be added to these processes.
[0095] Those of ordinary skill in the art will understand that all or part of the steps in the above methods can be completed by instructing relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, etc. Optionally, all or part of the steps of the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in the form of hardware or in the form of a software functional module. The present disclosure is not limited to any specific combination of hardware and software.
[0096] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.
[0097] The above is an illustration of the present disclosure and should not be regarded as a limitation thereof. Although several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the above is an illustration of the present disclosure and should not be regarded as limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.
Claims
1. A layout processing method, characterized in that, Including: Obtain the source layout of the target module based on the source process design; Perform target parameter calibration on the source layout to make the source layout match the design rules of the target process; Map each source layer of the source layout to the target layer with the same function in the target process respectively; Calibrate each of the target layers according to the DRC rules of the target process to obtain a target layout that meets the design rules of the target process.
2. The method according to claim 1, characterized in that, The obtaining of the source layout of the target module based on the source process design includes: Obtain the design layout of the integrated circuit based on the source process design; Split the design layout of the integrated circuit into multiple source layouts according to the layout area, and each source layout corresponds to a sub-module of the integrated circuit; Respectively take each of the sub-modules as the target sub-module to obtain the source layout of the target sub-module.
3. The method according to claim 2, wherein The splitting of the design layout of the integrated circuit into multiple source layouts according to the layout area includes: Call the Yank function of the Virtuoso software, and split the design layout of the integrated circuit into multiple source layouts according to the layout area based on the Yank function.
4. The method according to claim 1, wherein The target parameters include grid resolution; The performing of target parameter calibration on the source layout includes: Align the coordinates of the source layout based on the grid resolution of the target process, and correct the graphic offset caused by the difference in grid resolution between the source process and the target process.
5. The method according to claim 1, characterized in that, The mapping of each source layer of the source layout to the target layer with the same function in the target process respectively includes: Based on the principle of consistent layer functions, match the layers of the source process with the layers of the target process one by one; Preferably map the core function layers in the source layout to the matching target layers in the target process.
6. The method according to claim 1, wherein Also including: Create a target via layer in the target layout according to the design rules of the target process, and the target via layer is at the same level as the via layer in the source layout.
7. The method according to claim 6, wherein Also including: Perform DRC detection and layout versus schematic (LVS) detection on the target layout.
8. A layout processing device, characterized in that, Including: An obtaining unit for obtaining the source layout of the target module based on the source process design; A first calibration unit for performing target parameter calibration on the source layout to make the source layout match the design rules of the target process; A mapping unit for mapping each source layer of the source layout to the target layer with the same function in the target process respectively; A second calibration unit for calibrating each of the target layers according to the DRC rules of the target process to obtain a target layout that meets the design rules of the target process.
9. An electronic device, comprising: A memory, a processor, and a computer program stored on the memory and executed by the processor, wherein when the processor executes the computer program, the steps of the layout processing method according to any one of claims 1 to 7 are implemented.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the steps of the layout processing method according to any one of claims 1 to 7 are implemented.