Semiconductor manufacturing apparatus, semiconductor device manufacturing method, and pickup method

Abstract

Provided are a technique relating to a semiconductor manufacturing apparatus, a semiconductor device manufacturing method, and a pickup method that can reduce the occurrence of pickup errors. The semiconductor manufacturing apparatus includes: a wafer holding table that holds a wafer ring having a dicing tape attached to a wafer divided into bare chips; a peeling unit which assists the pickup of the bare chip from the dicing tape; and a control unit configured to set a peeling condition, which is a condition for operation of the peeling unit, on the basis of peripheral information, which is configuration information of the bare chip in a peripheral region of the bare chip to be picked up.

Description

Technical Field

[0001] The present invention relates to a semiconductor manufacturing apparatus, and can be applied to, for example, a chip mounter having a peeling unit. Background Art

[0002] As one process of a semiconductor device manufacturing process, there is a peeling process of peeling a bare chip separated from a wafer from a dicing tape. In the peeling process, for example, a bare chip is lifted from the back surface of the dicing tape by a lifting unit, peeled one by one from the dicing tape held by the wafer supply unit, and the bare chip is picked up using a suction nozzle such as a collet provided in a pick-up head or a mounting head.

[0003] The dicing tape held by the wafer ring is stretched to increase the interval between the bare chips, thereby improving the pick-up property of the bare chips (Patent Document 1).

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2013-172122 Summary of the Invention

[0007] When picking up a bare chip, the tension of the dicing tape is different between the part where the bare chip is picked up and the part where the bare chip remains. Therefore, depending on the peeling conditions of the peeling unit that picks up the bare chip from the dicing tape, such as an auxiliary lifting unit, pick-up failures sometimes occur.

[0008] An object of the present invention is to provide a technique capable of reducing the occurrence of pick-up failures. Other objects and new features will become apparent from the description of this specification and the accompanying drawings.

[0009] If the outline of a representative aspect of the present invention is briefly described, it is as follows.

[0010] That is, a semiconductor manufacturing apparatus includes: a wafer holding table that holds a wafer ring which holds a dicing tape pasted to a wafer divided into bare chips; a peeling unit that assists in picking up the bare chips from the dicing tape; and a control unit that is configured to set peeling conditions that are conditions for the operation of the peeling unit based on surrounding information that is configuration information of the bare chips in the surrounding area of the bare chip to be picked up.

[0011] Advantages of the Invention

[0012] According to the present invention, the occurrence of pick-up failures can be reduced. Brief Description of the Drawings

[0013] Figure 1 It is a schematic top view showing a structural example of a chip mounter in an embodiment.

[0014] Figure 2 is a diagram showing a schematic structure when viewed from the direction of arrow A in Figure 1 .

[0015] Figure 3 is a schematic cross-sectional view showing the main part of the wafer supply unit shown in Figure 1 .

[0016] Figure 4 is a block diagram showing the schematic structure of the control system of the chip mounter shown in Figure 1 .

[0017] Figure 5 is a flowchart showing a method of manufacturing a semiconductor device using the chip mounter shown in Figure 1 .

[0018] Figure 6 is a Figure 2 top view of the peeling unit shown in

[0019] Figure 7 is a diagram schematically showing Figure 2 a cross-section of an important part of the peeling unit shown in

[0020] Figure 8 is a diagram explaining Figure 6 the lifting sequence in an operation example of the peeling unit shown in

[0021] Figure 9 is a diagram showing Figure 8 an example of the block operation timing of the sequence of

[0022] Figure 10 is a diagram showing Figure 9 an example of a parameter table corresponding to the block operation timing of

[0023] Figure 11 is a diagram showing an example of the wafer mapping data in the embodiment

[0024] Figure 12 is a diagram showing the wafer mapping data after picking up the first-classified bare chips from the wafer corresponding to the wafer mapping data of Figure 11

[0025] Figure 13 is a diagram showing the picking-up process in this embodiment

[0026] Figure 14 is a diagram explaining the peripheral information

[0027] Figure 15 is a diagram explaining Figure 2 the relationship between the field of view of the wafer identification camera shown in

[0028] ​Figure 16 This is a diagram showing an example of a diagram case of peripheral information.

[0029] Explanation of Reference Numerals

[0030] 1 ··· Chip mounter (semiconductor manufacturing apparatus)

[0031] 12 ··· Wafer holding stage

[0032] 13 ··· Stripping unit

[0033] 80 ··· Control unit Detailed Description of the Embodiment

[0034] Hereinafter, the embodiment will be described with reference to the drawings. However, in the following description, the same reference numerals may be given to the same structural elements and repeated descriptions may be omitted. In addition, for the sake of clarity, there are cases where the drawings schematically show the width, thickness, shape, etc. of each part as compared with the actual state. Also, among the multiple drawings, the dimensional relationships between the elements, the ratios of the elements, etc. are not necessarily consistent.

[0035] Use Figures 1 to 3 To describe the structure of a chip mounter as an embodiment of a semiconductor manufacturing apparatus. Figure 1 This is a schematic top view showing a structural example of the chip mounter in the embodiment. Figure 2 This is to explain Figure 1 The schematic structure when viewed from the direction of arrow A in Figure 3 This is a schematic cross-sectional view showing the main part of the wafer supply unit shown in Figure 1

[0036] The chip mounter 1 generally includes a wafer supply unit 10, a pick-up unit 20, an intermediate stage unit 30, a mounting unit 40, a transfer unit 50, a substrate supply unit 60, a substrate discharge unit 70, and a control unit (control device) 80. The Y2 - Y1 direction is the front - rear direction of the chip mounter 1, the X2 - X1 direction is the left - right direction, and the Z1 - Z2 direction is the up - down direction. The wafer supply unit 10 is arranged on the front side of the chip mounter 1, and the mounting unit 40 is arranged on the rear side.

[0037] The wafer supply unit 10 includes a wafer cassette elevator 11, a wafer holding stage 12, a stripping unit 13, and a wafer identification camera 14.

[0038] The wafer cassette elevator 11 moves a wafer cassette (not shown) storing a plurality of wafer rings WR up and down to the wafer transfer height. A wafer alignment groove (not shown) aligns the wafer rings WR supplied from the wafer cassette elevator 11. A wafer extractor (not shown) takes out the wafer ring WR from the wafer cassette and supplies it to the wafer holding stage 12, or takes it out from the wafer holding stage 12 and stores it in the wafer cassette.

[0039] The wafer holding stage 12 has an expansion ring 121 that holds the wafer ring WR, and a support ring 122 that is held by the wafer ring WR and horizontally positions the dicing tape DT. The peeling unit 13 is disposed inside the support ring 122.

[0040] The wafer W is bonded (attached) to the dicing tape DT, and the wafer W is divided into a plurality of bare chips D. A film-like bonding material DF called a chip adhesive film (DAF) is attached between the wafer W and the dicing tape DT. The bonding material DF is cured by heating.

[0041] The wafer holding stage 12 is moved in the X1-X2 direction and the Y1-Y2 direction by a drive unit (not shown), and the picked bare chip D is moved to the position of the peeling unit 13. In addition, the wafer holding stage 12 rotates the wafer ring WR in the XY plane by a drive unit (not shown). The peeling unit 13 is moved in the vertical direction by a drive unit (not shown). The peeling unit 13 peels the bare chip D from the dicing tape DT. The wafer holding stage 12 and the peeling unit 13 constitute a picking device (semiconductor manufacturing device). The picking unit 20 may be included in the picking device.

[0042] When the bare chip D is lifted, the wafer holding stage 12 lowers the expansion ring 121 that holds the wafer ring WR. At this time, since the support ring 122 does not lower, the dicing tape DT held by the wafer ring WR is stretched and the interval between the bare chips D is expanded, preventing interference and contact between the bare chips D, and creating conditions for easy separation and lifting of each bare chip. The expansion ring 121 and the support ring 122 together are called an expander. The peeling unit 13 performs the peeling of the bare chip D by lifting the bare chip D from below, improving the pick-up property of the bare chip D by the collet.

[0043] The wafer identification camera 14 identifies the pick-up position of the bare chip D picked from the wafer W and performs a surface inspection of the bare chip D.

[0044] The picking unit 20 has a picking head 21 and a Y drive unit 23. A collet 22 is provided on the picking head 21, and the collet 22 adsorbs and holds the peeled bare chip D at the front end. The picking head 21 picks up the bare chip D from the wafer supply unit 10 and places it on the intermediate stage 31. The Y drive unit 23 moves the picking head 21 in the Y1-Y2 direction. The picking unit 20 has drive units (not shown) for lifting, rotating, and moving the picking head 21 in the X direction.

[0045] The intermediate stage portion 30 has an intermediate stage 31 for placing the bare chip D thereon, and a stage recognition camera 34 for recognizing the bare chip D on the intermediate stage 31. The intermediate stage 31 has suction holes for sucking the placed bare chip D. The placed bare chip D is temporarily held on the intermediate stage 31. The intermediate stage 31 is a placement stage for placing the bare chip D, and is also a pick-up stage for picking up the bare chip D.

[0046] The mounting portion 40 has a mounting head 41, a Y drive portion 43, a substrate recognition camera 44, and a mounting stage 46. A collet 42 is provided on the mounting head 41, and the collet 42 sucks and holds the bare chip D at the front end. The Y drive portion 43 moves the mounting head 41 in the Y1 - Y2 direction. The substrate recognition camera 44 photographs the position recognition marks (not shown) of the substrate S to recognize the mounting positions. Here, a plurality of product areas (hereinafter referred to as package areas P) that will eventually become one package are formed on the substrate S. The position recognition marks are provided for each package area P. When placing the bare chip D on the substrate S, the mounting stage 46 rises and supports the substrate S from below. The mounting stage 46 has suction ports (not shown) for vacuum-sucking the substrate S and can fix the substrate S. The mounting stage 46 has a heating portion (not shown) for heating the substrate S. The mounting portion 40 has drive portions (not shown) for lifting, rotating, and moving the mounting head 41 in the X direction.

[0047] According to such a structure, the mounting head 41 corrects the pick-up position and posture based on the shooting data of the stage recognition camera 34, and picks up the bare chip D from the intermediate stage 31. And the mounting head 41 mounts on the package area P of the substrate S based on the shooting data of the substrate recognition camera 44, or mounts in a form of stacking on the bare chip that has already been mounted on the package area P of the substrate S.

[0048] The conveyance portion 50 has a conveyance claw 51 for gripping and conveying the substrate S, and a conveyance path 52 for moving the substrate S. The substrate S moves in the X direction by driving a nut (not shown) of the conveyance claw 51 provided in the conveyance path 52 by a ball screw (not shown) provided along the conveyance path 52. According to such a structure, the substrate S moves from the substrate supply portion 60 along the conveyance path 52 to the mounting position, and after mounting, moves to the substrate discharge portion 70, and delivers the substrate S to the substrate discharge portion 70.

[0049] The substrate supply portion 60 takes out the substrate S stored in the conveyance jig and carried in from the conveyance jig and supplies it to the conveyance portion 50. The substrate discharge portion 70 stores the substrate S conveyed by the conveyance portion 50 into the conveyance jig.

[0050] Next, Figure 4 the control portion 80 will be described. Figure 4 represents Figure 1Block diagram of the schematic structure of the control system of the chip mounter shown.

[0051] The control system 8 includes a control unit (control device) 80, a drive unit 86, a signal unit 87, an optical system 88, etc. The control unit 80 generally has a control and arithmetic device 81 mainly composed of a CPU (Central Processing Unit), a storage device 82, an input / output device 83, a bus 84, and a power supply unit 85. The storage device 82 has a main storage device 82a and an auxiliary storage device 82b. The main storage device 82a is composed of a RAM (Random Access Memory) that stores processing programs and the like. The auxiliary storage device 82b is composed of an HDD (Hard Disk Drive) or an SSD (SolidState Drive) that stores control data and image data required for control, etc.

[0052] The input / output device 83 has: a monitor 83a that displays device status and information, etc., a touch panel 83b that inputs the operator's instructions, a mouse 83c that operates the monitor 83a, and an image input device 83d that takes in image data from the optical system 88. The input / output device 83 further has a motor control device 83e and an I / O signal control device 83f. The motor control device 83e controls the XY table (not shown) of the wafer supply unit 10, the ZY drive shaft of the mounter head table, the drive unit of the peeling unit 13, etc. The I / O signal control device 83f takes in signals from the signal unit 87 that includes various sensors and switches or knobs that control the brightness of the lighting device, etc., or performs control. The optical system 88 includes a wafer identification camera 14, a stage identification camera 34, and a substrate identification camera 44. The control and arithmetic device 81 takes in necessary data via the bus 84, performs arithmetic operations, controls the pick-up head 21, etc., and sends information to the monitor 83a, etc.

[0053] Use Figure 5 A part of the manufacturing process of semiconductor devices (manufacturing method of semiconductor devices) using the chip mounter 1 will be described. Figure 5 It shows the use of Figure 1 Flowchart of the manufacturing method of semiconductor devices using the chip mounter shown. In the following description, the operations of each part constituting the chip mounter 1 are controlled by the control unit 80.

[0054] (Wafer loading process: Process S1)

[0055] A wafer cassette (not shown) containing a wafer ring WR is loaded into the wafer cassette elevator 11. The wafer supply unit 10 takes out the wafer ring WR from the wafer cassette filled with the wafer ring WR and transfers it into the wafer holding stage 12. In addition, the wafer W is previously inspected by an inspection device such as a probe for each bare chip, and wafer (classification) map data indicating the grades or non-conformities of the bare chips with different electrical characteristics is generated. This wafer map data is stored in the storage device of the control unit 80.

[0056] (Substrate loading process: Process S2)

[0057] A transfer jig holding the substrate S is loaded into the substrate supply unit 60. The substrate supply unit 60 takes out the substrate S from the transfer jig. The taken-out substrate S is transferred into the mounting unit 40 via the transfer unit 50.

[0058] (Pick-up process: Process S3)

[0059] After Process S1, the wafer holding stage 12 is moved so that the desired bare chip D can be picked up from the dicing tape DT. The bare chip D is photographed by the wafer identification camera 14, and the positioning and surface inspection of the bare chip D are performed based on the image data obtained by the photographing. By performing image processing on the image data, the offsets (in the X, Y, and θ directions) of the bare chip D on the wafer holding stage 12 from the bare chip position reference point of the chip mounter are calculated and positioned. In addition, regarding the bare chip position reference point, a specified position of the wafer holding stage 12 is set as the initial setting of the device in advance and maintained. By performing image processing on the image data, the surface inspection of the bare chip D is performed.

[0060] The positioned bare chip D is peeled off from the dicing tape DT by the peeling unit 13 and the pick-up head 21. The bare chip D peeled off from the dicing tape DT is adsorbed and held by the collet 22 provided on the pick-up head 21, transferred, and placed on the intermediate stage 31.

[0061] The bare chip D on the intermediate stage 31 is photographed by the stage identification camera 34, and the positioning and surface inspection of the bare chip D are performed based on the image data obtained by the photographing. By performing image processing on the image data, the offsets (in the X, Y, and θ directions) of the bare chip D on the intermediate stage 31 from the bare chip position reference point of the chip mounter are calculated and positioned. In addition, regarding the bare chip position reference point, a specified position of the intermediate stage 31 is set as the initial setting of the device in advance and maintained. By performing image processing on the image data, the surface inspection of the bare chip D is performed.

[0062] The pick-up head 21 that has transferred the bare chip D to the intermediate stage 31 returns to the wafer supply unit 10. In the above-described order, the next bare chip D is peeled off from the dicing tape DT, and thereafter, the bare chips D are peeled off from the dicing tape DT one by one in the same order.

[0063] (Mounting process: Process S4)

[0064] The substrate S is transported to the mounting stage 46 by the transport unit 50. The substrate S placed on the mounting stage 46 is photographed by the substrate recognition camera 44, and the positioning and surface inspection of the substrate S are performed based on the image data obtained by the photographing. By performing image processing on the image data, the offset amounts (in the X, Y, and θ directions) of the substrate S from the substrate position reference point of the chip mounter 1 are calculated. In addition, regarding the substrate position reference point, a specified position of the mounting unit 40 is set as the initial setting of the device in advance and maintained. By performing image processing on the image data, the surface inspection of the substrate S is performed.

[0065] The adsorption position of the mounting head 41 is corrected according to the offset amount of the bare chip D on the intermediate stage 31 calculated in Process S3, and the bare chip D is adsorbed by the collet 42. The bare chip D is mounted on a specified part of the substrate S supported by the mounting stage 46 by the mounting head 41 that has adsorbed the bare chip D from the intermediate stage 31. Here, the specified part of the substrate S is the package region P of the substrate S, or the region where components have already been mounted and components are mounted in an added form thereto, or the mounting region of the components for stacked mounting. The bare chip D mounted on the substrate S is photographed by the substrate recognition camera 44, and inspections such as whether the bare chip D is mounted at the desired position are performed based on the image data obtained by the photographing.

[0066] The mounting head 41 after mounting the bare chip D on the substrate S returns to the intermediate stage 31. In the above-described order, the next bare chip D is picked up from the intermediate stage 31 and mounted on the substrate S. This order is repeated to mount the bare chips D in all the package regions P of the substrate S.

[0067] (Substrate unloading process: Process S5)

[0068] The substrate S on which the bare chip D has been mounted is transported to the substrate unloading unit 70. The substrate S is taken out from the transport claw 51 by the substrate unloading unit 70 and stored in the transport jig. The transport jig storing the substrate S is unloaded from the chip mounter 1.

[0069] As described above, the bare chip D is mounted on the substrate S and unloaded from the chip mounter 1. After that, for example, the transport jig storing the substrate S on which the bare chip D has been mounted is transported to the wire bonding process, and the electrodes of the bare chip D are electrically connected to the electrodes of the substrate S via Au wires or the like. Then, the substrate S is transported to the injection molding process, and the bare chip D and the Au wires are sealed with an injection molding resin (not shown), thereby completing the semiconductor package.

[0070] Next, Figure 6 and Figure 7 the peeling unit 13 will be described. Figure 6 isFigure 2 Top view of the peeling unit shown Figure 7 Schematically shows Figure 2 A view of an important part cross-section of the peeling unit shown

[0071] The peeling unit 13 is provided with a block portion 131 on a cylindrical dome 132. At the central portion of the upper surface of the dome 132, there is an opening 1321 that can achieve the up and down movement of the above-mentioned block portion 131. On the outer peripheral portion of the opening 1321 on the upper surface of the dome 132, a plurality of suction ports 1322 and a plurality of grooves 1323 connecting the plurality of suction ports 1322 are provided. When the peeling unit 13 is lifted so that its upper surface contacts the back surface of the cutting tape DT, the inside of the suction port 1322 is depressurized by a suction mechanism (not shown). At this time, the back surface of the cutting tape DT is attracted downward and closely contacts the upper surface of the dome 132.

[0072] The block portion 131 has blocks BLK1 to BLK4 that push up the cutting tape DT upward. The three outer blocks BLK1 to BLK3 are in the shape of a quadrangular prism with a quadrangular opening penetrating in the Z1-Z2 direction. The innermost block BLK4 is in the shape of a quadrangular prism. The second block BLK2 with a smaller size than the first block is arranged inside the first block BLK1. And, the third block BLK3 with a smaller size than the second block BLK2 is arranged inside the second block BLK2. And, the fourth block BLK4 with a smaller size than the third block BLK3 is arranged inside the third block BLK3.

[0073] The outermost block BLK1 among the four blocks BLK1 to BLK4 has a size slightly smaller than the outer periphery of the bare chip D to be peeled. Thus, the corner portion that becomes the outer periphery of the upper surface of the block BLK1 is slightly located inside compared to the outer edge of the bare chip D, so that the force for peeling the two can be concentrated at the portion (the outermost periphery of the bare chip D) that becomes the starting point when the bare chip D is peeled from the cutting tape DT.

[0074] As Figure 7 Shown, the blocks BLK1 to BLK4 can move up and down independently through the drive shafts ND1 to ND4 of the drive unit 133. For example, the drive shafts ND1 to ND4 are each composed of a motor and a push rod mechanism that converts the rotation of the motor into up and down movement.

[0075] Next, a method for setting and controlling the operation of the peeling unit 13 will be described.

[0076] The control unit 80 is configured to control the drive shafts ND1 to ND4 that drive the blocks BLK1 to BLK4 respectively based on the parameter table. Regarding the operations of the blocks BLK1 to BLK4, in the parameter table, for each step, the step time or time difference (TL), the rising or falling speed (V) of the block, the height (H) of the block, etc., which are the jacking conditions (peeling conditions), are set and controlled. Here, the time difference refers to the action time difference (interval time) used to adjust the processing time between the blocks. In other words, the time difference refers to the time from the end of the rising or falling of the block in each step to the start of the rising or falling of the block in the next step.

[0077] Regarding the setting of the parameter table, for example, it can be that the user inputs setting values for the items of the time chart recipe through the GUI (Graphical User Interface). Alternatively, it can also be that multiple time chart recipes with different setting items are prepared, and the user selects one time chart recipe from the multiple time chart recipes through the GUI and inputs setting values for the items of the selected time chart recipe. Or, the user can also set the parameter table by inputting in advance the setting values of the time chart recipe from an external device to a semiconductor manufacturing device such as a chip mounter through data communication, or by installing it from an external storage device to the semiconductor manufacturing device. The external storage device is, for example, a magnetic disk such as a tape, a floppy disk, and a hard disk, an optical disk such as a CD and a DVD, an optical disk such as an MO, or a semiconductor memory such as a USB memory and a memory card. In addition, the control unit 80 can rewrite (set) the parameter table in real time based on the information obtained from sensors or images of the recognition camera to change the jacking action (pickup condition).

[0078] As described above, through the setting of the parameter table, the operations of the blocks BLK1 to BLK4 of the peeling unit 13 can be freely set in the jacking action step, and the peeling unit 13 can perform various operations.

[0079] For example, the peeling unit 13 jacks up the blocks BLK1 to BLK4 simultaneously, then further jacks up the blocks BLK2 to BLK4 simultaneously, then further jacks up the blocks BLK3 and BLK4 simultaneously, and then further jacks up the block BLK4, enabling a pyramidal-shaped operation. In addition, the peeling unit 13 can perform an operation of jacking up the blocks BLK1 to BLK4 simultaneously and then descending in the order of the block BLK1, the block BLK2, and the block BLK3.

[0080] Use Figures 8 to 10 To illustrate an operation example of the peeling unit 13. Figure 8 It is to illustrate Figure 6 A diagram showing the jacking order in one operation example of the peeling unit shown. Figure 9 It is a diagram showing Figure 8 An example of the block operation timing in the order of. Figure 10It shows an example of a parameter table corresponding to the block operation timing of Figure 9 Fig.

[0081] The pick-up operation starts when the target bare chip D on the cutting tape DT is positioned between the peeling unit 13 and the collet 22. When the positioning is completed, vacuum is drawn through the suction port 1322 of the peeling unit 13 and the gaps between the blocks BLK1 to BLK4, thereby adsorbing the cutting tape DT onto the upper surface of the peeling unit 13. At this time, the upper surfaces of the blocks BLK1 to BLK4 are at the same height (initial position) as the upper surface of the dome 132. In this state, vacuum is supplied from a vacuum supply source (not shown), and the collet 22 descends while drawing vacuum toward the device surface of the bare chip D and lands on the upper surface of the bare chip D.

[0082] After that, the blocks BLK1 to BLK4 simultaneously rise to a specified height (h1) at a specified speed (s1) and become Figure 8 the first state shown in A of Figure 9 Fig. Here, as

[0083] shown in Figure 8 Fig., if the time for the blocks BLK1 to BLK4 to reach h1 is set as t1, then t1 = h1 / s1. After that, a specified time (t2) is waited for. The bare chip D rises while being held by the collet 22 and the blocks BLK1 to BLK4, but the peripheral portion of the cutting tape DT is still vacuum-adsorbed to the suction port 1322 of the dome 132 which is the periphery of the peeling unit 13, so tension is generated around the bare chip D. As a result, the peeling of the cutting tape DT starts around the bare chip D. Figure 9 Fig.

[0084] Next, the outermost block BLK1 descends to a height below the upper surface of the dome 132 at a constant speed (s2) and becomes Figure 8 the second state shown in B of

[0085] Fig. Here, as Figure 9 shown in Fig., if the time for the block BLK1 to reach the specified height (-h2) is set as t3, then t3 = (h1 + h2) / s2.

[0084] After a specified time (t10) from the start of the descent of the outermost block BLK1, in parallel with the descent of the outermost block BLK1, the second block BLK2 descends to a height below the upper surface of the dome 132 at a constant speed (s2) and becomes Figure 8 the third state shown in C of

[0085] Fig. Here, since the second block BLK2 descends to the height of the upper surface of the dome 132, the support of the cutting tape DT is no longer carried out, and the peeling of the cutting tape DT further proceeds due to the tension of the cutting tape DT.

[0085] After a specified time (t11) from the start of the descent of the second block BLK2, in parallel with the descent of the second block BLK2, the third block BLK3 descends to a height below the upper surface of the dome 132 at a constant speed (s2) and becomesFigure 8 The fourth state shown in D. Here, since the third block BLK3 descends to the height of the upper surface of the dome 132, the support of the dicing tape DT is no longer performed, and the peeling of the dicing tape DT further proceeds due to the tension of the dicing tape DT. Thus, except for the portion where the dicing tape DT contacts the block BLK4, the bare chip D is peeled off from the dicing tape DT.

[0086] After a predetermined time (t6) has elapsed since the descent of the third block BLK3 stopped, the blocks BLK1 to BLK3 rise at a constant speed (s3), the collet 22 rises, and the fourth block BLK4 descends at a constant speed (s4) to return to the initial position. Here, if the time when the blocks BLK1 to BLK3 reach the initial position is set as t8, then t8 = h2 / s3, and if the time when the block BLK4 reaches the initial position is set as t9, then t9 = h1 / s4. Thus, the operation of peeling the bare chip D from the dicing tape DT is completed. The peeling unit 13 peels off a part of the bare chip D from the dicing tape DT and assists in picking up the bare chip D from the dicing tape DT by the collet 22.

[0087] For Figure 10 the operation details of the parameter table are described in detail. Figure 10 As shown, TL is the time difference, V is the speed, and H is the height.

[0088] (1) Block BLK1

[0089] The time difference in the first step (STEP1) is t2, and the block BLK1 rises from the start of the first step at a speed of s1 to a height of h1 and maintains the state at the height of h1. The first step (STEP1) of the block BLK1 corresponds to Figure 8 the first state of

[0090] The time difference in the second step (STEP2) is (t4 + t5 + t6), and the block BLK1 descends from the start of the second step at a speed of s2 to a height of -h2 and maintains the state at the height of -h2. The second step (STEP2) of the block BLK1 corresponds to Figure 8 the second state to the fourth state of

[0091] The time difference in the third step (STEP3) is t9, and the block BLK1 rises from the start of the third step at a speed of s3 to the initial position (height is 0).

[0092] (2) Block BLK2

[0093] The time difference in the first step (STEP1) is (t2 + t10), and the block BLK2 rises from the start of the first step at a speed of s1 to a height of h1 and maintains the state at the height of h1. The first step (STEP1) of the block BLK2 corresponds to Figure 8corresponds to the first state and the second state.

[0094] The time difference of the second step (STEP2) is (t5 + t6). Block BLK2 descends from the start of the second step at a speed of s2 to a height of -h2 and maintains the state at the height of -h2. The second step (STEP2) of block BLK2 corresponds to Figure 8 the third state and the fourth state.

[0095] The time difference of the third step (STEP3) is t9, which causes block BLK2 to rise from the start of the third step at a speed of s3 to the initial position (height is 0).

[0096] (3) Block BLK3

[0097] The time difference of the first step (STEP1) is (t2 + t10 + t11). Block BLK3 rises from the start of the first step at a speed of s1 to a height of h1 and maintains the state at the height of h1. The first step (STEP1) of block BLK3 corresponds to Figure 8 the first state, the second state and the third state.

[0098] The time difference of the second step (STEP2) is t6. Block BLK3 descends from the start of the second step at a speed of s2 to a height of -h2 and maintains the state at the height of -h2. The second step (STEP2) of block BLK3 corresponds to Figure 8 the fourth state.

[0099] The time difference of the third step (STEP3) is t9. Block BLK3 rises from the start of the third step at a speed of s3 to the initial position (height is 0).

[0100] (4) Block BLK4

[0101] The time difference of the first step (STEP1) is (t2 + t3 + t4 + t5 + t6). Block BLK4 rises from the start of the first step at a speed of s1 to a height of h1 and maintains the state at the height of h1. The first step (STEP1) of block BLK4 corresponds to Figure 8 the first state, the second state, the third state and the fourth state.

[0102] The time difference of the second step (STEP2) is 0. Block BLK4 descends from the start of the second step at a speed of s4 to the initial position (height is 0).

[0103] Use Figure 11 and Figure 12 to illustrate the wafer mapping data. Figure 11 is a diagram showing an example of the wafer mapping data in the embodiment. Figure 12 is a diagram showing fromFigure 11 The figure of the wafer mapping data corresponding to the wafer mapping data after picking up the bare chips of the first classification of the wafer.

[0104] As described above, in the wafer mapping data, as Figure 11 shown, it includes data representing the grades and non-conformities of the bare chips. Regarding the identified grades, here, there are two, namely the first classification recorded as "1" on the figure and the second classification recorded as "2". In addition, the bare chips recorded as "9" on the figure are non-conforming products.

[0105] When picking up by each grade (classification), for example, sometimes after picking up all the bare chips of the first classification, the bare chips of the second classification are picked up. After the picking up of the bare chips of the first classification is completed, it becomes Figure 12 the wafer mapping data as shown. In other words, when picking up the bare chips of the second classification, the wafer is full of gaps, and the tension of the dicing tape around the bare chips to be picked up decreases. After the picking up of the bare chips of the first classification is completed, if the bare chips of the second classification are picked up under the same peeling conditions as the bare chips of the first classification, picking errors may sometimes occur.

[0106] Not limited to picking up by each grade, if picking up is performed under the same peeling conditions from the beginning (when there are many bare chips) to the end (when there are few bare chips), picking errors are likely to occur. For example, as the bare chips gradually decrease with picking, in this case, if picking up is performed under the same peeling conditions from the beginning to the end, picking errors are likely to occur. In addition, there is a case where the wafer is taken out during the picking up of a single wafer and then re-introduced. In this case, the proportion of the re-introduced bare chips decreases. If picking up is performed under the same peeling conditions as the wafer with a large proportion of bare chips, picking errors are likely to occur.

[0107] Therefore, in the embodiment, the peeling conditions are changed based on the peripheral information of the picked-up bare chips for picking. This will be described using Figures 11 to 16 for illustration. Figure 13 It is a figure showing the picking process in this embodiment. Figure 14 It is a figure for explaining the peripheral information. Figure 15 It is for explaining Figure 2 the relationship between the field of view of the wafer identification camera shown and the wafer. Figure 16 It is a figure showing a case example of the peripheral information. The steps described below are performed by the control unit 80.

[0108] (Step S11: Set the peripheral information)

[0109] Set the picking information indicating which position of the wafer the bare chips have been picked up and store it in the storage device. The picking information is set or updated before each picking. The picking information is set based on the wafer mapping data.

[0110] The pick-up information immediately after picking up a bare chip is information on the position where the bare chip does not exist. For example, assume that the bare chip Ds in the upper right of the wafer map data shown is picked up. The bare chip Ds is a bare chip of the first classification, and the pick-up information immediately after picking up the bare chip Ds is information on the position of the bare chip Ds. After that, the pick-up information is updated each time the picking up of the bare chips of the first classification is repeated. When the picking up of the bare chips of the first classification is completed, the bare chips of the second classification are picked up. The pick-up information immediately before picking up the bare chips of the second classification is Figure 11 information on the position of the bare chips of the first classification shown. In other words, the pick-up information is Figure 11 information on the position of the blank (white) of the wafer map data shown. Figure 12 The wafer map data shown is also pick-up information. The pick-up information changes each time a pick-up is made. Figure 12 The wafer map data shown is also pick-up information. The pick-up information changes each time a pick-up is made.

[0111] Based on the pick-up information, the surrounding information of the next bare chip to be picked up (the pick-up target bare chip) Dp is set. The surrounding information refers to configuration information such as the number, ratio, and position of the bare chips in the surrounding area of the pick-up target bare chip Dp. For example, Figure 12 the surrounding information of the pick-up target bare chip Dp shown is whether there is a bare chip in the surrounding area of the pick-up target bare chip Dp, and it is Figure 14 the information shown. In Figure 14 , there are bare chips at the three shaded places and no bare chips at the five unshaded places. In Figure 14 , the surrounding area of the pick-up target bare chip Dp is an area adjacent to the pick-up target bare chip Dp, and is set to a 3×3 range centered on the pick-up target bare chip Dp. The surrounding area of the pick-up target bare chip Dp may also be a 5×5 range centered on the pick-up target bare chip Dp, or may be a 7×7 range.

[0112] An example of setting the surrounding information based on the pick-up information has been described, but it may also be set based on whether a bare chip is recognized from the image data of the wafer recognition camera.

[0113] As Figure 15 shown, assume that when the pick-up target bare chip Dp is arranged at the center of the field of view IF of the wafer recognition camera 14, at least the bare chips adjacent to the pick-up target bare chip Dp are included in the field of view IF of the wafer recognition camera 14. The pick-up target bare chip Dp is photographed by the wafer recognition camera 14 to obtain image data. Based on this image data, it is recognized whether there is a bare chip, and thus the presence or absence information of the bare chips around the pick-up target bare chip Dp can be obtained. Thereby, the surrounding information can be set.

[0114] (Step S12: Set peeling conditions)

[0115] The peeling conditions are set based on the surrounding information. Additionally, the setting of the picking conditions is performed for each bare chip to be picked up. Depending on the surrounding information, there are cases where the peeling conditions remain unchanged. Here, the peeling conditions are, for example, Figure 10 the heights (h1), speeds (s1), and time differences (t2, t2 + t10, t2 + t10 + t11, t2 + t3 + t4 + t5 + t6) of blocks BLK1 to BLK4 as shown.

[0116] If there are few bare chips around the bare chip Dp to be picked up, the tension of the dicing tape DT around the bare chip Dp to be picked up becomes smaller. In this case, it is necessary to change the peeling conditions. For example, by increasing the lifting height (h1) and the speed (s1), the tension of the dicing tape DT around the bare chip Dp to be picked up can be increased. Additionally, by increasing the time difference (t2, t2 + t10, t2 + t10 + t11, t2 + t3 + t4 + t5 + t6), the bare chip Dp to be picked up can be peeled from the dicing tape DT even with a small tension. In other words, the peeling conditions are set to conditions that make it easy to peel the bare chip Dp to be picked up.

[0117] It is also possible to change the peeling conditions based on Figure 16 the configuration pattern of the bare chips (patterned surrounding information) as shown. In Figure 16 the unshaded parts around the bare chip Dp to be picked up indicate the absence of bare chips, and the shaded parts indicate the presence of bare chips. All the bare chip configuration patterns are not shown in Figure 16 . It is also possible not to change the peeling conditions for each of all the bare chip configuration patterns shown in Figure 16 .

[0118] A1 is a configuration pattern where there are no bare chips in the surrounding area adjacent to the bare chip Dp to be picked up. E5 is a configuration pattern where there are bare chips in all the surrounding areas adjacent to the bare chip Dp to be picked up.

[0119] A2 to A5 are configuration pattern examples where there are bare chips in the surrounding areas adjacent to the corners of the bare chip Dp to be picked up with respect to A1, and the number of bare chips increases in the order of A2 to A5. In other words, the tension of the dicing tape DT around the bare chip Dp to be picked up increases in the order of A2 to A5.

[0120] B1, C1, D1, and E1 are configuration pattern examples where there are bare chips in the surrounding areas adjacent to the sides of the bare chip Dp to be picked up with respect to A1, and the number of bare chips increases in the order of B1, C1, D1, and E1. In other words, the tension of the dicing tape DT around the bare chip Dp to be picked up increases in the order of B1, C1, D1, and E1.

[0121] The tension of the dicing tape DT around the bare chip Dp to be picked up is the smallest in A1 and the largest in E5.

[0122] (Step S13: Pickup)

[0123] Actuate the block portion 131 of the peeling unit 13 according to the set pickup conditions to peel the bare chip D from the dicing tape DT, and pick up the bare chip D using the pickup head 21.

[0124] (Step S14: Judgment)

[0125] Judge whether all the bare chips to be picked up have been picked up (pickup completed). If the pickup is not completed (No), return to step 12. If the pickup is completed (Yes), end.

[0126] According to the present embodiment, the peeling conditions are changed based on the peripheral information indicating the peripheral state of the bare chip Dp to be picked up. Since the peeling conditions are optimized for each picked-up bare chip, pickup errors can be reduced.

[0127] Since pickup errors are reduced, the stoppage of the device is decreased. As a result, the device operation time is increased, and an improvement in MTBA (Mean Time Between Attentions) can be achieved.

[0128] As described above, the invention completed by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can of course be made.

[0129] In the embodiment, an example in which the peeling unit is composed of a jacking block that moves the block up and down is described. The peeling unit is not limited thereto, as long as it assists in pickup and can change the peeling conditions. For example, a needle can be used instead of the block. In addition, the peeling unit can also slide the block or plate.

[0130] In addition, the peeling unit can also peel the bare chip from the dicing tape using heat (heating and melting), ultraviolet (UV) light (photoirradiation for chemical modification), or laser (photoirradiation for heating and melting). When there are few bare chips around the bare chip Dp to be picked up, increase the heating temperature, increase the irradiation intensity of UV light or laser, and / or increase the irradiation time.

[0131] In the embodiment, an example in which the number of blocks is four is described. However, depending on the bare chip size, etc., the number of blocks can be less than or more than four.

[0132] In the embodiment, an example of using a chip bonding film is described. However, a preprocessing section for coating an adhesive on the substrate can also be provided without using a chip bonding film.

[0133] In an embodiment, a chip mounter is described in which a bare chip is picked up from a wafer supply unit by a pick-up head and placed on an intermediate stage, and the bare chip placed on the intermediate stage is mounted on a substrate by a mounting head. However, it is not limited thereto, and it can also be applied to a chip mounting device that picks up a bare chip from a wafer supply unit.

[0134] For example, it can also be applied to a chip mounter that mounts a bare chip from a wafer supply unit on a substrate using a mounting head without an intermediate stage and a pick-up head.

[0135] In addition, it can also be applied to a flip chip mounter that picks up a bare chip from a wafer supply unit, rotates the bare chip pick-up head upward to deliver the bare chip to a mounting head, and mounts the bare chip on a substrate using the mounting head without an intermediate stage.

[0136] In the embodiment, a chip mounter is described as an example, but it can also be applied to a semiconductor manufacturing device that places the picked-up bare chip on a tray.

Claims

1. A semiconductor manufacturing apparatus, characterized in that, Comprising: A wafer holding stage that holds a wafer ring which holds a dicing tape adhered to a wafer divided into bare chips; A peeling unit that assists in picking up the bare chips from the dicing tape; and A control unit configured to set peeling conditions that are conditions for the operation of the peeling unit based on surrounding information which is configuration information of bare chips in the peripheral area of the bare chip to be picked up.

2. The semiconductor manufacturing apparatus according to claim 1, wherein The surrounding information is information on whether there are bare chips in the area adjacent to the bare chip to be picked up.

3. The semiconductor manufacturing apparatus according to claim 2, wherein The control unit is configured to set the surrounding information based on picking information indicating which position of the bare chips on the wafer have been picked up.

4. The semiconductor manufacturing apparatus according to claim 2, wherein The control unit is configured to capture an image of the bare chip to be picked up and its periphery to obtain image data, and set the surrounding information based on the obtained image data.

5. The semiconductor manufacturing apparatus according to claim 2, wherein The control unit is configured to pattern the surrounding information into a plurality of patterns and set the peeling conditions for each pattern.

6. The semiconductor manufacturing apparatus according to claim 1, wherein The peeling unit is a lifting unit that lifts a block or a pin, or a unit that slides a block or a plate, or a unit that peels the bare chip from the dicing tape using heat, ultraviolet light, or laser.

7. The semiconductor manufacturing apparatus according to claim 6, wherein The lifting unit is configured to have a block portion and a dome. The dome has an opening that enables the up and down movement of the block portion and a suction port provided on the outer periphery of the opening. The lifting unit contacts the dicing tape.

8. The semiconductor manufacturing apparatus according to claim 7, wherein The peeling conditions are the lifting height, lifting speed of the block of the block portion, and the time from when the movement of the block stops until the next movement starts.

9. The semiconductor manufacturing apparatus according to claim 8, wherein The control unit is configured to increase the lifting height, increase the lifting speed, and increase the time as the number of bare chips in the periphery of the bare chip to be picked up is fewer.

10. The semiconductor manufacturing apparatus according to claim 1, wherein It further includes a head member that picks up the bare chips.

11. A method for manufacturing a semiconductor device, characterized in that, Including: A process of loading the wafer ring into the semiconductor manufacturing apparatus of claim 1; and A process of picking up the bare chips by cooperation of a pick-up head and the peeling unit.

12. A picking method, wherein A wafer ring is held, where the wafer ring holds a dicing tape adhered to a wafer divided into bare chips, Peeling conditions that are conditions for the operation of the peeling unit are set based on surrounding information which is configuration information of bare chips in the peripheral area of the bare chip to be picked up, The bare chips are picked up by cooperation of a collet and the peeling unit that operates based on the peeling conditions.

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