Semiconductor packaging structure

Abstract

The invention discloses a semiconductor packaging structure. The semiconductor packaging structure comprises a lead frame, a first MOS (Metal Oxide Semiconductor) chip and a second MOS chip, a first electrode is arranged on the front surface of the first MOS chip, and a second electrode and a third electrode are arranged on the back surface of the first MOS chip; the first MOS chip is arranged on the base island, and the first electrode is electrically connected with the base island; a fourth electrode is arranged on the front surface of the second MOS chip, and a fifth electrode and a sixth electrode are arranged on the back surface of the first MOS chip; the second MOS chip is stacked on the first MOS chip, and the fourth electrode is electrically connected with the second electrode; the first connecting pin is electrically connected with a sixth electrode of the second MOS chip; the first connecting pin is electrically connected with the first electrode of the first MOS chip, the second connecting pin is electrically connected with the third electrode of the first MOS chip and the fifth electrode of the second MOS chip, the first MOS chip and the second MOS chip which are connected in series are packaged in an up-down stacking mode, the occupied area of the first MOS chip and the second MOS chip in the semiconductor packaging structure is effectively reduced, and miniaturization of multi-MOS chip packaging can be achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure. Background Art

[0002] With the continuous development of the semiconductor industry, and the continuous miniaturization and light weight of consumer electronic products such as smart phones, tablet computers, and wearable devices, the demand for high-performance and small-size power semiconductor devices is increasing continuously, and in many cases, multiple semiconductor devices need to be used in combination. As an important semiconductor device in these devices, the market demand for the packaging of miniaturized MOS transistors (MOSFETs, metal-oxide-semiconductor field-effect transistors) also increases accordingly; compared with the previous generation of electronic products, intelligent products require more lightness, thinness, shortness, and smallness in application, especially in portable electronic products, earphones or bracelets, watches, etc. in the wearable field, and have higher requirements for the occupied area and thickness of parts.

[0003] In the current prior art for multi-MOS transistor packaging, most of them adopt a flat layout. When using this packaging structure to package multiple MOS transistors, due to the flat layout of each MOS transistor, the space occupied is relatively large, which does not meet the requirements of miniaturized semiconductor packaging. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor packaging structure to solve the problem that the existing semiconductor packaging structure has a relatively large volume.

[0005] A semiconductor packaging structure includes a lead frame, a first MOS chip, and a second MOS chip; The lead frame includes a base island and first, second, and third connection pins arranged on the periphery of the base island; the third connection pin is electrically connected to the base island; The front surface of the first MOS chip is provided with a first electrode, and the back surface of the first MOS chip is provided with a second electrode and a third electrode; the first MOS chip is arranged on the base island, and the first electrode is electrically connected to the base island; The front surface of the second MOS chip is provided with a fourth electrode, and the back surface of the first MOS chip is provided with a fifth electrode and a sixth electrode; the second MOS chip is stacked on the first MOS chip, and the fourth electrode is electrically connected to the second electrode; The first connection pin is electrically connected to the sixth electrode of the second MOS chip; the second connection pin is electrically connected to the third electrode of the first MOS chip and the fifth electrode of the second MOS chip respectively.

[0006] Further, the semiconductor packaging structure includes an electrical connection member and an insulating support member; The electrical connector includes a connection body, and a first connection portion and a second connection portion extending along both sides of the connection body in the length direction thereof; the first connection portion is disposed on the second electrode of the first MOS chip, and the second connection portion is disposed in a suspended manner and is held above the base island through the insulating support member; The second MOS chip is disposed on the electrical connector, and a fourth electrode of the second MOS chip is electrically connected to the second electrode of the first MOS chip through the electrical connector.

[0007] Further, the first connection portion covers a partial area on the back surface of the first MOS chip, and other areas on the back surface of the first MOS chip form exposed areas, and a third electrode of the first MOS chip is disposed in the exposed areas.

[0008] Further, the first connection portion is L-shaped.

[0009] Further, a first deformation portion protruding to one side is formed in a first area of the first connection portion through a stamping process, and the first deformation portion includes a first inclined side wall and a first top platform that are smoothly transitioned with the connection body; A first continuous planar area that is not stamped is provided around the first deformation portion, and the thickness of the first continuous planar area is the same as the thickness of the connection body; At least a part of the first top platform is electrically connected to the second electrode of the first MOS chip.

[0010] Further, a second deformation portion protruding to one side is formed in a second area of the second connection portion through a stamping process, and the second deformation portion includes a second inclined side wall and a second top platform that are smoothly transitioned with the connection body; A second continuous planar area that is not stamped is provided around the second deformation portion, and the thickness of the second continuous planar area is the same as the thickness of the connection body; One end of the insulating support member is fixedly connected to the second top platform, and the other end of the insulating support member is fixedly connected to the base island.

[0011] Further, the material of the electrical connector is copper.

[0012] Further, the insulating support member is made of a high-temperature resistant insulating material.

[0013] Further, a sixth electrode of the second MOS chip is electrically connected to the first connection pin through a first wire; A third electrode of the first MOS chip is electrically connected to the second connection pin through a second wire; a fifth electrode of the second MOS chip is electrically connected to the second connection pin through a third wire.

[0014] Further, the lead frame further includes a fourth connection pin electrically connected to the first connection pin; the fourth connection pin is disposed adjacent to the first connection pin, and the fourth connection pin is electrically connected to the sixth electrode of the second MOS chip through a fourth wire.

[0015] An embodiment of the present invention provides a semiconductor package structure, which includes a lead frame, a first MOS chip, and a second MOS chip; the lead frame includes a base island and first, second, and third connection pins disposed on the periphery of the base island; the third connection pin is electrically connected to the base island; a first electrode is disposed on the front surface of the first MOS chip, and a second electrode and a third electrode are disposed on the back surface of the first MOS chip; the first MOS chip is disposed on the base island, and the first electrode is electrically connected to the base island; a fourth electrode is disposed on the front surface of the second MOS chip, and a fifth electrode and a sixth electrode are disposed on the back surface of the first MOS chip; the second MOS chip is stacked on the first MOS chip, and the fourth electrode is electrically connected to the second electrode; the first connection pin is electrically connected to the sixth electrode of the second MOS chip; the second connection pin is electrically connected to the third electrode of the first MOS chip and the fifth electrode of the second MOS chip respectively, so as to package the series-connected first MOS chip and second MOS chip in a stacked manner, effectively reducing the occupied area of the first MOS chip and the second MOS chip in the semiconductor package structure, which is beneficial to realizing the miniaturization of multi-MOS chip packaging. Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0017] Figure 1 is a schematic diagram of a semiconductor package structure according to an embodiment of the present invention; Figure 2 is another schematic diagram of a semiconductor package structure according to an embodiment of the present invention; Figure 3 is another schematic diagram of a semiconductor package structure according to an embodiment of the present invention; Figure 4 is a schematic diagram of an electrical connector according to an embodiment of the present invention.

[0018] In the figure: 1, lead frame; 2, first MOS chip; 3, second MOS chip; 4, electrical connector; 41, first connection part; 411, first area; 42, second connection part; 421, second area; 5, insulating support. Detailed Embodiments

[0019] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0020] It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. Like reference numerals throughout the drawings denote like elements.

[0021] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below may be denoted as a second element, component, region, layer or section without departing from the teachings of the present invention.

[0022] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein for convenience in describing the relationship of one element or feature shown in the drawings to another element or feature. It should be understood that, in addition to the orientation shown in the drawings, spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0023] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0024] To fully understand the present invention, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed by the present invention. The preferred embodiments of the present invention are described in detail below. However, in addition to these detailed descriptions, the present invention may also have other embodiments.

[0025] This embodiment provides a semiconductor package structure, as Figures 1 to 3 shown, comprising a lead frame 1, a first MOS chip 2 and a second MOS chip 3; the lead frame 1 includes a base island and first, second and third connection pins arranged on the periphery of the base island; the third connection pin is electrically connected to the base island; the front surface of the first MOS chip 2 is provided with a first electrode, and the back surface of the first MOS chip 2 is provided with a second electrode and a third electrode; the first MOS chip 2 is arranged on the base island, and the first electrode is electrically connected to the base island; the front surface of the second MOS chip 3 is provided with a fourth electrode, and the back surface of the first MOS chip 2 is provided with a fifth electrode and a sixth electrode; the second MOS chip 3 is stacked on the first MOS chip 2, and the fourth electrode is electrically connected to the second electrode; the first connection pin is electrically connected to the sixth electrode of the second MOS chip 3; the second connection pin is electrically connected to the third electrode of the first MOS chip 2 and the fifth electrode of the second MOS chip 3 respectively.

[0026] As an example, the semiconductor package structure adopts DFN (Dual Flat No-lead Package) packaging. Optionally, the lead frame 1 inside the semiconductor package structure is a six-pin lead frame. Exemplarily, the lead frame 1 includes a base island disposed in the central region and two rows of connection pins arranged side by side on both sides of the base island. Three pins are arranged at intervals in each row. Exemplarily, the first row of pins successively includes a first connection pin, a fourth connection pin, and a second connection pin; the second row of pins successively includes a sixth connection pin, a third connection pin, and a fifth connection pin. The third connection pin is electrically connected to the base island through a semi-etching process. The first connection pin is used for electrically connecting the sixth electrode of the second MOS chip 3. The second connection pin is used for electrically connecting the third electrode of the first MOS chip 2 and the fifth electrode of the second MOS chip 3. The fourth connection pin is electrically connected to the first connection pin and is used for connecting the sixth electrode of the second MOS chip 3 to improve the overcurrent and heat dissipation capabilities. The fifth connection pin and the sixth connection pin are suspended. The fourth connection pin, the fifth connection pin, and the sixth connection pin all adopt the frame semi-etching process so that the fourth connection pin, the fifth connection pin, and the sixth connection pin are not exposed after encapsulation.

[0027] As an example, the first MOS chip 2 and the second MOS chip 3 are of the same type of MOS chip. Exemplarily, both the first MOS chip 2 and the second MOS chip 3 are N-type MOS chips or P-type MOS chips. Exemplarily, the first electrode of the first MOS chip 2 is the drain electrode, the second electrode of the first MOS chip 2 is the source electrode, and the third electrode of the first MOS chip 2 is the gate electrode. The fourth electrode of the second MOS chip 3 is the drain electrode, the fifth electrode of the second MOS chip 3 is the source electrode, and the sixth electrode of the first MOS chip 2 is the gate electrode.

[0028] In this embodiment, the semiconductor package structure includes a lead frame 1, a first MOS chip 2, and a second MOS chip 3; the lead frame 1 includes a base island and a first connection pin, a second connection pin, and a third connection pin arranged on the periphery of the base island; the third connection pin is electrically connected to the base island; a first electrode is arranged on the front surface of the first MOS chip 2, and a second electrode and a third electrode are arranged on the back surface of the first MOS chip 2; the first MOS chip 2 is arranged on the base island, and the first electrode is electrically connected to the base island; a fourth electrode is arranged on the front surface of the second MOS chip 3, and a fifth electrode and a sixth electrode are arranged on the back surface of the first MOS chip 2; the second MOS chip 3 is stacked on the first MOS chip 2, and the fourth electrode is electrically connected to the second electrode; the first connection pin is electrically connected to the sixth electrode of the second MOS chip 3; the second connection pin is electrically connected to the third electrode of the first MOS chip 2 and the fifth electrode of the second MOS chip 3 respectively, so as to package the series-connected first MOS chip 2 and second MOS chip 3 in a stacked manner, effectively reducing the occupied area of the first MOS chip 2 and the second MOS chip 3 in the semiconductor package structure, which is beneficial to realizing the miniaturization of the multi-MOS chip package.

[0029] In one embodiment, the semiconductor package structure includes an electrical connector 4 and an insulating support 5; as Figure 4 shown, the electrical connector 4 includes a connection body and a first connection portion 41 and a second connection portion 42 extending along both sides of the length direction of the connection body; the first connection portion 41 is arranged on the second electrode of the first MOS chip 2, and the second connection portion 42 is arranged in a suspended manner and is held above the base island through the insulating support 5; the second MOS chip 3 is arranged on the electrical connector 4, and the fourth electrode of the second MOS chip 3 is electrically connected to the second electrode of the first MOS chip 2 through the electrical connector 4.

[0030] As an example, the electrical connector 4 is made of a metal material. The metal can be a composite copper sheet or a copper sheet. The insulating support 5 is made of a high-temperature resistant insulating material. Preferably, the insulating support 5 is a ceramic to prevent the high temperature from affecting the stability of the home support.

[0031] In the related art, multiple MOS chips in the semiconductor package structure are laid flat, and the MOS chips inside the semiconductor package structure are electrically connected to the connection pins of the semiconductor package structure through wires. When the semiconductor package structure is applied to a PCB board, if it is necessary to connect multiple MOS chips in series in the semiconductor package structure, additional circuits need to be added in the PCB board, which requires a large circuit area.

[0032] As an example, the electrical connector 4 is held on the first MOS chip 2 through the first connecting portion 41 and on the insulating support 5 through the second connecting portion 42, so that the second MOS chip 3 can be stably and reliably carried on the electrical connector 4, enabling the first MOS chip 2 and the second MOS chip 3 to achieve a common pole through the electrical connector 4, reducing the external PCB lines when the first MOS chip 2 and the second MOS chip 3 are in series, and thus reducing the line area on the PCB board. Moreover, due to the presence of the electrical connector 4 and the insulating support 5, a second MOS chip 3 with a size larger than that of the first MOS chip 2 can also be stacked on the electrical connector 4. At the same time, wire bonding can be performed in the suspended area between the second connecting portion 42 and the base island, increasing the space utilization rate.

[0033] In an embodiment, the first connecting portion 41 covers a partial area on the back surface of the first MOS chip 2, and other areas on the back surface of the first MOS chip 2 form exposed areas, and the third electrode of the first MOS chip 2 is disposed in the exposed areas.

[0034] In this embodiment, the first connecting portion 41 covers a partial area on the back surface of the first MOS chip 2, and other areas on the back surface of the first MOS chip 2 form exposed areas, and the third electrode of the first MOS chip 2 is disposed in the exposed areas to facilitate wire bonding of the third electrode, and at the same time, enable the electrical connector 4 to have a large enough area to carry the second MOS chip 3.

[0035] In an embodiment, the first connecting portion 41 is in an L shape. In this embodiment, the first connecting portion 41 is in an L shape. On the one hand, it can ensure that there is an exposed area with a sufficient area for disposing the third electrode, and on the other hand, it can increase the electrical contact area between the fourth electrode of the first connecting portion 41 and the second MOS chip 3 and the second electrode of the first MOS chip 2, thereby increasing the current-carrying capacity.

[0036] In an embodiment, a first deformed portion protruding to one side is formed on the first region 411 of the first connecting portion 41 through a stamping process. The first deformed portion includes a first inclined side wall and a first top platform that are smoothly transitioned with the connecting body; a first continuous planar region that is not stamped is provided around the first deformed portion, and the thickness of the first continuous planar region is the same as the thickness of the connecting body; at least part of the first top platform is electrically connected to the second electrode of the first MOS chip 2.

[0037] Among them, the shape, area, and position of the first region 411 can be determined according to actual experience and are not limited herein.

[0038] As an example, at least part of the first top platform is electrically connected to the second electrode of the first MOS chip 2. In this example, the electrical connection between the first top platform and the second electrode of the first MOS chip 2 can be achieved by applying solder paste and then curing through a reflow oven to ensure that the electrical connection has high firmness and current-carrying capacity.

[0039] In one embodiment, a second deformation portion that protrudes to one side is formed in a second region 421 of the second connecting portion 42 through a stamping process. The second deformation portion includes a second inclined sidewall and a second top platform that are smoothly transitioned with the connecting body; an unstamped second continuous planar region is provided around the second deformation portion, and the thickness of the second continuous planar region is the same as the thickness of the connecting body; one end of the insulating support 5 is fixedly connected to the second top platform, and the other end of the insulating support 5 is fixedly connected to the base island.

[0040] Wherein, the shape, area, and position of the second region can be determined according to actual experience and are not limited herein.

[0041] As an example, one end of the insulating support 5 is fixedly connected to the second top platform after being cured with glue or solder paste, and the other end of the insulating support 5 is fixedly connected to the base island after being cured with glue or solder paste. By contacting one end of the second top platform with the insulating support 5, the firmness of the contact surface can be improved.

[0042] Furthermore, the processing method of the electrical connector 4 includes: First, determine multiple processing regions for the electrical connectors 4 on the initial copper sheet, and determine a first region 411 of the first connecting portion 41 and a second region 421 of the second connecting portion 42 on each electrical connector 4; then, stamp the first region 411 and the second region 421 in each processing region; then, paste an insulating support 5 on the second top platform of each second region 421 with glue; finally, cut each processing region to obtain multiple electrical connectors 4.

[0043] In one embodiment, the sixth electrode of the second MOS chip 3 is electrically connected to the first connection pin through a first wire; the third electrode of the first MOS chip 2 is electrically connected to the second connection pin through a second wire; the fifth electrode of the second MOS chip 3 is electrically connected to the second connection pin through a third wire.

[0044] As an example, the sixth electrode of the second MOS chip 3 is electrically connected to the first connection pin through a first wire, thereby realizing the electrical connection between the second MOS chip 3 and the first connection pin; the third electrode of the first MOS chip 2 is electrically connected to the second connection pin through a second wire; the fifth electrode of the second MOS chip 3 is electrically connected to the second connection pin through a third wire, so that the second connection pin can control the third electrode of the first MOS chip 2 and the fifth electrode of the second MOS chip 3 at the same time, reducing the number of circuits.

[0045] In one embodiment, the lead frame 1 further includes a fourth connection pin electrically connected to the first connection pin; the fourth connection pin is disposed adjacent to the first connection pin, and the fourth connection pin is electrically connected to the sixth electrode of the second MOS chip 3 through a fourth wire.

[0046] In this embodiment, the sixth electrode is simultaneously connected to the first connection pin and the fourth connection pin that are electrically connected to each other through the first wire and the fourth wire, which can increase the over-current capacity at the sixth electrode.

[0047] As an example, the processing technological process of the above semiconductor package structure includes: S1: Prepare a lead frame 1 with six connection pins, and the base island of the lead frame 1 is electrically connected to the third connection pin; S2: Use a die bonder to solder or glue on the base island of the lead frame 1, place the first MOS chip 2 at an appropriate position on the base island and cure it; S3: Apply solder paste at the second electrode (source electrode) on the back of the first MOS chip 2, place the electrical connector 4 (composite copper sheet) on the second electrode (source electrode) of the first MOS chip 2, so as to facilitate the bonding of the first MOS chip 2 and the second MOS chip 3 through the electrical connector 4 (composite copper sheet). An insulating support 5 is provided between the electrical connector 4 (composite copper sheet) and the base island, and the insulating support 5 is approximately located at the middle position between the sixth connection pin and the first connection pin, and cure it through a reflow oven; S4. Use a die bonder to solder or glue on the electrical connector 4 (composite copper sheet), apply solder paste at the fourth electrode (drain electrode) of the second MOS chip 3, place the second MOS chip 3 on the electrical connector 4 (composite copper sheet), and cure it through a reflow oven; S5: Wire bond between the third electrode (gate electrode) of the first MOS chip 2 and the second connection pin, between the fifth electrode (gate electrode) of the second MOS chip 3 and the second connection pin, and between the sixth electrode (source electrode) of the second MOS chip 3 and the first connection pin and the fourth connection pin; S6: Encapsulate and post-cure.

[0048] The above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A semiconductor package structure, characterized in that, It includes a lead frame, a first MOS chip and a second MOS chip; The lead frame includes a base island and first, second and third connection pins arranged on the periphery of the base island; the third connection pin is electrically connected to the base island; On the front of the first MOS chip, there is a first electrode, and on the back of the first MOS chip, there are a second electrode and a third electrode; the first MOS chip is arranged on the base island, and the first electrode is electrically connected to the base island; On the front of the second MOS chip, there is a fourth electrode, and on the back of the first MOS chip, there are a fifth electrode and a sixth electrode; the second MOS chip is stacked on the first MOS chip, and the fourth electrode is electrically connected to the second electrode; The first connection pin is electrically connected to the sixth electrode of the second MOS chip; the second connection pin is respectively electrically connected to the third electrode of the first MOS chip and the fifth electrode of the second MOS chip.

2. The semiconductor package structure according to claim 1, wherein The semiconductor package structure includes an electrical connector and an insulating support; The electrical connector includes a connection body and first and second connection portions extending along both sides in the length direction of the connection body; the first connection portion is arranged on the second electrode of the first MOS chip, and the second connection portion is arranged in a suspended manner and is held above the base island through the insulating support; The second MOS chip is arranged on the electrical connector, and the fourth electrode of the second MOS chip is electrically connected to the second electrode of the first MOS chip through the electrical connector.

3. The semiconductor package structure according to claim 2, wherein, The first connection portion covers a partial area on the back of the first MOS chip, and other areas on the back of the first MOS chip form an exposed area, and the third electrode of the first MOS chip is arranged in the exposed area.

4. The semiconductor package structure according to claim 3, wherein, The first connection portion is L-shaped.

5. The semiconductor package structure according to claim 2, wherein A first deformed portion protruding to one side is formed in a first area of the first connection portion through a stamping process. The first deformed portion includes a first inclined sidewall and a first top platform that are smoothly transitioned with the connection body; A first continuous planar area that is not stamped is arranged around the first deformed portion, and the thickness of the first continuous planar area is the same as the thickness of the connection body; At least part of the first top platform is electrically connected to the second electrode of the first MOS chip.

6. The semiconductor package structure according to claim 2, wherein, A second deformed portion protruding to one side is formed in a second area of the second connection portion through a stamping process. The second deformed portion includes a second inclined sidewall and a second top platform that are smoothly transitioned with the connection body; A second continuous planar area that is not stamped is arranged around the second deformed portion, and the thickness of the second continuous planar area is the same as the thickness of the connection body; One end of the insulating support is fixedly connected to the second top platform, and the other end of the insulating support is fixedly connected to the base island.

7. The semiconductor package structure according to claim 2, wherein, The material of the electrical connector is copper.

8. The semiconductor package structure according to claim 2, wherein The insulating support is made of a high-temperature resistant insulating material.

9. The semiconductor package structure according to claim 1, wherein, The sixth electrode of the second MOS chip is electrically connected to the first connection pin through a first wire; The third electrode of the first MOS chip is electrically connected to the second connection pin through a second wire; the fifth electrode of the second MOS chip is electrically connected to the second connection pin through a third wire.

10. The semiconductor package structure according to claim 1, wherein The lead frame further includes a fourth connection pin electrically connected to the first connection pin; the fourth connection pin is disposed adjacent to the first connection pin, and the fourth connection pin is electrically connected to the sixth electrode of the second MOS chip through a fourth wire.

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