Protection circuit and electronic device

Abstract

The invention discloses a protection circuit and electronic equipment, and belongs to the technical field of electronics. The first end of a first protection sub-circuit and the first end of a second protection sub-circuit in the protection circuit are both connected with the input and output port of a protected circuit, and the second end of the first protection sub-circuit and the second end of the second protection sub-circuit are both grounded. The first protection sub-circuit is used for performing first charging processing under the action of a first electric signal of which the amplitude output by the input / output port is higher than a first amplitude threshold; the second protection sub-circuit is used for generating a second electric signal under the action of the first electric signal; and the first protection sub-circuit is also used for carrying out second charging processing under the action of the second electric signal. The protection capability of the protection circuit is improved, and the possibility that the protected circuit is damaged is reduced.

Description

Technical Field

[0001] This application relates to the field of electronic technologies, and particularly to a protection circuit and an electronic device. Background Art

[0002] During the operation of a circuit, it may be impacted by various electrical or physical factors. For example, the circuit may be impacted by EOS (Electrical Over Stress) or ESD (Electrical Static Discharge). When a circuit is impacted by EOS, it means that the current or voltage borne by the circuit exceeds the tolerance range of the current or voltage of the circuit. When a circuit is impacted by ESD, it means that the circuit is affected by the instantaneous high voltage and large current generated by electrostatic discharge.

[0003] When a circuit is impacted by EOS or ESD, it may lead to problems such as device damage and circuit performance degradation in the circuit. Therefore, in the field of electronic technologies, an EOS ESD protection circuit is usually used to protect the circuit to be protected and reduce the degree of EOS and ESD impacts on the circuit to be protected. For example, the EOS ESD protection circuit can charge or discharge based on the instantaneous high voltage or high current input to both the EOS ESD protection circuit and the circuit to be protected through the capacitor in the EOS ESD protection circuit, thereby reducing the voltage and current input to the circuit to be protected. Summary of the Invention

[0004] This application provides a protection circuit and an electronic device, which can be used to improve the protection ability of the protection circuit and reduce the possibility of damage to the circuit to be protected. The technical solutions are as follows:

[0005] On the one hand, this application provides a protection circuit, which includes a first protection sub-circuit and a second protection sub-circuit. The first ends of the first protection sub-circuit and the second protection sub-circuit are both connected to the input / output port of the circuit to be protected, and the second ends of the first protection sub-circuit and the second protection sub-circuit are both grounded. The first protection sub-circuit is used to perform a first charging process under the action of a first electrical signal output from the input / output port, and the amplitude of the first electrical signal is higher than a first amplitude threshold. The second protection sub-circuit is used to generate a second electrical signal under the action of the first electrical signal. The first protection sub-circuit is further used to perform a second charging process under the action of the second electrical signal.

[0006] In a possible implementation manner, the first protection sub-circuit includes a first capacitor, one end of the first capacitor is connected to the input / output port, and the other end of the first capacitor is grounded.

[0007] In a possible implementation, the second protection sub-circuit includes a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device and the second semiconductor device are connected to the input / output port through a first node. The first semiconductor device and the third semiconductor device are also grounded. The second semiconductor device is also connected to the third semiconductor device. The second semiconductor device is in a forward conduction state under the action of a first electrical signal. The third semiconductor device and the first semiconductor device are in a reverse cut-off state under the action of the first electrical signal. Under the combined action of the first semiconductor device, the second semiconductor device, the third semiconductor device, and the first electrical signal, a second electrical signal is formed at the first node.

[0008] In a possible implementation, the reverse breakdown thresholds of the first semiconductor device and the third semiconductor device are greater than a second amplitude threshold, the second amplitude threshold is greater than a first amplitude threshold, the amplitude of the second electrical signal is less than or equal to the second amplitude threshold, the second amplitude threshold is related to the protection level of the protection circuit, and the amplitude of the second electrical signal is related to the resistance values of the first semiconductor device and the third semiconductor device in the reverse cut-off state.

[0009] In a possible implementation, the protection circuit further includes a third protection sub-circuit. The third protection sub-circuit is connected to the power supply port of the circuit to be protected. The second protection sub-circuit is connected to the third protection sub-circuit through a second node and grounded. The third protection sub-circuit is configured to perform a third charging process under the action of a third electrical signal output from the power supply port and transmit the third electrical signal to the ground. The amplitude of the third electrical signal is higher than the first amplitude threshold.

[0010] In a possible implementation, the third protection sub-circuit includes a second capacitor and a fourth semiconductor device. One end of the fourth semiconductor device and the second capacitor are both connected to the power supply port. The other end of the fourth semiconductor device and the second capacitor are both grounded. The second capacitor is configured to perform a third charging process under the action of a first sub-signal in the third electrical signal output from the power supply port. The fourth semiconductor device is configured to transmit a second sub-signal in the third electrical signal to the ground. The second capacitor is further configured to transmit a fourth electrical signal generated based on the first sub-signal to the fourth semiconductor device after completing the third charging process. The fourth semiconductor device is further configured to transmit the fourth electrical signal to the ground.

[0011] In a possible implementation, the second capacitor is located outside the chip on which the circuit to be protected is deployed, and the fourth semiconductor device is located on the chip.

[0012] In a possible implementation, the circuit to be protected is located on the chip, and the first protection sub-circuit is located outside the chip.

[0013] On the other hand, an electronic device is provided. The electronic device includes a protection circuit and a circuit to be protected. The protection circuit includes a first protection sub-circuit and a second protection sub-circuit. The first ends of the first protection sub-circuit and the second protection sub-circuit are both connected to the input / output port of the circuit to be protected, and the second ends of the first protection sub-circuit and the second protection sub-circuit are both grounded. The first protection sub-circuit is configured to perform a first charging process under the action of a first electrical signal output from the input / output port, and the amplitude of the first electrical signal is higher than a first amplitude threshold. The second protection sub-circuit is configured to generate a second electrical signal under the action of the first electrical signal. The first protection sub-circuit is further configured to perform a second charging process under the action of the second electrical signal.

[0014] In a possible implementation manner, the first protection sub-circuit includes a first capacitor. One end of the first capacitor is connected to the input / output port, and the other end of the first capacitor is grounded.

[0015] In a possible implementation manner, the second protection sub-circuit includes a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device and the second semiconductor device are connected to the input / output port through a first node. The first semiconductor device and the third semiconductor device are also grounded. The second semiconductor device is also connected to the third semiconductor device. The second semiconductor device is in a forward conduction state under the action of the first electrical signal. The third semiconductor device and the first semiconductor device are in a reverse cut-off state under the action of the first electrical signal. Under the combined action of the first semiconductor device, the second semiconductor device, the third semiconductor device, and the first electrical signal, a second electrical signal is formed at the first node.

[0016] In a possible implementation manner, the reverse breakdown thresholds of the first semiconductor device and the third semiconductor device are greater than a second amplitude threshold. The second amplitude threshold is greater than the first amplitude threshold. The amplitude of the second electrical signal is less than or equal to the second amplitude threshold. The second amplitude threshold is related to the protection level of the protection circuit. The amplitude of the second electrical signal is related to the resistance values of the first semiconductor device and the third semiconductor device in the reverse cut-off state.

[0017] In a possible implementation manner, the protection circuit further includes a third protection sub-circuit. The third protection sub-circuit is connected to the power supply port of the circuit to be protected. The second protection sub-circuit and the third protection sub-circuit are connected through a second node and grounded. The third protection sub-circuit is configured to perform a third charging process under the action of a third electrical signal output from the power supply port and transmit the third electrical signal to the ground. The amplitude of the third electrical signal is higher than the first amplitude threshold.

[0018] In a possible implementation, the third protection sub-circuit includes a second capacitor and a fourth semiconductor device. One end of the fourth semiconductor device and the second capacitor are both connected to the power supply port, and the other end of the fourth semiconductor device and the second capacitor are both grounded. The second capacitor is configured to perform a third charging process under the action of a first sub-signal in the third electrical signal output from the power supply port. The fourth semiconductor device is configured to transmit a second sub-signal in the third electrical signal to the ground. The second capacitor is further configured to transmit a fourth electrical signal generated based on the first sub-signal to the fourth semiconductor device after completing the third charging process. The fourth semiconductor device is further configured to transmit the fourth electrical signal to the ground.

[0019] In a possible implementation, the second capacitor is located outside the chip on which the circuit to be protected is deployed, and the fourth semiconductor device is located on the chip.

[0020] In a possible implementation, the circuit to be protected is located on the chip, and the first protection sub-circuit is located outside the chip.

[0021] The technical solution provided by this application at least brings the following beneficial effects:

[0022] When the amplitude of the first electrical signal output from the input / output port is higher than the first amplitude threshold, it represents that the input / output port has been impacted. Therefore, the first protection sub-circuit performs a first charging process under the action of the first electrical signal to absorb the first electrical signal and reduce the amplitude of the electrical signal transmitted to the circuit to be protected through the input / output port, or in other words, reduce the electrical energy transmitted to the circuit to be protected. In addition, after receiving the first electrical signal, the second protection sub-circuit generates a second electrical signal based on the first electrical signal to increase the potential of the high-potential end of the first protection sub-circuit. The first protection sub-circuit also receives the second electrical signal and performs a second charging process under the action of the second electrical signal to achieve further absorption of the electrical signal, thereby further preventing the circuit to be protected from being damaged by high-amplitude electrical signals and improving the protection ability of the protection circuit. Description of the Drawings

[0023] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 is a schematic structural diagram of a protection circuit provided by the related art;

[0025] Figure 2 is a schematic structural diagram of a protection circuit provided by an embodiment of this application;

[0026] Figure 3 It is a schematic structural diagram of a first protection sub-circuit provided by an embodiment of the present application;

[0027] Figure 4 It is a schematic structural diagram of a second protection sub-circuit provided by an embodiment of the present application;

[0028] Figure 5 It is a schematic structural diagram of another protection circuit provided by an embodiment of the present application;

[0029] Figure 6 It is a schematic structural diagram of a third protection sub-circuit provided by an embodiment of the present application;

[0030] Figure 7 It is a schematic structural diagram of another protection circuit provided by an embodiment of the present application;

[0031] Figure 8 It is a schematic structural diagram of another protection circuit provided by an embodiment of the present application. Detailed implementation manners

[0032] To make the objectives, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0033] EOS refers to the phenomenon that the operating environment of the circuit exceeds the expectation, such as the power supply voltage exceeding the normal range. The reasons for EOS include abnormal power supply caused by incorrect power operation, surges caused by drastic changes in the load, lightning strikes, etc. When the circuit is impacted by EOS, a large amount of heat energy is generated due to overvoltage or overcurrent in the circuit, which will further cause internal burnout of components, damage to bonding wires, and even carbonization of the package, etc.

[0034] EOS protection can also be called EOS safeguard, which can reduce the degree of EOS impact on the circuit to improve the reliability and stability of the circuit. For example, during the design and manufacturing process of a chip or a system circuit board, an EOS protection circuit can be integrated on the chip, on the system circuit board, around the chip, or around the system circuit board. When the chip or the system circuit board is impacted by EOS, the EOS protection circuit will conduct the overvoltage or overcurrent to the ground or perform current limiting processing to protect the core circuit in the chip or the system circuit board from damage.

[0035] ESD refers to the charge transfer between two objects with different electrostatic potentials. When the static electricity accumulates to a certain extent, it will trigger a discharge phenomenon. The characteristics of ESD are high voltage, low power, small current, and short action time. The total energy released during the ESD process is limited, but it is sufficient to damage the internal structure of components, usually resulting in damage at the transistor level. ESD protection can also be called ESD safeguard, which can reduce the degree of ESD impact on the circuit. For example, ESD protection diodes, such as bilateral trigger diodes, Zener diodes, etc., can be integrated inside the chip to protect other components in the chip.

[0036] In a chip or system circuit board, I / O (input / output) ports or power ports are vulnerable to EOS impact or ESD impact. Therefore, in circuit applications, EOS ESD protection circuits are usually set up for I / O ports, power ports, and the circuits connected to them. An EOS ESD protection circuit refers to a circuit that can protect the circuit to be protected when the circuit to be protected is subjected to EOS impact and can also protect the circuit to be protected when the circuit to be protected is subjected to ESD impact.

[0037] In the field of electronic technology, capacitors are usually externally connected to I / O ports or power ports. When the externally connected capacitors are subjected to EOS impact or ESD impact at the I / O ports or power ports, they can be charged based on the high-amplitude current or voltage applied to the I / O ports or power ports to absorb part of the high-amplitude current or voltage, reduce the EOS impact or ESD impact received by the I / O ports or power ports, and achieve the protection of the I / O ports or power ports and the circuits connected to them. The EOS ESD protection circuit for protecting I / O ports or power ports may include, in addition to the capacitors externally connected to the I / O ports or power ports, ESD protection diodes located on the chip or integrated circuit board.

[0038] See Figure 1 , which shows a schematic structural diagram of an EOS ESD protection circuit provided by the related art. The EOS ESD protection circuit includes diode D0, diode D1, diode D2, capacitor C1, capacitor C2, a power port connected to the power supply voltage VDD, a ground terminal GND (Ground), and an I / O port. The circuit to be protected by the EOS ESD protection circuit includes the I / O port, the power port, and the circuits connected to them (not shown in the figure).

[0039] When the protected circuit is operating normally, the voltages of the I / O port and the power supply port are within a reasonable range, and diodes D0, D1, and D2 are all in the reverse cut-off state. At this time, the current will not pass through the branch including the diodes. The protected circuit operates according to its original functional design through normal signals and paths. Capacitors C1 and C2 in the EOS ESD protection circuit play conventional roles such as stabilizing voltage and filtering, maintaining the stable operation of the protected circuit.

[0040] When the power supply port is subjected to an EOS impact or an ESD impact, the voltage at the power supply port rises rapidly and discharges to capacitor C2 through path 2. A large amount of electrical energy is absorbed by capacitor C2, reducing the voltage at the power supply port. The ability of a capacitor to absorb electrical energy is related to the capacitance value of the capacitor. The larger the capacitance value of the capacitor, the stronger the ability to absorb electrical energy. Usually, the capacitance value of capacitor C2 is relatively large, generally on the order of 10 μF (microfarad), so the EOS ESD protection circuit generally has a relatively strong protection ability for the power supply port.

[0041] When the I / O port is subjected to an EOS impact or an ESD impact, the EOS ESD protection circuit can protect the I / O port in two ways. Method 1: Absorb electrical energy through capacitor C1; Method 2: Discharge to capacitor C2 through path 1, that is, the current passes through diode D0 and the power supply port to capacitor C2, and capacitor C2 absorbs the electrical energy of the current. On the system circuit board, the capacitance value of capacitor C1 is usually on the order of 1 μF, which is smaller than the capacitance value of capacitor C2 and has a weaker ability to absorb electrical energy. Therefore, a large amount of current will discharge to capacitor C2 through diode D0. In this case, due to the excessive voltage amplitude at the I / O port and the excessive current flowing through diode D0 to capacitor C2, a higher requirement is imposed on the forward overcurrent capacity of diode D0.

[0042] The forward overcurrent capacity of a diode refers to the ability of the diode to transmit a current exceeding the rated forward current amplitude in the forward-biased state without permanent damage. The magnitude of the forward overcurrent capacity of a diode is positively correlated with the area of the PN (Positive-Negative) junction of the diode, that is, the larger the area of the PN junction of the diode, the greater the forward overcurrent capacity of the diode, the longer the time the diode can transmit a current exceeding the rated forward current amplitude, and the larger the amplitude of the forward current that can be transmitted without permanent damage. Therefore, in related technologies, if the requirement for the forward overcurrent capacity of diode D0 is greater, the area of the PN junction of diode D0 is larger, resulting in a larger layout area occupied by diode D0.

[0043] In addition, in Figure 1In the shown circuit, during the charging process of capacitor C2, that is, during the process of capacitor C2 absorbing electrical energy, the voltage at the high-potential end of capacitor C2 (the potential end connected to the power supply port) increases. During the process of diode D0 transmitting current to capacitor C2, diode D0 is in a forward-biased state. Therefore, the amplitude of the voltage between the anode (the electrode connected to the I / O port) and the cathode (the electrode connected to the power supply port) of diode D0 is the forward voltage drop of diode D0. Due to the connectivity of the circuit, the voltage at the high-potential end of capacitor C1 will be jointly affected by the forward voltage drop of diode D0 and the voltage change at the high-potential end of capacitor C2. Since capacitor C1 is connected to the I / O port, it will participate in the transfer and redistribution of charges during this process, resulting in the voltage of capacitor C1 being jointly determined by the forward voltage drop of diode D0 and the increase in the voltage of capacitor C2.

[0044] As the voltage of capacitor C1 increases, the voltage of the I / O port also increases accordingly. Since the cathode of diode D1 is connected to the I / O port and the anode of diode D1 is grounded, when the voltage of the I / O port exceeds the reverse breakdown voltage of diode D1, diode D1 will be reverse-biased. The magnitude of the reverse breakdown voltage of a diode is proportional to the area of the PN junction of the diode. Therefore, in related technologies, the reverse breakdown voltage of diode D1 is usually increased by increasing the area of diode D1 to improve the voltage withstand capacity of diode D1.

[0045] In actual usage scenarios, it is usually required that the EOS ESD protection circuit occupies a relatively small layout area, and there are often EOS ESD level requirements for the EOS ESD protection circuit set for the I / O port and the connected circuit. For example, the level requirement is 20 A (Ampere), which means that the EOS ESD protection circuit needs to have the ability to protect against the impact of EOS current or ESD current less than or equal to 20 A. Therefore, when the sizes of the individual diodes in the EOS ESD protection circuit are small, although the requirement for the layout area can be met, once the I / O port is subjected to a strong EOS impact or ESD impact, it may cause the individual diodes in the EOS ESD protection circuit to be broken down or burned out, thus seriously affecting the normal operation and stability of the chip or integrated circuit board.

[0046] The embodiment of the present application provides a protection circuit that can achieve a balance between the layout area and the protection ability of the protection circuit and improve the protection ability of the protection circuit. The protection circuit can be a circuit that can reduce the degree of various impacts received by the circuit to be protected. For example, the protection circuit can be an EOS ESD circuit to reduce the degree of EOS impact or ESD impact received by the circuit to be protected.

[0047] See Figure 2, which shows a schematic structural diagram of a protection circuit provided by an embodiment of the present application. The protection circuit includes a first protection sub-circuit 11 and a second protection sub-circuit 12. The first ends of the first protection sub-circuit 11 and the second protection sub-circuit 12 are both connected to the input / output port of the circuit to be protected, and the second ends of the first protection sub-circuit 11 and the second protection sub-circuit 12 are both grounded (GND). Optionally, when the voltage at the input / output port is higher than the voltage of GND, the first end is the high-potential end and the second end is the low-potential end. When the voltage at the input / output port is lower than the voltage of GND, the first end is the low-potential end and the second end is the high-potential end.

[0048] The first protection sub-circuit 11 is configured to perform a first charging process under the action of a first electrical signal output from the input / output port, and the amplitude of the first electrical signal is higher than a first amplitude threshold; the second protection sub-circuit 12 is configured to generate a second electrical signal under the action of the first electrical signal; the first protection sub-circuit 11 is further configured to perform a second charging process under the action of the second electrical signal.

[0049] Wherein, the first amplitude threshold is the maximum amplitude value of the electrical signal output from the input / output port to the circuit to be protected or the protection circuit when the circuit to be protected is not subject to various impacts, or the maximum amplitude value of the electrical signal that the circuit to be protected can withstand output from the input / output port. Therefore, when the amplitude of the first electrical signal output from the input / output port is higher than the first amplitude threshold, it means that the input / output port has been impacted, such as being impacted by EOS or ESD, etc., resulting in an increase in the amplitude of the electrical signal output from the input / output port. In this case, the protection circuit will perform protection based on the first electrical signal, thereby reducing the amplitude of the electrical signal transmitted to the circuit to be protected through the input / output port, or reducing the electrical energy transmitted to the circuit to be protected, so as to achieve the protection of the circuit to be protected.

[0050] The first protection sub-circuit 11 can reduce the amplitude of the electrical signal transmitted to the circuit to be protected through the charging process. The first protection sub-circuit 11 performing the first charging process means that the first protection sub-circuit 11 absorbs the first electrical signal, or absorbs and stores the electrical energy carried or transmitted by the first electrical signal. Storing the electrical energy carried or transmitted by the first electrical signal through the first protection sub-circuit 11 can reduce the electrical energy transmitted to the circuit to be protected.

[0051] Exemplarily, refer to Figure 3Schematic diagram of a first protection sub-circuit 11 provided by an embodiment of the present application. The first protection sub-circuit 11 may include a first capacitor 111. One end of the first capacitor 111 is connected to the input / output port, and the other end of the first capacitor 111 is grounded. The number of the first capacitors 111 may be one or more. If the number of the first capacitors 111 is multiple, the multiple first capacitors 111 may be connected in series or in parallel in sequence, or some of the multiple first capacitors 111 are connected in series and then connected in parallel with other first capacitors 111, etc. The embodiment of the present application does not limit the connection manner of the multiple first capacitors 111.

[0052] A capacitor has the ability to absorb and store electrical energy. Therefore, the first capacitor 111 in the first protection sub-circuit 11 can absorb and store the electrical energy transmitted or carried by the first electrical signal. The principle of the first capacitor 111 absorbing and storing the electrical energy transmitted or carried by the first electrical signal is as follows: When under the action of the first electrical signal, the potential of the input / output port is higher than the potential of the ground terminal (usually 0), a potential difference is formed across the two ends of the first capacitor 111. The potential difference will drive the charge to move directionally. Positive charges will gradually accumulate on the capacitor plate connected to the high-potential end in the first capacitor 111, and electrons (or negative charges) will gradually accumulate on the capacitor plate connected to the low-potential end in the first capacitor 111. As the charge continuously moves and accumulates, the two capacitor plates of the first capacitor 111 are respectively charged with equal amounts of positive and negative charges, forming an electric field, and the first capacitor 111 performs the first charging process. As the first capacitor 111 performs the first charging process, the charge on the capacitor plates of the first capacitor 111 increases, and the electrical energy stored in the electric field also continuously increases, and the voltage (i.e., potential difference) across the two ends of the first capacitor 111 continuously rises. Correspondingly, the more electrical energy is stored in the first capacitor 111, the less electrical energy carried by the electrical signal transmitted to the protected circuit.

[0053] In a possible implementation manner, the protected circuit is located on the chip, and the first protection sub-circuit 11 is located outside the chip. For example, the protection circuit and the protected circuit may be located on the same integrated circuit board. The integrated circuit board includes a chip. The protected circuit is located on the chip, while the first protection sub-circuit 11 is located outside the chip but is connected to the protected circuit through the input / output port. The first protection sub-circuit 11 being located outside the chip enables the electrical energy carried or transmitted by the first electrical signal to be absorbed by the first protection sub-circuit 11 outside the chip, further preventing high-amplitude electrical signals from entering the chip interior and reducing the possibility of the chip being damaged by high-amplitude electrical signals.

[0054] In addition to the first protection sub-circuit 11 protecting the circuit to be protected through the first charging process under the action of the first electrical signal, the second protection sub-circuit 12 also generates a second electrical signal under the action of the first electrical signal. Among them, the second electrical signal is used for the first protection sub-circuit 11 to perform further charging processing.

[0055] The manner in which the second protection sub-circuit 12 generates the second electrical signal under the action of the first electrical signal may be that, based on the first electrical signal, the device in the second protection sub-circuit 12 changes the voltage at the first end of the second protection sub-circuit 12, that is, a second electrical signal is formed at the first end.

[0056] The embodiments of the present application do not limit the structure of the second protection sub-circuit 12 and the manner or process in which the second protection sub-circuit 12 generates the second electrical signal under the action of the first electrical signal. Exemplarily, refer to Figure 4 , which shows a schematic structural diagram of a second protection sub-circuit 12 provided by an embodiment of the present application. The second protection sub-circuit 12 includes a first semiconductor device 121, a second semiconductor device 122, and a third semiconductor device 123. The first semiconductor device 121 and the second semiconductor device 122 are connected to the input-output port through a first node. The first semiconductor device 121 and the third semiconductor device 123 are also grounded, and the second semiconductor device 122 is also connected to the third semiconductor device 123.

[0057] Among them, the second semiconductor device 122 is in a forward conduction state under the action of the first electrical signal; the third semiconductor device 123 and the first semiconductor device 121 are in a reverse cut-off state under the action of the first electrical signal; under the combined action of the first semiconductor device 121, the second semiconductor device 122, the third semiconductor device 123, and the first electrical signal, a second electrical signal is formed at the first node.

[0058] Refer to Figure 4 , the input-output port is connected to the first end of the second protection sub-circuit 12. The first end is the potential end corresponding to the first node. The first electrical signal output by the input-output port is transmitted to the first semiconductor device 121 and the second semiconductor device 122 through the first node.

[0059] When the input-output port outputs the first electrical signal, the cut-off condition of the first semiconductor device 121 is satisfied. The first semiconductor device 121 is in a reverse cut-off state, and the first semiconductor device 121 exhibits a high impedance state. Only a very small part of the current can flow through the first semiconductor device 121 to the ground. Therefore, under the action of the first electrical signal, the current flowing through the first node increases, and the current flowing through the branch where the first semiconductor device 121 is located raises the voltage at the first node under the action of the first semiconductor device 121 in the high impedance state.

[0060] Among them, the cut-off condition of the first semiconductor device 121 is related to the type of the first semiconductor device 121. For example, if the first semiconductor device 121 is a diode, the cut-off condition of the first semiconductor device 121 is that the voltage of the anode of the first semiconductor device 121 is lower than the cathode voltage. Another example is that if the first semiconductor device 121 is an NMOS transistor (N-channel Metal-Oxide-Semiconductor Field-Effect Transistor), the cut-off condition of the first semiconductor device 121 is that the gate-source voltage is less than the conduction threshold voltage of the first semiconductor.

[0061] The amplitude of the first electrical signal is higher than the first amplitude threshold, the conduction condition of the second semiconductor device 122 is satisfied, the second semiconductor device 122 is in the forward conduction state, and the current generated under the action of the first electrical signal and transmitted to the second semiconductor device 122 flows through the second semiconductor device 122 to the third semiconductor device 123.

[0062] Among them, the conduction condition of the second semiconductor device 122 is related to the type of the second semiconductor device 122. For example, if the second semiconductor device 122 is a diode, the conduction condition of the second semiconductor device 122 is that the voltage of the anode of the second semiconductor device 122 is higher than the cathode voltage. Another example is that if the second semiconductor device 122 is an NMOS transistor, the conduction condition of the second semiconductor device 122 is that the gate-source voltage is greater than the conduction threshold voltage of the second semiconductor device 122. Still another example is that if the second semiconductor device 122 is a PMOS transistor (P-channel Metal-Oxide-Semiconductor Field-Effect Transistor), the conduction condition of the second semiconductor device 122 is that the gate-source voltage is less than the conduction threshold voltage of the second semiconductor device 122.

[0063] Under the action of the first electrical signal, the cut-off condition of the third semiconductor device 123 is satisfied, the third semiconductor device 123 is in the reverse cut-off state, which also shows a high impedance state. The current flowing through the second semiconductor device 122 to the third semiconductor device 123 cannot be transmitted to the ground through the third semiconductor device 123, or only a very small part of the current can be transmitted to the ground through the third semiconductor device 123. Therefore, the current flowing to the third semiconductor device 123, under the action of the third semiconductor device 123 in the high impedance state, raises the voltage applied across the second semiconductor device 122. Since the high-potential end of the second semiconductor device 122 is connected to the first node, the voltage at the first node is further raised.

[0064] Thus, under the action of the first semiconductor device 121, the second semiconductor device 122, the third semiconductor device 123, and the first electrical signal, the voltage at the first node is elevated, that is, a second electrical signal is formed at the first node.

[0065] In a possible implementation manner, the reverse breakdown thresholds of the first semiconductor device 121 and the third semiconductor device 123 are greater than the second amplitude threshold, the second amplitude threshold is greater than the first amplitude threshold, the amplitude of the second electrical signal is less than or equal to the second amplitude threshold, the second amplitude threshold is related to the protection level of the protection circuit, and the amplitude of the second electrical signal is related to the resistance values of the first semiconductor device 121 and the third semiconductor device 123 in the reverse cut-off state.

[0066] The protection level of the protection circuit is a protection level set based on experience or user requirements, such as the 20A level or the 20V level, etc. When the protection level is the 20A level, it means that the protection circuit needs to have the ability to protect against the impact of EOS current or ESD current less than or equal to 20A, so the second amplitude threshold can be set to a current amplitude higher than or equal to 20A. Correspondingly, when the protection level is 20V, it means that the protection circuit needs to have the ability to protect against the impact of EOS voltage or ESD voltage less than or equal to 20V, so the second amplitude threshold can be set to a voltage amplitude higher than or equal to 20V.

[0067] Select semiconductor devices with reverse breakdown thresholds greater than the second amplitude threshold as the first semiconductor device 121 and the third semiconductor device 123, so that when the amplitude of the first electrical signal output at the input-output port is less than or equal to the second amplitude threshold, the first semiconductor device 121 and the third semiconductor device 123 will not be reversely broken down, and cooperate with the second semiconductor device 122 to generate a second electrical signal.

[0068] In the embodiment of the present application, by increasing the reverse breakdown thresholds of the first semiconductor device 121 and the third semiconductor device 123 in the second protection sub-circuit 12, the possibility of the devices in the second protection sub-circuit 12 being broken down or damaged is reduced, so that the second protection sub-circuit 12 can withstand electrical signals with a larger amplitude, thereby improving the protection ability of the second protection sub-circuit 12. For example, the reverse breakdown thresholds of the first semiconductor device 121 and the third semiconductor device 123 can be increased by changing the material of the first semiconductor device 121 and the third semiconductor device 123 or the impurity concentration on both sides of the PN junction.

[0069] The second electrical signal is generated at the first node of the second protection sub-circuit 12. The first node belongs to the first end. The first end of the second protection sub-circuit 12 is connected to the first end of the first protection sub-circuit 11 through the input / output port. Therefore, the electrical signal at the first end of the first protection sub-circuit 11 is also raised, that is, the second electrical signal has an impact on the first protection sub-circuit 11.

[0070] So that under the action of the second electrical signal, the first protection sub-circuit 11 is further configured to perform a second charging process. The principle and process of the first protection sub-circuit 11 performing the second charging process under the action of the second electrical signal are similar to the principle and process of the first protection sub-circuit 11 performing the first charging process under the action of the first electrical signal, and will not be elaborated here. Since under the action of the second electrical signal, the voltage at the first end of the first protection sub-circuit 11 is raised, thereby increasing the power absorption capacity of the first protection sub-circuit 11 and improving the protection ability of the first protection sub-circuit 11.

[0071] In summary, when the amplitude of the first electrical signal output by the input / output port is higher than the first amplitude threshold, it represents that the input / output port has received an EOS impact or an ESD impact. Therefore, under the action of the first electrical signal, the first protection sub-circuit 11 performs a first charging process to absorb the first electrical signal and reduce the amplitude of the electrical signal transmitted to the protected circuit through the input / output port, or in other words, reduce the electrical energy transmitted to the protected circuit. In addition, under the action of the first electrical signal, the second protection sub-circuit 12 generates a second electrical signal to raise the potential of the first end of the first protection sub-circuit 11. Since the devices in the second protection sub-circuit 12 are not easily broken down by the first electrical signal, the protection ability of the protection circuit is improved. And, under the action of the second electrical signal, the first protection sub-circuit 11 performs a second charging process to achieve further absorption of the electrical signal, thereby further preventing high-amplitude electrical signals from damaging the protected circuit and improving the protection ability of the protection circuit.

[0072] Both the above-mentioned first protection sub-circuit 11 and second protection sub-circuit 12 are circuits for protecting the input / output port of the protected circuit. The protection circuit provided by the embodiments of the present application may further include a circuit for protecting the power port of the protected circuit. In a possible implementation manner, referring to Figure 5 , the protection circuit provided by the embodiments of the present application further includes a third protection sub-circuit 13. The third protection sub-circuit 13 is used to protect the power port of the protected circuit. The third protection sub-circuit 13 is connected to the power port of the protected circuit. The second protection sub-circuit 12 is connected to the third protection sub-circuit 13 through a second node and grounded.

[0073] The third protection sub-circuit 13 is configured to perform a third charging process under the action of a third electrical signal output from the power supply port, and transmit the third electrical signal to the ground. The amplitude of the third electrical signal is higher than the first amplitude threshold.

[0074] When the amplitude of the third electrical signal is higher than the first amplitude threshold, it represents that the power supply port has been impacted. In this case, the third protection sub-circuit 13 can absorb part of the electrical energy transmitted or carried by the third electrical signal through the third charging process, reducing the electrical energy transmitted to the protected circuit. The third protection sub-circuit 13 can also transmit the third electrical signal to the ground, further reducing the electrical energy transmitted to the protected circuit.

[0075] Exemplarily, referring to Figure 6 , a schematic structural diagram of a third protection sub-circuit 13 provided by an embodiment of the present application is shown. The third protection sub-circuit 13 includes a second capacitor 131 and a fourth semiconductor device 132. One end of the fourth semiconductor device 132 and the second capacitor 131 are both connected to the power supply port, and the other end of the fourth semiconductor device 132 and the second capacitor 131 are both grounded.

[0076] The second capacitor 131 is configured to perform a third charging process under the action of a first sub-signal in the third electrical signal. When, under the action of the third electrical signal, the amplitude of the end of the second capacitor 131 connected to the power supply port is higher than the amplitude of the end grounded, a potential difference is formed across the second capacitor 131. The potential difference will drive the charges to move directionally, forming an electric field inside the second capacitor 131. As the second capacitor 131 performs the third charging process and the charges on the capacitor plates of the second capacitor 131 increase, the voltage across the second capacitor 131 continuously rises, and the electrical energy stored in the electric field also continuously increases. Correspondingly, the more electrical energy is stored in the second capacitor 131, the less electrical energy carried by the electrical signal transmitted to the protected circuit.

[0077] Since the electrical energy stored by the second capacitor 131 through the third charging process is limited, the second capacitor 131 can only perform the third charging process based on the first sub-signal in the third electrical signal, that is, the second capacitor 131 can only absorb and store part of the electrical energy transmitted or carried by the third electrical signal.

[0078] The fourth semiconductor device 132 is used to transmit the second sub-signal in the third electrical signal to the ground. The second capacitor 131 performs the third charging process, which takes a certain amount of time. Therefore, the voltage of the power supply port gradually decreases as the third charging process progresses. If only the second capacitor 131 is used to perform the third charging process on the third electrical signal, there is still a possibility that the high-amplitude electrical signal output from the power supply port is transmitted to the protected circuit. Therefore, the fourth semiconductor device 132 transmits the second sub-signal to the ground. The second sub-signal is an electrical signal whose electrical energy cannot be absorbed by the second capacitor 131, reducing the electrical energy carried or transmitted by the electrical signal transmitted to the protected circuit. Since the speed and completion time of the fourth semiconductor device 132 transmitting the second sub-signal to the ground may be different from the speed and completion time of the second capacitor 131 performing the third charging process under the action of the first sub-signal, there is an overlapping part in the existence time of the first sub-signal and the second sub-signal, but they may not be exactly the same.

[0079] Optionally, the fourth semiconductor device 132 may transmit the second sub-signal to the ground when in a reverse breakdown state. Exemplarily, if the fourth semiconductor device 132 is a diode, the anode of the fourth semiconductor device 132 is grounded, and the cathode of the fourth semiconductor device 132 is connected to the power supply port. Therefore, under the action of the second sub-signal, the voltage of the cathode of the fourth semiconductor device 132 is higher than that of the anode. Since the amplitude of the third electrical signal is higher than the first amplitude threshold, if the first amplitude threshold is higher than the reverse breakdown threshold of the fourth semiconductor device 132, the fourth semiconductor device 132 is reverse broken down and conducts in reverse, quickly transmitting the second sub-signal to the ground.

[0080] The second capacitor 131 is further configured to transmit a fourth electrical signal generated based on the first sub-signal to the fourth semiconductor device 132 after completing the third charging process. After the second capacitor 131 completes the third charging process, it can release the electrical energy stored during the third charging process. Therefore, the second capacitor 131 can transmit the fourth electrical signal generated based on the first sub-signal to the fourth semiconductor device 132 to realize the release of electrical energy.

[0081] The fourth semiconductor device 132 transmits the fourth electrical signal to the ground. Correspondingly, the fourth semiconductor device 132 may also transmit the fourth electrical signal to the ground when in a reverse breakdown state.

[0082] Optionally, the second capacitor 131 is located outside the chip on which the circuit to be protected is deployed, and the fourth semiconductor device 132 is located on the chip. For example, the protection circuit and the circuit to be protected may be located on the same integrated circuit board, which includes a chip, the circuit to be protected is located on the chip, and the second capacitor 131 is located outside the chip but is connected to the circuit to be protected through a power port. The second capacitor 131 being located outside the chip enables the electrical energy carried or transmitted by the third electrical signal to be absorbed outside the chip on which the circuit to be protected is deployed, reducing the possibility of the chip being damaged by high-amplitude electrical signals.

[0083] Alternatively, it may also be that the third protection sub-circuit 13 is located outside the chip on which the circuit to be protected is deployed. For example, in the case where the third protection sub-circuit 13 includes the fourth semiconductor device 132 and the second capacitor 131, both the fourth semiconductor device 132 and the second capacitor 131 are located outside the chip. Not only is electrical energy absorbed outside the chip, but the electrical energy is also transmitted to the ground through the semiconductor device outside the chip, preventing high-amplitude electrical signals from being transmitted to the circuit to be protected after the semiconductor device outside the chip is broken down, further improving the protection ability of the protection circuit.

[0084] See Figure 7 , which shows a schematic structural diagram of a protection circuit provided by an embodiment of the present application. This protection circuit can protect the circuit to be protected against EOS shock or ESD shock. Figure 7 The capacitor C1 in corresponds to the first capacitor 111 in the above-mentioned first protection sub-circuit 11, the I / O port corresponds to the input / output port of the above-mentioned circuit to be protected, the diode D8 corresponds to the first semiconductor device 121 in the above-mentioned second protection sub-circuit 12, the diode D4 corresponds to the second semiconductor device 122 above, the diode D9 corresponds to the third semiconductor device 123 above, the power port (VDD) corresponds to the power port of the above-mentioned circuit to be protected, the diode D7 corresponds to the fourth semiconductor device 132 in the above-mentioned third protection sub-circuit 13, the capacitor C2 corresponds to the second capacitor 131 above, the connection node between the diode D8 and the diode D4 is the first node, and the connection node between the diode D9 and the diode D7 is the second node.

[0085] In the case where the I / O port is subjected to EOS shock or ESD shock, the capacitor C1 performs a first charging process under the action of the first electrical signal output by the I / O port, reducing the electrical energy transmitted to the circuit to be protected.

[0086] In addition, since the cathode of diode D8 is connected to the I / O port and the anode of diode D8 is grounded, after the I / O port outputs the first electrical signal, the voltage at the cathode of diode D8 is higher than the voltage at the anode of diode D8, and diode D8 is in the reverse cut-off state, and diode D8 exhibits a high impedance state. Therefore, under the action of the first electrical signal, diode D8 raises the voltage at the first node.

[0087] Since the amplitude of the first electrical signal is higher than the first amplitude threshold, the voltage generated across diode D4 based on the first electrical signal is generally higher than the forward conduction voltage of diode D4. Therefore, under the action of the first electrical signal, diode D4 enters the forward conduction state and transmits current to diode D9.

[0088] The cathode of diode D9 is connected to the cathode of diode D4, and the anode of diode D9 is grounded. After diode D4 transmits current to diode D9, the voltage at the cathode of diode D9 is higher than the voltage at the anode of diode D9, and diode D9 is in the reverse cut-off state, and diode D9 exhibits a high impedance state. Therefore, almost all of the electrical signal transmitted to diode D9 is applied across diode D9. Combining the high resistance value of diode D9 and the action of the current flowing into diode D9, the voltage at the cathode of diode D4 is raised. Since diode D4 is in the forward bias or in the forward conduction state at this time, the voltage across diode D4 is maintained at the forward voltage drop of diode D4. The magnitude of the forward voltage drop of diode D4 is related to the material of diode D4. For example, if diode D4 is a silicon diode, the magnitude of the forward voltage drop of diode D4 is 0.6 to 0.8 V (volt); if diode D4 is a germanium diode, the forward voltage drop of diode D4 is 0.1 to 0.3 V.

[0089] Therefore, when the voltage at the cathode of diode D4 is raised, the voltage at the anode of diode D4 will also be raised accordingly, so that the voltage drop between the anode and cathode of diode D4 is maintained at the forward voltage drop. The voltage at the first node is further raised, forcing capacitor C1 to absorb more electrical energy and reducing the electrical energy transmitted to the protected circuit.

[0090] When, for example Figure 7When the power supply port (VDD) in the shown circuit is subjected to an EOS impact or an ESD impact, the power supply port (VDD) outputs a third electrical signal. Under the action of the third electrical signal, the capacitor C2 absorbs part of the electrical energy of the third electrical signal, that is, a second charging process is performed on the first sub-signal of the third electrical signal. At the same time, the diode D7 is reversely broken down under the action of the third electrical signal and transmits the second sub-signal of the third electrical signal to the ground. When the capacitor C2 is saturated and the diode D7 completes the discharge of the second sub-signal, the voltage across the capacitor C2 is higher than the anode voltage of the diode D7, and the diode D7 is reversely broken down again, continuing to discharge to the ground the fourth electrical signal generated by the electrical energy stored in the capacitor C2, reducing the voltage amplitude at the power supply port (VDD), and protecting the impact of the high-amplitude third electrical signal output by the power supply port (VDD) on the circuit to be protected.

[0091] See Figure 8 , which shows a schematic structural diagram of another protection circuit provided by an embodiment of the present application. This protection circuit can protect the circuit to be protected against EOS impact or ESD impact. This protection circuit includes a capacitor C11 and a capacitor C12 corresponding to the first capacitor 111. The capacitor C11 and the capacitor C12 are connected in parallel and are both connected to the I / O port corresponding to the above input / output port and GND. This protection circuit further includes an NMOS transistor N1 corresponding to the above first semiconductor device 121, a PMOS transistor P2 corresponding to the above second semiconductor device 122, and an NMOS transistor N3 corresponding to the above semiconductor device 123. In addition, this protection circuit further includes a diode D7 corresponding to the above fourth semiconductor 132 and a capacitor C2 corresponding to the second capacitor 131.

[0092] When the I / O port is subjected to an EOS impact and an ESD impact, the capacitor C11 and the capacitor C12 jointly perform a first charging process under the action of the first electrical signal. The capacitor C11 and the capacitor C12 are connected in parallel, so the absorption speed of electrical energy is faster and more electrical energy is absorbed during the first charging process.

[0093] In addition, the gate of transistor N1 is connected to an additional interface, the voltage of which is less than or equal to the voltage of the I / O port when not subject to various shocks, and the voltage difference between the voltage of this interface and the voltage of the I / O port is less than the conduction threshold voltage of transistor N1, so that in the case of not being subject to EOS shock or ESD shock, transistor N1 is in the off state, or in the reverse cut-off state. The gate of transistor P2 is also connected to an additional interface, and the interface connected to the gate of transistor P2 may be the same as or different from the interface connected to the gate of transistor N1. The voltage of the interface connected to the gate of transistor P2 is greater than the voltage of the I / O port when not subject to various shocks, and makes the gate-source voltage of transistor P2 greater than the conduction threshold voltage of transistor P2. Transistor P2 is in the reverse cut-off state when not subject to EOS shock or ESD shock.

[0094] When the I / O port is subject to ESD shock or EOS shock, under the action of the first electrical signal, the voltage at the first node is rapidly raised, the gate-source voltage of transistor N1 becomes a negative voltage, and transistor N1 is in the reverse cut-off state, presenting a high impedance state. Combining with the current flowing to transistor N1 under the action of the first electrical signal, the transistor N1 in the high impedance state raises the voltage at the first node.

[0095] The source of transistor P2 is connected to transistor N3. Since both the source and the gate of transistor N3 are grounded, the gate-source voltage of transistor N3 is about 0, which is less than the conduction threshold voltage of transistor N3, and transistor N3 is in the reverse cut-off state. Therefore, when not subject to EOS shock or ESD shock, the voltage at the source of transistor P2 is extremely low. After the I / O port is subject to EOS shock or ESD shock, at the moment when the first electrical signal with an amplitude higher than the first amplitude threshold is output, the drain voltage of transistor P2 is rapidly raised, and the gate-source voltage of transistor P2 remains unchanged. Since the source and drain materials of transistor P2 are heavily doped P-type materials and the substrate material of transistor P2 is N-type material, a PN junction will be formed between the drain and the substrate of transistor P2, and a PN junction will also be formed between the source and the substrate of transistor P2. These PN junctions form the drain / body (D / B) parasitic diode of transistor P2, that is, Figure 8 the diode D21 shown in. The drain of transistor P2 is equivalent to the anode of diode D21, and the source of transistor P2 is equivalent to the cathode of diode D21. When the I / O port outputs the first electrical signal, the voltage at the drain of transistor P2 rises, making diode D21 in the forward conduction state, that is, the drain and the source of transistor P2 are conducting. Under the action of the first electrical signal, a current is generated at transistor P2, and the current flows through the drain and the source of transistor P2 and flows to transistor N3.

[0096] Since the transistor N3 is always in the reverse cut-off state, the voltage at the first node is raised under the combined action of the transistor N1, the transistor P2, the transistor N3, and the first electrical signal, and a second electrical signal is formed at the first node. The amplitude of the second electrical signal is higher than that of the first electrical signal, causing the voltage at the I / O port to be raised. Under the action of the second electrical signal, the absorption capacities of the capacitors C11 and C12 increase, absorbing more electrical energy and effectively reducing the electrical energy transmitted to the protected circuit.

[0097] When the power supply port (VDD) in the circuit as Figure 8 shown is subjected to an EOS impact or an ESD impact, the power supply port (VDD) outputs a third electrical signal. Under the action of the third electrical signal, the capacitor C2 absorbs part of the electrical energy of the third electrical signal, that is, a second charging process is performed on the first sub-signal of the third electrical signal. At the same time, the diode D7 is reversely broken down under the action of the third electrical signal and transmits the second sub-signal of the third electrical signal to the ground. When the capacitor C2 is saturated and the diode D7 has completed the discharge of the second sub-signal, the voltage across the capacitor C2 is higher than the anode voltage of the diode D7, and the diode D7 is reversely broken down again, continuing to discharge to the ground the fourth electrical signal generated by the electrical energy stored in the capacitor C2, reducing the voltage amplitude at the power supply port (VDD) and protecting the impact of the high-amplitude third electrical signal output by the power supply port (VDD) on the protected circuit.

[0098] As Figure 7 or Figure 8 shown, the protection circuit, compared with the EOS ESD protection circuit as Figure 1 shown provided by the related art, adds a floating EOS ESD discharge path, that is, Figure 7 the path 11 from the diode D4 to the diode D9 in Figure 8 or the path 12 from the transistor P2 to the transistor N3 in

[0099] At the same time, improve Figure 7The reverse breakdown thresholds of diode D8 and diode D9. When an EOS ESD event occurs at the I / O port, that is, when it is subjected to EOS impact or ESD impact, due to the relatively high trigger voltage of the floating EOS ESD discharge path, that is, the reverse breakdown thresholds of diode D4 and diode D9 are both relatively high, making it impossible for a high-amplitude current to be transmitted along path 11, increasing the difficulty for the current generated by EOS impact or ESD impact to penetrate each diode and enter the protected circuit, raising the voltage at the high-potential end of capacitor C1, forcing the electrical signal to be absorbed by capacitor C1, reducing the requirement for the forward-bias overcurrent capacity of diode D4, thereby improving the EOS ESD level of the I / O port.

[0100] In the related art, to achieve the same protection level against EOS ESD for the I / O port, a relatively strong overcurrent capacity of diode D0 is required, so the area of diode D0 needed is relatively large, while Figure 7 in the protection circuit shown, the requirement for the forward-bias overcurrent capacity of diode D4 is greatly reduced (such as reduced to the 2A level), so even on the basis of adding diode D9 device, the purpose of saving area can be achieved.

[0101] Correspondingly, increasing Figure 8 the reverse breakdown thresholds of transistor N1, transistor P2, and transistor N3 can also achieve the effect of forcing capacitors C11 and C12 to absorb more electrical energy, reducing the possibility of transistors N1 and N3 being reverse broken down, and improving the protection level of the protection circuit.

[0102] In an exemplary embodiment, an electronic device is provided. The electronic device includes a protection circuit and a protected circuit. The protection circuit includes a first protection sub-circuit and a second protection sub-circuit. The first ends of the first protection sub-circuit and the second protection sub-circuit are connected to the input / output port of the protected circuit, and the second ends of the first protection sub-circuit and the second protection sub-circuit are both grounded; the first protection sub-circuit is configured to perform a first charging process under the action of a first electrical signal output from the input / output port, and the amplitude of the first electrical signal is higher than a first amplitude threshold; the second protection sub-circuit is configured to generate a second electrical signal under the action of the first electrical signal; the first protection sub-circuit is further configured to perform a second charging process under the action of the second electrical signal.

[0103] In a possible implementation manner, the first protection sub-circuit includes a first capacitor, one end of the first capacitor is connected to the input / output port, and the other end of the first capacitor is grounded.

[0104] In a possible implementation manner, the protected circuit is located on a chip in the electronic device, and the first protection sub-circuit is located outside the chip.

[0105] In a possible implementation, the second protection sub-circuit includes a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device and the second semiconductor device are connected to the input / output port through a first node. The first semiconductor device and the third semiconductor device are also grounded, and the second semiconductor device is also connected to the third semiconductor device. The second semiconductor device is in a forward conduction state under the action of a first electrical signal. The third semiconductor device and the first semiconductor device are in a reverse cut-off state under the action of the first electrical signal. Under the combined action of the first semiconductor device, the second semiconductor device, the third semiconductor device, and the first electrical signal, a second electrical signal is formed at the first node.

[0106] In a possible implementation, the reverse breakdown thresholds of the first semiconductor device and the third semiconductor device are greater than a second amplitude threshold, the second amplitude threshold is greater than a first amplitude threshold, the amplitude of the second electrical signal is less than or equal to the second amplitude threshold, the second amplitude threshold is related to the protection level of the protection circuit, and the amplitude of the second electrical signal is related to the resistance values of the first semiconductor device and the third semiconductor device in the reverse cut-off state.

[0107] In a possible implementation, the protection circuit further includes a third protection sub-circuit. The third protection sub-circuit is connected to the power supply port of the circuit to be protected. The second protection sub-circuit is connected to the third protection sub-circuit through a second node and is grounded. The third protection sub-circuit is configured to perform a third charging process under the action of a third electrical signal output from the power supply port and transmit the third electrical signal to the ground. The amplitude of the third electrical signal is higher than the first amplitude threshold.

[0108] In a possible implementation, the third protection sub-circuit includes a second capacitor and a fourth semiconductor device. One end of the fourth semiconductor device and the second capacitor are both connected to the power supply port, and the other end of the fourth semiconductor device and the second capacitor are both grounded. The second capacitor is configured to perform a third charging process under the action of a first sub-signal in the third electrical signal output from the power supply port. The fourth semiconductor device is configured to transmit a second sub-signal in the third electrical signal to the ground. The second capacitor is further configured to transmit a fourth electrical signal generated based on the first sub-signal to the fourth semiconductor device after completing the third charging process. The fourth semiconductor device is further configured to transmit the fourth electrical signal to the ground.

[0109] In a possible implementation, the second capacitor is located outside the chip on which the circuit to be protected is deployed, and the fourth semiconductor device is located on the chip.

[0110] It should be noted that the terms "first", "second", etc. (if any) in the description and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of this application described here can be implemented in an order different from those illustrated or described here. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. On the contrary, they are merely examples of devices and methods consistent with some aspects of this application as detailed in the appended claims.

[0111] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with the relevant laws, regulations and standards of relevant countries and regions. For example, the electrical signals involved in this application are obtained under full authorization.

[0112] It should be understood that the term "a plurality" as mentioned herein refers to two or more. "And / or" describes the association relationship of associated objects and indicates that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0113] The above are only exemplary embodiments of this application and are not intended to limit this application. Any modifications, equivalent replacements, improvements, etc. made within the principles of this application shall be included within the protection scope of this application.

Claims

1. A protection circuit, characterized in that, The protection circuit includes a first protection sub - circuit and a second protection sub - circuit. The first ends of the first protection sub - circuit and the second protection sub - circuit are both connected to the input - output port of the circuit to be protected, and the second ends of the first protection sub - circuit and the second protection sub - circuit are both grounded; The first protection sub - circuit is used to perform a first charging process under the action of a first electrical signal output from the input - output port, and the amplitude of the first electrical signal is higher than a first amplitude threshold; The second protection sub - circuit is used to generate a second electrical signal under the action of the first electrical signal; The first protection sub - circuit is further used to perform a second charging process under the action of the second electrical signal.

2. The protection circuit according to claim 1, characterized in that The first protection sub - circuit includes a first capacitor. One end of the first capacitor is connected to the input - output port, and the other end of the first capacitor is grounded.

3. The protection circuit according to claim 1 or 2, characterized in that, The second protection sub - circuit includes a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device and the second semiconductor device are connected to the input - output port through a first node. The first semiconductor device and the third semiconductor device are also grounded, and the second semiconductor device is also connected to the third semiconductor device; The second semiconductor device is in a forward - conducting state under the action of the first electrical signal; The third semiconductor device and the first semiconductor device are in a reverse - cut - off state under the action of the first electrical signal; Under the combined action of the first semiconductor device, the second semiconductor device, the third semiconductor device, and the first electrical signal, the second electrical signal is formed at the first node.

4. The protection circuit according to claim 3, wherein The reverse - breakdown thresholds of the first semiconductor device and the third semiconductor device are greater than a second amplitude threshold. The second amplitude threshold is greater than the first amplitude threshold. The amplitude of the second electrical signal is less than or equal to the second amplitude threshold. The second amplitude threshold is related to the protection level of the protection circuit, and the amplitude of the second electrical signal is related to the resistance value in the reverse - cut - off state of the first semiconductor device and the third semiconductor device.

5. The protection circuit according to any one of claims 1-4, characterized in that, The protection circuit further includes a third protection sub - circuit. The third protection sub - circuit is connected to the power - supply port of the circuit to be protected. The second protection sub - circuit and the third protection sub - circuit are connected through a second node and grounded; The third protection sub - circuit is used to perform a third charging process under the action of a third electrical signal output from the power - supply port and transmit the third electrical signal to the ground. The amplitude of the third electrical signal is higher than the first amplitude threshold.

6. The protection circuit according to claim 5, characterized in that, The third protection sub - circuit includes a second capacitor and a fourth semiconductor device. One ends of the fourth semiconductor device and the second capacitor are both connected to the power - supply port, and the other ends of the fourth semiconductor device and the second capacitor are both grounded; The second capacitor is used to perform a third charging process under the action of a first sub - signal in the third electrical signal output from the power - supply port; The fourth semiconductor device is used to transmit a second sub - signal in the third electrical signal to the ground; The second capacitor is further configured to transmit a fourth electrical signal generated based on the first sub-signal to the fourth semiconductor device after the third charging process is completed; The fourth semiconductor device is further configured to transmit the fourth electrical signal to the ground.

7. The protection circuit according to claim 6, wherein The second capacitor is located outside the chip on which the protected circuit is deployed, and the fourth semiconductor device is located on the chip.

8. The protection circuit according to claim 1 or 2, characterized in that, The protected circuit is located on the chip, and the first protection sub-circuit is located outside the chip.

9. An electronic device, characterized in that, The electronic device includes a protection circuit and a protected circuit. The protection circuit includes a first protection sub-circuit and a second protection sub-circuit. The first ends of the first protection sub-circuit and the second protection sub-circuit are both connected to the input / output port of the protected circuit, and the second ends of the first protection sub-circuit and the second protection sub-circuit are both grounded; The first protection sub-circuit is configured to perform a first charging process under the action of a first electrical signal output from the input / output port, and the amplitude of the first electrical signal is higher than a first amplitude threshold; The second protection sub-circuit is configured to generate a second electrical signal under the action of the first electrical signal; The first protection sub-circuit is further configured to perform a second charging process under the action of the second electrical signal.

10. The electronic device according to claim 9, characterized in that, The protection circuit further includes a third protection sub-circuit. The third protection sub-circuit is connected to the power supply port of the protected circuit. The second protection sub-circuit is connected to the third protection sub-circuit through a second node and grounded; The third protection sub-circuit is configured to perform a third charging process under the action of a third electrical signal output from the power supply port and transmit the third electrical signal to the ground. The amplitude of the third electrical signal is higher than the first amplitude threshold.

Images