Static random access memory and forming method thereof
By forming germanium silicon stress layers and applying stress etch stop layers to balance NMOS and PMOS transistors, the method addresses performance disparities in SRAM bit cells, enhancing drive current and reducing mismatch in static random access memory.
Patent Information
- Application Number
- CN202510311525.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-17
- Publication Date
- 2025-07-15
AI Technical Summary
In 40-nanometer static random access memory, the speed difference between NMOS devices and PMOS devices leads to poor performance of PMOS devices, affecting the performance, power and area competitiveness of the process platform.
By forming a silicon germanium stress layer in the substrates on both sides of the PMOS device and covering the compressive stress etch stop layer on the PMOS device, the tensile stress etch stop layer is covered on the NMOS device, and compressive stress and tensile stress are applied to improve device performance.
The driving current ratio between NMOS devices and PMOS devices is improved, the transistor parameter mismatch in the memory cell is reduced, and the performance of PMOS devices is improved.
Smart Images
Figure CN120321939A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit technology, and particularly relates to a static random access memory and a method for forming the same. Background Art
[0002] Some products of the 40-nanometer node HV (High Voltage) process platform need to use a large area of static random access memory (SRAM). The size of the bit cell in the SRAM directly affects the PPA (performance, power, area) competitiveness of the process platform. Therefore, a shrinked SRAM design is often required. Due to the shrinked SRAM design, there are high requirements for the manufacturing process.
[0003] When the size of the bit cell of the 40-nanometer node high-voltage device static random access memory is shrunk to 190 (0.0199μm 2 ) and even less than 163 (0.0163μm 2 ) in the future, it is already close to the size of the static random access memory with a bit cell size of 155 (0.0155μm 2 ) at the 28-nanometer node. Compared with the 28-nanometer node, the speed difference between NMOS devices and PMOS devices on the 40-nanometer node platform is very large, resulting in poor performance of PMOS devices. Summary of the Invention
[0004] The purpose of the present invention is to provide a static random access memory and a method for forming the same, so as to solve the problem of poor performance of PMOS devices caused by the large speed difference between NMOS devices and PMOS devices when the size of the bit cell of the static random access memory is shrunk.
[0005] To solve the above technical problems, the present invention provides a method for forming a static random access memory, including:
[0006] Providing a substrate, on which PMOS devices and NMOS devices are formed;
[0007] Performing an epitaxial growth process to form germanium-silicon stress layers in the substrate on both sides of the PMOS devices;
[0008] Forming a compressive stress etch stop layer, which covers the PMOS devices;
[0009] Forming a tensile stress etch stop layer, which covers the NMOS devices.
[0010] Optionally, the step of forming the compressive stress etch stop layer includes:
[0011] Form a compressive stress etch stop layer that covers the PMOS device and the NMOS device;
[0012] Remove the compressive stress etch stop layer on the NMOS device and retain the compressive stress etch stop layer on the PMOS device.
[0013] Optionally, the step of forming the tensile stress etch stop layer includes:
[0014] Form a tensile stress etch stop layer that covers the PMOS device and the NMOS device;
[0015] Remove the tensile stress etch stop layer on the PMOS device and retain the tensile stress etch stop layer on the NMOS device.
[0016] Optionally, the compressive stress etch stop layer and the tensile stress etch stop layer are formed by chemical vapor deposition.
[0017] Optionally, the chemical vapor deposition processes for forming the compressive stress etch stop layer and the tensile stress etch stop layer have different temperatures.
[0018] Optionally, the materials of both the compressive stress etch stop layer and the tensile stress etch stop layer are silicon nitride.
[0019] Optionally, both the PMOS device and the NMOS device include gates. After forming the germanium silicon stress layer, source regions and drain regions of the PMOS device are formed in the substrate on both sides of the gate of the PMOS device, and source regions and drain regions of the NMOS device are formed in the substrate on both sides of the gate of the NMOS device.
[0020] Optionally, after forming the germanium silicon stress layer and before forming the compressive stress etch stop layer, it further includes:
[0021] Form a metal silicide blocking layer that covers the PMOS device and the NMOS device;
[0022] Etch the metal silicide blocking layer on the gates, source regions, and drain regions of the PMOS device and the gates, source regions, and drain regions of the NMOS device to expose the top surfaces of the gates, source regions, and drain regions of the PMOS device and the gates, source regions, and drain regions of the NMOS device;
[0023] Perform a pre-cleaning process to clean the top surfaces of the gates, source regions, and drain regions of the PMOS device and the gates, source regions, and drain regions of the NMOS device;
[0024] A deposited metal layer that covers the top surfaces of the gates, source regions, and drain regions of the PMOS devices and the gates, source regions, and drain regions of the NMOS devices;
[0025] Perform an annealing process to form metal silicides on the tops of the gates, source regions, and drain regions of the PMOS devices and the gates, source regions, and drain regions of the NMOS devices.
[0026] Optionally, after the step of forming the tensile stress etch stop layer:
[0027] Perform a contact hole etching process to form contact holes on the gates, the source regions, and the drain regions of the PMOS devices and on the gates, the source regions, and the drain regions of the NMOS devices;
[0028] Perform a deposition process to form contact plugs within the contact holes, and the contact plugs are used to lead out the gates, the source regions, and the drain regions of the PMOS devices and the gates, the source regions, and the drain regions of the NMOS devices.
[0029] Based on the same inventive concept, the present invention also provides a static random access memory, which is prepared by using the formation method of the static random access memory described in any one of the above.
[0030] In the formation method of the static random access memory provided by the present invention, by first performing a germanium silicon process to form germanium silicon stress layers in the substrates on both sides of the PMOS devices; then sequentially forming a compressive stress etch stop layer and a tensile stress etch stop layer, the compressive stress etch stop layer covers the PMOS devices, and the tensile stress etch stop layer covers the NMOS devices. By first forming germanium silicon stress layers in the substrates on both sides of the PMOS devices, and then sequentially forming a compressive stress etch stop layer on the PMOS devices and a tensile stress etch stop layer on the NMOS devices, compressive stress is applied to the PMOS devices and tensile stress is applied to the NMOS devices, which improves the drive current ratio between the NMOS devices and the PMOS devices of the static random access memory, reduces the transistor parameter mismatch in the memory cells of the static random access memory, and thereby effectively improves the performance of the PMOS devices of the static random access memory. Description of the Drawings
[0031] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:
[0032] Figure 1 is a flowchart of the formation method of the static random access memory according to an embodiment of the present invention.
[0033] Figures 2 to 12 It is a schematic structural diagram corresponding to the steps of the method for forming a static random access memory according to an embodiment of the present invention.
[0034] In the drawings:
[0035] 10 - Substrate; 11 - Shallow trench isolation structure; 12a - First well region; 12b - Second well region; 13 - NMOS device; 13a - Gate dielectric layer; 13b - Gate; 13c - Isolation layer; 13d - Sidewall; 14 - PMOS device; 15a - Buffer region of PMOS device; 15b - Buffer region of NMOS device; 16 - Germanium silicon stress layer; 16a - Germanium silicon trench; 17a - Source region of PMOS device; 17b - Source region of NMOS device; 18 - Metal silicide blocking layer; 19 - Metal layer; 19a - Metal silicide; 20 - Compressive stress etch stop layer; 21 - Tensile stress etch stop layer. Detailed implementation manners
[0036] To make the objectives, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in very simplified forms and not drawn to scale, and are only used to conveniently and clearly assist in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the accompanying drawings need to show different emphases, and sometimes different scales are used.
[0037] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", in addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features. In addition, as used in the present invention, when an element is disposed on another element, it generally only means that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the two elements can be directly or indirectly connected, coupled, cooperated or transmitted through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element can be inside, outside, above, below or on one side of another element, etc. in any orientation, unless otherwise explicitly stated in the content. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.
[0038] Figure 1It is a flowchart of a method for forming a static random access memory according to an embodiment of the present invention. As Figure 1 shown, this embodiment provides a method for forming a static random access memory, including:
[0039] Step S10: Provide a substrate, on which PMOS devices and NMOS devices are formed;
[0040] Step S20: Perform an epitaxial growth process to form germanium-silicon stress layers in the substrate on both sides of the PMOS devices;
[0041] Step S30: Form a compressive stress etch stop layer that covers the PMOS devices;
[0042] Step S40: Form a tensile stress etch stop layer that covers the NMOS devices.
[0043] Figures 2 to 12 It is a schematic structural diagram corresponding to the steps of the method for forming a static random access memory according to an embodiment of the present invention. To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following combines the accompanying Figures 2 to 12 description of the present invention to make a detailed description of specific embodiments of the present invention.
[0044] As Figure 2As shown, a substrate 10 is provided. The substrate 10 can be single-crystalline silicon or polycrystalline silicon, and can also be semiconductor materials such as silicon, germanium, silicon germanide, gallium arsenide, etc. It can also be a composite structure such as silicon-on-insulator. Those skilled in the art can select the type of the semiconductor substrate according to the semiconductor devices formed on the semiconductor substrate. Therefore, the type of the semiconductor substrate should not limit the protection scope of the present invention. The substrate 10 includes a first well region 12a and a second well region 12b. The doping type of the first well region 12a is N-type, that is, an N-well, which is used to form a PMOS device 14. The doping type of the second well region 12b is P-type, that is, a P-well, which is used to form an NMOS device 13. The adjacent first well region 12a and second well region 12b are isolated by a shallow trench isolation structure 11. The NMOS device 13 includes a gate dielectric layer 13a, a gate 13b, an isolation layer 13c, and a sidewall 13d. The material of the gate dielectric layer 13a includes one or a combination of an oxide layer and a hafnium oxide layer. The hafnium oxide material has a higher dielectric constant and can effectively improve the gate leakage current. The oxide layer can be formed by a thermal oxidation process and the hafnium oxide layer can be formed by an atomic layer deposition process. In order to prevent hafnium ions, the metal ions in hafnium oxide, from entering the gate 13b, a blocking layer (not shown) is usually formed on the gate dielectric layer 13a. The material of the blocking layer is, for example, titanium nitride. An isolation layer 13c is also formed on the gate 13b. The material of the isolation layer 13c is silicon nitride and / or silicon oxide. A sidewall 13d is formed on the sidewall of the gate 13b. The structural composition of the PMOS device 14 is the same as that of the NMOS device 13 and will not be described herein again.
[0045] Please continue to refer to Figure 2 , and the LDD (Lightly Doped Drain) process is used to form a buffer region 15a of the PMOS device in the substrate 10 on both sides of the PMOS device 14, and a buffer region 15b of the NMOS device is formed in the substrate 10 on both sides of the NMOS device 13. The lightly doped buffer region makes the doping gradient of the drain / source junction smoother, reduces the steepness of the junction, thereby reducing the leakage current and increasing the breakdown voltage. Especially in PMOS devices with a germanium silicon stress layer, the SiGe material improves the hole mobility by introducing compressive strain. The buffer region coordinates with the selectively epitaxially grown germanium silicon stress layer to avoid stress mutation or interface defects. The buffer region may serve as a transition between the germanium silicon stress layer and the channel, optimizing the stress distribution and maintaining the electrical performance. An etching process is used to form germanium silicon trenches 16a in the substrate 10 on both sides of the PMOS device 14. The etching process includes a dry etching process and a wet etching process. Those skilled in the art know the dry etching process and the wet etching process for forming the germanium silicon trenches 16a and will not be described herein again.
[0046] As Figure 3As shown, an epitaxial growth process is performed to form germanium-silicon stress layers 16 in the substrate 10 on both sides of the PMOS device 14. Specifically, germanium-silicon is selectively epitaxially grown in germanium-silicon trenches 16a, and a cap layer is formed on the top of the germanium-silicon. The germanium-silicon in the germanium-silicon trenches 16a and the cap layer on the top of the germanium-silicon together constitute the germanium-silicon stress layer 16. By applying compressive stress, the germanium-silicon stress layer 16 can change key parameters such as the energy band structure, carrier mobility, and light absorption coefficient in the PMOS device, thereby improving the performance and stability of the PMOS device.
[0047] As Figure 4 shown, an ion implantation process is used to form source regions 17a and drain regions of the PMOS device in the substrate 10 on both sides of the PMOS device 14, and source regions 17b and drain regions of the NMOS device are formed in the substrate 10 on both sides of the NMOS device 13.
[0048] As Figures 5 to 8 shown, a metal silicide 19a is formed, and the metal silicide 19a is located on the gate, source region, and drain region of the PMOS device 14 and on the gate, source region, and drain region of the NMOS device 13. Specifically, the process for forming the metal silicide 19a includes:
[0049] As Figure 5 shown, a metal silicide blocking layer 18 is formed, and the metal silicide blocking layer (Salicide Block, SAB) covers the PMOS device 14 and the NMOS device 13. The material of the metal silicide blocking layer 18 is, for example, silicon oxide, and it can be formed by chemical vapor deposition. The metal silicide blocking layer 18 is used to protect the regions where metal silicide is not required to be formed and prevent metal silicide from being formed in the regions where metal silicide is not required to be formed.
[0050] As Figure 6 shown, the metal silicide blocking layer 18 on the gate, source region, drain region of the PMOS device and on the gate, source region, drain region of the NMOS device is etched to expose the top surfaces of the gate, source region, drain region of the PMOS device and the gate, source region, drain region of the NMOS device. The etching process includes a dry etching process and a wet etching process. Those skilled in the art are aware of the dry etching process and the wet etching process for etching the metal silicide blocking layer 18, and will not be elaborated here.
[0051] As Figure 7As shown, after performing the etching process and before forming the metal layer, a pre-cleaning process is first performed to clean the surface impurities on the top surfaces of the gates, source regions, drain regions of the PMOS device and the gates, source regions, drain regions of the NMOS device. The metal layer 19 is deposited, and the metal layer 19 covers the top surfaces of the gates, source regions, and drain regions of the PMOS device 14 and the top surfaces of the gates, source regions, and drain regions of the NMOS device 13. The material of the metal layer 19 is, for example, NiPt and TiN, and the metal layer 19 is deposited by physical vapor deposition.
[0052] As Figure 8 shown, an annealing process is performed, and metal silicides 19a are formed on the top of the gate, the top of the source region and the drain region of the PMOS device 14 and the top of the gate, the top of the source region and the drain region of the NMOS device 13. The material of the metal silicide 19a is NiSi, and is formed by the reaction of the metal layer 19 and silicon through the annealing process.
[0053] As Figure 9 and Figure 10 shown, a compressive stress etch stop layer 20 is formed, and the compressive stress etch stop layer 20 covers the PMOS device 14. Specifically, the steps of forming the compressive stress etch stop layer 20 include: as Figure 9 shown, a compressive stress etch stop layer 20 is formed, and the compressive stress etch stop layer 20 covers the PMOS device 14 and the NMOS device 13; the material of the compressive stress etch stop layer 20 is silicon nitride. The compressive stress etch stop layer 20 is formed by chemical vapor deposition. As Figure 10 shown, the compressive stress etch stop layer 20 on the NMOS device 13 is removed by an etching process, and the compressive stress etch stop layer 20 on the PMOS device 14 is retained.
[0054] As Figure 11 and Figure 12 shown, a tensile stress etch stop layer 21 is formed, and the tensile stress etch stop layer 21 covers the NMOS device 13. Specifically, the steps of forming the tensile stress etch stop layer include: as Figure 11 shown, a tensile stress etch stop layer 21 is formed, and the tensile stress etch stop layer 21 covers the PMOS device 14 and the NMOS device 13; the material of the tensile stress etch stop layer 21 is silicon nitride, and the tensile stress etch stop layer 21 can be formed by chemical vapor deposition. The temperatures of the chemical vapor deposition processes for forming the compressive stress etch stop layer 20 and the tensile stress etch stop layer 21 are different.
[0055] As Figure 12As shown, the tensile stress etch stop layer 21 on the PMOS device 14 is removed, and the tensile stress etch stop layer 21 on the NMOS device 13 is retained. The static random access memory in this embodiment is a 40-nanometer node high-voltage device, and the bit cell size is scaled down to 190 (0.0199 μm 2 ) and even less than 163 (0.0163 μm 2 ) in the future. For the 40-nanometer node platform compared with the 28-nanometer one, the speed difference between the NMOS device and the PMOS device is significant, resulting in poor performance of the PMOS device. By first forming a germanium-silicon stress layer 16 in the substrate 10 on both sides of the PMOS device 14, and then forming a compressive stress etch stop layer 20 on the PMOS device 14, compressive strain is applied to the PMOS device. A tensile stress etch stop layer 21 is formed on the NMOS device 13, and tensile strain is applied to the NMOS device. Through the tensile stress etch stop layer 21, the electron mobility is improved, thereby enhancing the current driving ability; the drive current ratio (N / P Ratio) of the NMOS device and the PMOS device in the static random access memory is increased, and the transistor parameter mismatch (Mismatch) in the memory cell of the static random access memory is reduced, thereby effectively improving the performance of the PMOS device in the static random access memory.
[0056] After the step of forming the tensile stress etch stop layer 21: An inter-layer dielectric layer is formed using an ILD (Inter-Layer Dielectric) process, and a contact hole etching process is performed to form contact holes on the gate, source, and drain of the PMOS device, and contact holes on the gate, source, and drain of the NMOS device. The contact holes penetrate the inter-layer dielectric layer and expose the metal silicide 19a of the gate, source, and drain of the PMOS device and the NMOS device; A deposition process is performed to form contact plugs in the contact holes, and the contact plugs are used to lead out the gate, source, and drain of the PMOS device and the gate, source, and drain of the NMOS device. The deposition process is, for example, a physical vapor deposition process.
[0057] This embodiment also provides a static random access memory, which is prepared by using the formation method of the static random access memory described in any one of the above, as Figure 12As shown, it includes the substrate 10, the first well region 12a and the second well region 12b located within the substrate 10. The doping type of the first well region 12a is N-type, that is, an N-well, which is used to form the PMOS device 14. The doping type of the second well region 12b is P-type, that is, a P-well, which is used to form the NMOS device 13. The adjacent first well region 12a and second well region 12b are isolated by a shallow trench isolation structure 11. The NMOS device 13 includes a gate dielectric layer 13a, a gate 13b, an isolation layer 13c and sidewalls 13d. The material of the gate dielectric layer 13a includes one or a combination of an oxide layer and a hafnium oxide layer. Hafnium oxide materials have a high dielectric constant and can effectively improve the gate leakage current. The oxide layer can be formed by a thermal oxidation process and the hafnium oxide layer can be formed by an atomic layer deposition process. In order to prevent hafnium ions, the metal ions in hafnium oxide, from entering the gate 13b, a barrier layer (not shown) is usually formed on the gate dielectric layer 13a. The material of the barrier layer is, for example, titanium nitride. An isolation layer 13c is also formed on the gate 13b. The material of the isolation layer 13c is silicon nitride and / or silicon oxide. Sidewalls 13d are formed on the sidewalls of the gate 13b. The structural composition of the PMOS device 14 is the same as that of the NMOS device 13. Germanium-silicon stress layers 16 are formed in the substrate 10 on both sides of the PMOS device 14. Metal silicides 19a are formed on the top surface of the gate, the source region and the drain region surfaces of the PMOS device 14 and on the top surface of the gate, the source region and the drain region surfaces of the NMOS device 13. A compressive stress etch stop layer 20 is formed on the PMOS device 14 to apply compressive stress to the PMOS device. A tensile stress etch stop layer 21 is formed on the NMOS device 13 to apply tensile stress to the NMOS device. Through the tensile stress etch stop layer 21, the electron mobility is improved, thereby improving the current driving ability; the drive current ratio (N / P Ratio) of the NMOS device and the PMOS device in the static random access memory is increased, and the transistor parameter mismatch (Mismatch) in the memory cell of the static random access memory is reduced, thereby effectively improving the performance of the PMOS device in the static random access memory.
[0058] In summary, in the method for forming a static random access memory provided by the embodiments of the present invention, by first performing a germanium-silicon process to form germanium-silicon stress layers in the substrate on both sides of the PMOS device; then sequentially forming a compressive stress etch stop layer and a tensile stress etch stop layer, the compressive stress etch stop layer covers the PMOS device, and the tensile stress etch stop layer covers the NMOS device. By first forming germanium-silicon stress layers in the substrate on both sides of the PMOS device, and then sequentially forming a compressive stress etch stop layer on the PMOS device and a tensile stress etch stop layer on the NMOS device, a compressive stress is applied to the PMOS device and a tensile stress is applied to the NMOS device, thereby improving the drive current ratio between the NMOS device and the PMOS device of the static random access memory, reducing the transistor parameter mismatch in the memory cell of the static random access memory, and further effectively improving the performance of the PMOS device of the static random access memory.
[0059] It should be noted that the embodiments in this specification are described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. In addition, the different parts among the embodiments can also be combined and used with each other. The present invention does not limit this.
[0060] In addition, it should also be recognized that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the protection of the technical solution of the present invention.
Claims
1. A method for forming a static random access memory, characterized in that, Comprising: Providing a substrate on which PMOS devices and NMOS devices are formed; Performing an epitaxial growth process to form germanium-silicon stress layers in the substrate on both sides of the PMOS devices; Forming a compressive stress etch stop layer that covers the PMOS devices; Forming a tensile stress etch stop layer that covers the NMOS devices.
2. The method for forming a static random access memory according to claim 1, wherein The step of forming the compressive stress etch stop layer includes: Forming a compressive stress etch stop layer that covers the PMOS devices and the NMOS devices; Removing the compressive stress etch stop layer on the NMOS devices and retaining the compressive stress etch stop layer on the PMOS devices.
3. The method for forming a static random access memory according to claim 1, wherein The step of forming the tensile stress etch stop layer includes: Forming a tensile stress etch stop layer that covers the PMOS devices and the NMOS devices; Removing the tensile stress etch stop layer on the PMOS devices and retaining the tensile stress etch stop layer on the NMOS devices.
4. The method for forming a static random access memory according to claim 1, characterized in that, The compressive stress etch stop layer and the tensile stress etch stop layer are formed by a chemical vapor deposition process.
5. The method for forming a static random access memory according to claim 4, wherein, The temperatures of the chemical vapor deposition processes for forming the compressive stress etch stop layer and the tensile stress etch stop layer are different.
6. The method for forming a static random access memory according to claim 1, wherein The materials of both the compressive stress etch stop layer and the tensile stress etch stop layer are silicon nitride.
7. The method for forming a static random access memory according to claim 1, wherein, Both the PMOS devices and the NMOS devices include gates. After forming the germanium-silicon stress layers, source regions and drain regions of the PMOS devices are formed in the substrate on both sides of the gates of the PMOS devices, and source regions and drain regions of the NMOS devices are formed in the substrate on both sides of the gates of the NMOS devices.
8. The method for forming a static random access memory according to claim 7, wherein After forming the germanium-silicon stress layers and before forming the compressive stress etch stop layer, it further includes: Forming a metal silicide blocking layer that covers the PMOS devices and the NMOS devices; Etching the metal silicide blocking layer on the gates, source regions, and drain regions of the PMOS devices and the gates, source regions, and drain regions of the NMOS devices to expose the top surfaces of the gates, source regions, and drain regions of the PMOS devices and the gates, source regions, and drain regions of the NMOS devices; Performing a pre-cleaning process to clean the top surfaces of the gates, source regions, and drain regions of the PMOS devices and the gates, source regions, and drain regions of the NMOS devices; Depositing a metal layer that covers the top surfaces of the gates, source regions, and drain regions of the PMOS devices and the gates, source regions, and drain regions of the NMOS devices; Performing an annealing process to form metal silicides on the tops of the gates, source regions, and drain regions of the PMOS devices and the gates, source regions, and drain regions of the NMOS devices.
9. The method for forming a static random access memory according to claim 7, wherein, After the step of forming the tensile stress etch stop layer: Performing a contact hole etching process to form contact holes on the gates, source regions, and drain regions of the PMOS devices and on the gates, source regions, and drain regions of the NMOS devices; A deposition process is performed to form a contact plug within the contact hole, and the contact plug is used to lead out the gate, the source region, and the drain region of the PMOS device, as well as the gate, the source region, and the drain region of the NMOS device.
10. A static random access memory, characterized in that, It is fabricated by using the method for forming a static random access memory according to any one of claims 1 to 9.