Storage chip based on two-dimensional flash memory device and CMOS and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductor memories, and particularly relates to a memory chip based on a two-dimensional material flash memory device and a CMOS (complementary metal oxide semiconductor) and a preparation method of the memory chip. The memory chip comprises a substrate and a flash memory array, wherein the substrate is prepared by a CMOS (Complementary Metal Oxide Semiconductor) process and is provided with a memory peripheral circuit; the flash memory array is constructed by a two-dimensional material flash memory device; the substrate with a memory peripheral circuit includes: a bottom substrate; the MOS device is arranged on the surface of the substrate; an isolation layer between the metal wires; based on the ultrafast nonvolatile storage characteristic of the two-dimensional material flash memory device, the integration density of the flash memory device is further improved, and the method comprises the steps of flash memory device stacking design, flash memory device structure design and flash memory array circuit structure design. On the basis of keeping the basic performance of the ultra-fast flash memory device, the three-dimensional stacking and scale integration of the flash memory device compatible with the CMOS process are realized, and the collaborative breakthrough of the storage performance and the storage density of a storage chip is further realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor memories, and particularly relates to a storage chip based on a two-dimensional material flash device and CMOS, and a preparation method thereof. Background Art

[0002] Existing memory technologies are mainly dominated by volatile memory technologies such as dynamic random access memory (DRAM) and static random access memory (SRAM). However, their data volatility characteristics result in high chip power consumption. For mainstream non-volatile memory, limited by the material factors of silicon material itself, the typical programming speed of silicon-based flash (Flash) (~100 microseconds) is far behind volatile memory technologies.

[0003] In recent years, with the gradual failure of Moore's law, in order to increase the capacity of memories, many different three-dimensional integrated Flash technologies have been proposed successively, including BiCS (bit cost scalable), PBiCS (Pipe-shaped BiCS), and V-NAND, etc. These structures can be divided into two types: channel stacking type and gate stacking type. Among them, the gate stacking type V-NAND is the first commercial 3D NAND structure, using polysilicon as the channel in the vertical direction and Si3N4 as the charge trapping layer. Currently, most domestic and foreign manufacturers (including Samsung, SK Hynix, Micron, Yangtze Memory Technologies Co., Ltd., etc.) have the mass production capacity to achieve 200+ layers.

[0004] It should be noted that two-dimensional material flash devices show great potential in improving the storage performance and size miniaturization of storage chips due to their unique properties. However, there are still many challenges in their transformation into practical applications and further development. First, the current two-dimensional material logic device technology is not yet mature, and it is difficult to implement the external circuit of the storage chip corresponding to the two-dimensional material flash device, and it is difficult to realize a storage chip completely composed of two-dimensional materials; second, due to the inherently thin channel of two-dimensional materials, it is difficult to be compatible with traditional high-temperature and high-energy processes, resulting in difficulty in realizing three-dimensional integration of a single chip, and thus difficult to achieve a breakthrough in chip storage capacity. Summary of the Invention

[0005] The purpose of the present invention is to provide a storage chip based on a two-dimensional material flash device and CMOS technology with good storage performance and high storage density, and a preparation method thereof, which can improve the storage density and realize its storage function while maintaining the nanosecond-level programming ability of the storage device.

[0006] The storage chip based on a two-dimensional flash device and CMOS provided by the present invention has a cross-sectional structure as Figure 1 shown, and its main components are as Figure 2As shown, the chip mainly includes two parts, a substrate with a memory peripheral circuit fabricated by standard CMOS process and a flash memory array constructed by two-dimensional material flash memory devices.

[0007] The substrate with a memory peripheral circuit, as Figure 2 shown in the lower right figure, includes: a silicon wafer substrate (1) at the bottom layer; an N-type silicon active region (2) on the substrate surface, serving as the source and drain of NMOS devices; a P-type silicon active region (3) on the substrate surface, serving as the source and drain of PMOS devices; metal wires (7) on the active regions, for ohmic contact of the active regions and interconnection between devices; a low dielectric constant material (4) between the metal wires, acting as an isolation layer.

[0008] Optionally, the silicon wafer substrate, active regions, metal wires, and isolation layer material are determined with reference to the materials used in the specific silicon-based process node.

[0009] The two-dimensional material flash memory device array, as Figure 2 shown in the upper right figure. Taking the first layer of devices as an example, each layer of the flash memory array includes: a first metal layer covering the surface of the memory peripheral circuit substrate, serving as the gate (7) of the two-dimensional material flash memory device; a first dielectric layer covering the first metal layer, serving as a barrier layer (5); a second metal layer covering the first dielectric layer and at the exact center of the first metal layer, serving as the floating gate (7) of the flash memory device; a second dielectric layer covering the second metal layer, serving as the tunneling layer (5) of the flash memory device; a two-dimensional material channel (6) covering the surface of the tunneling layer and covered by source-drain metals; a low dielectric constant material covering between the channel material and the gate of the second layer of devices, acting as a buffer and isolation layer (4). The devices of each layer are interconnected through vias to form the final flash memory device array.

[0010] Preferably, for the first metal layer, the material type of the gate is a Cr / Au / Pt metal stack, with thicknesses of 5nm - 10nm / 80nm - 100nm / 5nm - 10nm respectively.

[0011] Preferably, for the second metal layer, the material type of the floating gate is Pt, with a thickness of 1 - 10nm.

[0012] Preferably, the metal material type of the source and drain is a Cr / Au metal stack, with a thickness of 50nm - 100nm.

[0013] Preferably, for the barrier layer (the dielectric between the gate (14) and the floating gate (15)), the material type of the gate dielectric is HfO2, with a thickness of 14nm - 20nm.

[0014] Preferably, the material type of the tunneling layer (the dielectric between the floating gate (15) and the source and drain (12, 13)) of the gate dielectric is HfO2, and the thickness is 7 nm - 10 nm.

[0015] Preferably, the buffer layer material is cross-linked polyvinyl chloride (PVA), and the thickness is 500 nm - 700 nm.

[0016] Preferably, the material type of the low dielectric constant isolation material is SiO2, and the thickness is 100 nm - 300 nm.

[0017] Preferably, the type of the two-dimensional semiconductor material is MoS2.

[0018] Preferably, the metal deposited by the via process is a Cr / Au / Pt dielectric stack, and the thicknesses are 5 nm - 10 nm / 80 nm - 100 nm / 5 nm - 10 nm respectively.

[0019] The present invention also provides a method for manufacturing the above-mentioned memory chip based on the two-dimensional flash device and CMOS, as shown in Figure 3 including using standard CMOS process, pre-cleaning process, via process, metal patterning process, dielectric material deposition process, two-dimensional semiconductor transfer technology and patterning etching process; the specific steps are as follows:

[0020] (1) First, form a substrate with a complete memory external circuit through the standard CMOS process;

[0021] (2) Then, after the pre-cleaning process of the substrate, lead out the wires required for the device;

[0022] (3) Then, complete the deposition of the dielectric stack through patterning exposure, metal deposition process and dielectric material deposition process;

[0023] (4) Then, use the two-dimensional material transfer technology to transfer the two-dimensional material from the grown substrate to the target substrate wafer, and through patterning exposure and etching process;

[0024] (5) Finally, use patterning exposure and metal deposition process to form the source and drain electrodes of the device, and then deposit the buffer layer material and isolation layer material separately;

[0025] Repeat steps (3), (4), (5) to achieve multi-layer stacking of the flash memory array, and finally complete the manufacture of the chip.

[0026] Preferably, the node of the standard CMOS process flow is the "0.13 um" process node.

[0027] Optionally, the patterning exposure includes electron beam lithography, ultraviolet lithography, laser direct writing, etc.

[0028] Optionally, the metal deposition process includes physical vapor deposition (PVD), electron beam evaporation (EBE), etc.

[0029] Optionally, the dielectric material deposition process includes atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), etc.

[0030] Optionally, the dielectric material etching process includes reactive ion etching (RIE), inductively coupled plasma etching (ICP), etc.

[0031] In the memory chip and its manufacturing method according to the present invention, it further includes:

[0032] (1) Flash memory array stacking process design:

[0033] For the device stacking process in the manufacturing method of the flash memory chip, its basic principle is as Figure 4 shown. According to the characteristics of the material deposition process itself, by transferring a layer of non-destructive dielectric material 10 on the surface of the channel material 9, physical isolation between materials is achieved, thereby effectively avoiding the damage of the channel material 9 by the material 11 with a relatively intense process reaction, and realizing stable non-destructive interlayer isolation.

[0034] (2) Flash memory device structure design:

[0035] For the two-dimensional material flash memory device array, the device structure diagram of each specific unit is as Figure 5 shown. The device structure includes a gate (14), a floating gate (15), source and drain electrodes (12 and 13); a low dielectric constant material (4) for device interlayer isolation in the lower layer, a high dielectric constant material (5) serving as a device blocking layer and a tunneling layer, a two-dimensional material (6) of the channel, and the basic device is connected by a circuit to form the basic circuit structure of the two-dimensional flash memory. The present invention effectively improves the coupling efficiency of the gate (14) for channel programming and the programming efficiency of the device by increasing the area of the floating gate layer (15).

[0036] (3) Flash memory array structure design:

[0037] As Figure 6As shown, due to the performance characteristics of the ultra-fast flash memory device, the present invention intends to adopt an array structure with parallel arrangement of flash memory devices. Specifically, the devices in the same horizontal row share the word line, and the devices in the same vertical row share the bit line and the source line. Taking the operation of one device as an example, when performing a programming operation, a positive voltage is applied to the word line corresponding to the selected cell, a negative voltage is applied to the corresponding bit line, and the source line is floating. Thus, the selected memory cell senses a positive bias voltage from the gate to the source-drain, realizing the programming operation of the device. During the erasing operation, the voltage polarities of the word line, the bit line, and the source line are reversed to achieve the erasing of the device. When performing a read operation, a positive voltage is applied to the corresponding bit line, the corresponding word line and source line are grounded, other word lines are applied with a negative voltage for suppression, and the bit lines and source lines of other cells are uniformly grounded to realize the read operation of the device. Description of the Drawings

[0038] Figure 1 It is a cross-sectional structure diagram of a flash memory chip.

[0039] Figure 2 It is a diagram showing the components of a flash memory chip.

[0040] Figure 3 It is a diagram showing the preparation process flow of a flash memory chip.

[0041] Figure 4 It is a diagram showing the principle of the stacking process of flash memory devices.

[0042] Figure 5 It is a diagram showing the structure of a flash memory device.

[0043] Figure 6 It is a diagram showing the circuit connection of flash memory devices in a flash memory chip.

[0044] Reference numerals in the figure: 1 is undoped material Si, 2 is N-type heavily doped material Si, 3 is P-type heavily doped material Si, 4 is low dielectric constant material for isolation (mainly refers to polyvinyl chloride PVA, SiO2), 5 is high dielectric constant material (including Al2O3, HfO2, etc.), 6 is two-dimensional material (including MoS2, WSe2, etc.), 7 is various metal materials (including Pt, Au, Cr, Ti, Ni, etc.), 8 is a support substrate, 9 is channel two-dimensional material (mainly including MoS2, WSe2, etc.), 10 is buffer layer material (such as transferred cross-linked polyvinyl chloride (PVA), etc.), 11 is low dielectric constant material (such as SiO2); 12 is the source electrode, 13 is the drain electrode, 14 is the gate, 15 is the floating gate; BL, WL, and SL respectively represent the bit line, word line, and source line in the flash memory array. Detailed Embodiment

[0045] The present invention will be further introduced below through embodiments in combination with the drawings.

[0046] Many specific details of the present invention described hereinafter, such as the structure, materials, dimensions, processing technologies and techniques of the device, are provided to facilitate a clearer understanding of the present invention. Unless otherwise specified, each part in the device can be made of materials known to those skilled in the art.

[0047] The present invention provides a method for fabricating a three-dimensional stacked CMOS flash memory chip based on a two-dimensional material flash memory device. The process is as Figure 3 shown, and the specific steps are as follows:

[0048] (1) Fabricate a substrate including the memory peripheral circuit using CMOS technology;

[0049] (2) Clean the substrate, and then use patterning methods such as laser direct writing / electron beam lithography / ultraviolet lithography, combined with metal deposition means such as electron beam evaporation / physical vapor deposition, to fabricate the word line (WL) of the first layer of the device and the interconnection lines with the lower-layer circuit;

[0050] (3) Use dielectric deposition means such as atomic layer deposition in combination with the metal patterning method prepared in step (2) to complete the preparation of the gate dielectric / metal / dielectric stack;

[0051] (4) Transfer the two-dimensional material onto the target substrate using two-dimensional material transfer technology;

[0052] (5) Use patterning methods such as laser direct writing / EBL / ultraviolet lithography again, combined with wet / dry etching to complete the preparation of the channel pattern;

[0053] (6) Use the patterning method and metal deposition method described in (2) again to fabricate the bit line (BL) and source line (SL) of the first layer of the device;

[0054] (7) Use medium integration processes such as transfer technology, atomic layer deposition, and physical vapor deposition to form an interlayer isolation dielectric stack. Note that at this time, a buffer layer material should be transferred first, then a low dielectric constant material should be deposited, and the device via lead-out should be completed using the patterning and etching technologies described in step (5);

[0055] (8) Repeat steps (2) to (7) to achieve three-dimensional stacking of the flash memory array.

[0056] The operation method of the flash memory array provided by the present invention is as follows (as Figure 6 shown): Taking the operation of the first device in the first row as an example:

[0057] For the write operation, a positive voltage pulse is applied to word line 1, the other word lines are grounded, a synchronous negative voltage pulse is applied to bit line 1, the other bit lines are grounded, and all source lines are floating.

[0058] For the erasing operation, a negative voltage pulse is applied to word line 1, and the remaining word lines are grounded. A synchronous positive voltage pulse is applied to bit line 1 and source line 1, and the remaining source lines are grounded.

[0059] For the reading operation, word line 1 is grounded, bit line 1 is grounded, the remaining bit lines are connected to a negative voltage, and the remaining word lines and source lines are all grounded.

[0060] As described above, the three-dimensional stacked CMOS flash memory chip based on the two-dimensional material flash memory device of the present invention has been described in detail. However, the present invention is not limited to the above examples, and various improvements and deformations can be made without departing from the gist of the present invention.

Claims

1. A storage chip based on a two-dimensional flash memory device and CMOS, characterized in that It includes two parts: a substrate with a memory peripheral circuit prepared by CMOS process and a flash memory array constructed by two-dimensional material flash memory devices; where: The substrate with a memory peripheral circuit includes: a bottom silicon wafer substrate (1); an N-type silicon active region (2) on the substrate surface, serving as the source and drain of NMOS devices; a P-type silicon active region (3) on the substrate surface, serving as the source and drain of PMOS devices; metal wires (7) on the active regions, for ohmic contact of the active regions and interconnection between devices; a low dielectric constant material (4) between the metal wires, acting as an isolation layer; The two-dimensional material flash memory device array, where each layer of the flash memory array includes: a first metal layer, covering the surface of the memory peripheral circuit substrate, serving as the gate (7) of the two-dimensional material flash memory device; a first dielectric layer, covering the first metal layer, serving as a blocking layer (5); a second metal layer, covering the first dielectric layer and in the exact center of the first metal layer, serving as the floating gate (7) of the flash memory device; a second dielectric layer, covering the second metal layer, serving as the tunneling layer (5) of the flash memory device; a two-dimensional material channel (6) covering the surface of the tunneling layer and covered by source-drain metals; a low dielectric constant material covering between the channel material and the gate of the second-layer device, acting as a buffer and isolation layer (4); the devices of each layer are interconnected through vias to form the final flash memory device array.

2. The storage chip according to claim 1, wherein, The two-dimensional material flash memory device array adopts an array structure form with parallel arrangement of flash memory devices. Specifically, that is, the devices in the same horizontal row share the word line, and the devices in the same vertical row share the bit line and the source line; the specific operation method is: when performing a programming operation, a positive voltage is applied to the selected word line, a negative voltage is applied to the corresponding bit line, and the source line is floating, so that the selected memory cell senses a positive bias voltage from the gate to the source-drain, realizing the programming operation of the device; When performing an erase operation, the voltage polarities of the word line, the bit line, and the source line are reversed to achieve the erase of the device; when performing a read operation, a positive voltage is applied to the corresponding bit line, the corresponding word line and source line are grounded, other word lines are applied with an inhibitory negative voltage, and the bit lines and source lines of other cells are uniformly grounded to achieve the read operation of the device.

3. The storage chip according to claim 1, characterized in that: For the first metal layer, the material of the gate is a Cr / Au / Pt metal stack, with a thickness of 5nm - 10nm / 80nm - 100nm / 5nm - 10nm; For the second metal layer, the material of the floating gate is Pt, with a thickness of 1 - 10nm; For the source and drain, the metal material is a Cr / Au metal stack, with a thickness of 50nm - 100nm; For the blocking layer, that is, the dielectric between the gate (14) and the floating gate (15), the material is HfO2, with a thickness of 14nm - 20nm; For the tunneling layer, that is, the dielectric between the floating gate (15) and the source and drain (12, 13), the material is HfO2, with a thickness of 7nm - 10nm; The material of the buffer layer is cross-linked polyvinyl chloride (PVA), with a thickness of 500nm - 700nm; The low dielectric constant isolation material is SiO2 with a thickness of 100 nm - 300 nm; The two-dimensional semiconductor material is MoS2; The metal deposited by the via process is a Cr / Au / Pt dielectric stack with a thickness of 5 nm - 10 nm / 80 nm - 100 nm / 5 nm - 10 nm.

4. The manufacturing method of the storage chip according to any one of claims 1-3, characterized in that, It includes using CMOS process, pre-clean process, via process, metal patterning process, dielectric material deposition process, two-dimensional semiconductor transfer technology and patterning etching process; the specific steps are as follows: (1) First, form a substrate with a complete external circuit of the memory through the CMOS process; (2) Then, perform a pre-cleaning process on the substrate, and then lead out the wires required for the device; (3) Then, complete the deposition of the dielectric stack through patterned exposure, metal deposition process and dielectric material deposition process; (4) Then, use two-dimensional material transfer technology to transfer the two-dimensional material from the growth substrate to the target substrate wafer, and through patterned exposure and etching process; (5) Finally, use patterned exposure and metal deposition process to form the source and drain electrodes of the device, and then deposit the buffer layer material and isolation layer material separately; Repeat steps (3), (4), (5) to achieve multi-layer stacking of the flash memory array, and finally complete the preparation of the chip.

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