Ultra-short-channel nonvolatile flash memory device based on two-dimensional material and preparation method of ultra-short-channel nonvolatile flash memory device

Abstract

The invention belongs to the technical field of semiconductor memories, and particularly relates to an ultra-short channel nonvolatile flash memory device based on a two-dimensional material and a preparation method of the ultra-short channel nonvolatile flash memory device. According to the invention, the characteristic length is reduced through the design of the atomic-scale thin-layer channel and the gate stack, thereby promoting the size miniaturization of the device; according to the device, the tunneling potential barrier is reduced through the energy band design and a Van der Waals stacked high-quality interface, and the ten-nanosecond programming / erasing speed and the nonvolatile characteristic are achieved; the short channel of the device is realized through a vertical deposition and inclined deposition two-step process, and the channel length can be regulated and controlled by changing the electrode thickness and the deposition angle. On the premise of not using an advanced photoetching technology, the sub-10nm channel length can be realized, the channel length miniature bottleneck of a silicon-based flash memory device is broken through, and a new solution is provided for high-density integration of a novel high-speed nonvolatile memory.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor memory, and in particular relates to a non-volatile flash memory device and a preparation method thereof. Background Art

[0002] In the era of artificial intelligence, higher research has been conducted on information storage technology, and new storage technologies that meet the requirements of large capacity, high speed and low power consumption are urgently needed. Neither mainstream volatile memory (DRAM) nor non-volatile memory (flash memory) can independently cover the above three requirements. Among them, flash memory has significant advantages in integrated capacity and power consumption due to its single-transistor structure and long retention time. However, the large tunneling barrier under the silicon material system limits the Fowler-Nordheim (FN) tunneling programming speed of flash memory to 10-100 microseconds. In addition, in the post-Moore era, device size miniaturization has gradually reached its limit. For example, the channel length miniaturization of silicon flash memory has stagnated at about 15 nanometers. To ensure mobility, the silicon channel thickness cannot be less than 6 nanometers. At the same time, to ensure the reliability of charge storage, the miniaturization of the flash memory medium stack thickness lags significantly behind that of transistors. Thicker channels and dielectric layers lead to larger characteristic lengths (scale lengths), exacerbating the short channel effect, causing unstable storage state thresholds, and hindering device miniaturization and integrated capacity improvement.

[0003] With the advent of graphene, two-dimensional layered materials have gradually come into people's view and have been studied more and more widely. The mobility of two-dimensional materials does not decline with the thickness reduction, and still has high mobility at the atomic level thickness, breaking through the thickness limit of silicon materials. In the two-dimensional material channel, carriers are confined in the ultra-thin channel, which effectively improves the gate control ability and immunity to short channel effects. In addition, two-dimensional materials have rich energy band characteristics and can flexibly form heterojunctions in a van der Waals stacking manner, which provides the possibility for designing new principle devices.

[0004] Introducing two-dimensional materials into the flash memory structure can reduce the effective tunneling barrier and increase the FN tunneling programming speed to tens of nanoseconds on the basis of non-volatile data retention. However, advanced photolithography processes are complex and expensive, and the high-speed non-volatile characteristics of two-dimensional flash memory devices have only been verified in 10-micron long-channel prototype devices, limiting their high-integration applications. Summary of the invention

[0005] The object of the present invention is to provide a non-volatile flash memory device based on two-dimensional materials and having a significantly shortened channel length while maintaining high speed and long retention characteristics, and a preparation method thereof.

[0006] The ultra-short channel non-volatile flash memory device based on two-dimensional materials provided by the present invention includes: an insulator substrate; a gate electrode located on the surface of the insulator substrate; a first dielectric layer covering the gate electrode and the insulator substrate as a barrier layer; a second dielectric layer covering the first dielectric layer as a charge trapping layer; a third dielectric layer covering the second dielectric layer as a tunneling layer; a channel layer located on the surface of the third dielectric layer; a thick source electrode and a thick drain electrode layer located on the channel layer; a thin source electrode and a thin drain electrode layer located on the channel layer and the thick source electrode and the thick drain electrode layer. For the first to third dielectric layers, by selecting the dielectric constant and thickness of the materials (for example, introducing high dielectric constant dielectrics), the device feature length can be reduced, which is beneficial to size scaling, and the capacitance matching and electric field distribution of the flash memory gate stack can be optimized to improve the tunneling efficiency, thereby improving the programming speed.

[0007] Preferably, the gate electrode material is one of Cr, Ti, Sb, Au, Pt and any combination thereof;

[0008] Preferably, the material of the first gate dielectric layer is Al2O3, and the thickness is 10-20 nanometers;

[0009] Preferably, the material of the second gate dielectric layer is HfO2, and the thickness is 1-5 nanometers;

[0010] Preferably, the material of the third gate dielectric layer is BN, and the thickness is 6-8 nanometers;

[0011] Preferably, the material of the gate channel layer is selected from MoS2, WS2, WSe2;

[0012] Preferably, the materials of the thick source electrode and the thick drain electrode layer are selected from Cr, Ti, Sb, Au, Pt, and the thickness is 80-160 nanometers;

[0013] Preferably, the materials of the thin source electrode and the thin drain electrode layer are selected from Cr, Ti, Sb, Au, Pt, and the thickness is 15-50 nanometers;

[0014] The present invention also provides a preparation method for the ultra-short channel high-speed non-volatile flash memory device. Specifically, the feature length is reduced by designing the atomic-level thin channel and gate stack, thereby promoting the size scaling of the device; the tunneling barrier is reduced by energy band design and van der Waals stacking of high-quality interfaces to achieve a programming / erasing speed and non-volatile characteristics at the nanosecond level; the short channel of the device is realized by a two-step process of vertical deposition and inclined deposition, and the channel length is controlled by changing the electrode thickness and deposition angle; the specific steps are as follows:

[0015] (1) Define the gate electrode pattern and position on the insulator substrate by using photolithography technology, and deposit the gate electrode by using physical vapor deposition and other technologies;

[0016] (2) Deposit a first dielectric layer on a substrate with a patterned gate electrode using techniques such as atomic layer deposition;

[0017] (3) Deposit a second dielectric layer on the first dielectric layer using techniques such as atomic layer deposition;

[0018] (4) Deposit or transfer a third dielectric layer onto the second dielectric layer using atomic layer deposition or transfer methods;

[0019] (5) Transfer the channel onto the third dielectric layer and define the channel pattern and position using techniques such as photolithography and etching;

[0020] (6) Fabricate a thick source and a thick drain, which are realized by a process similar to that for the gate electrode. Note that, due to the non - use of advanced lithography, the channel length obtained after this step is relatively large (e.g., at the micron level);

[0021] (7) Fabricate a thin source and a thin drain, which are realized by a process similar to that for the gate electrode. Note that when depositing the thin source and thin drain, there is an inclination angle between the deposition direction and the normal direction of the substrate surface. Thus, the thick source and drain will block partial coverage of the thin source and drain on the channel, forming a gap and determining the final channel length. By adjusting the thickness of the thick source and drain and the inclination angle, the final channel length can be adjusted. The final channel length is the product of the thickness of the thick source and drain and the tangent value of the inclination angle during the deposition of the thin layer metal.

[0022] In the preparation method of the ultra - short channel high - speed non - volatile flash memory device of the present invention, preferably, the thick source and thick drain layers are one of Cr, Ti, Sb, Au, Pt and any combination thereof, with a thickness of 80 - 160 nanometers;

[0023] In the preparation method of the ultra - short channel high - speed non - volatile flash memory device of the present invention, preferably, the thin source and thin drain layers are one of Cr, Ti, Sb, Au, Pt and any combination thereof, with a thickness of 15 - 50 nanometers;

[0024] In the preparation method of the ultra - short channel high - speed non - volatile flash memory device of the present invention, preferably, the deposition direction of the thick source and thick drain during fabrication is perpendicular to the substrate surface;

[0025] In the present invention, for the short channel, its length is sub - 10 nanometers (i.e., less than 10 nanometers, such as 6 - 10 nanometers);

[0026] In the preparation method of the ultra - short channel high - speed non - volatile flash memory device of the present invention, preferably, the deposition direction of the thin source and thin drain makes an inclination angle of 1° - 10° with the normal of the substrate surface.

[0027] By combining the excellent properties of two-dimensional materials with the vertical-inclined two-step deposition method of source / drain electrodes, the present invention provides a super-short channel high-speed non-volatile memory device based on two-dimensional materials, and the realization of the short channel does not rely on advanced lithography technology. This memory has a channel length of less than 10 nanometers, a programming speed in the nanosecond range, and a data retention ability of more than ten years, which can promote the development of advanced storage technologies with high integration, high speed, and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 FIG. is a schematic diagram of the device structure of a super-short channel high-speed non-volatile flash memory based on two-dimensional materials.

[0029] Figure 2 FIG. is a schematic diagram of the energy band structure of the device.

[0030] Figure 3 FIG. is a schematic diagram of the preparation process of the device.

[0031] Figure 4 FIG. is a scanning electron microscope (SEM) characterization diagram of a sub-10 nanometer channel.

[0032] In the figure, the reference numeral 1 for the material is the first dielectric layer, 2 is the second dielectric layer, 3 is the third dielectric layer, 4 is the channel layer, 5 is the substrate, 6 is the gate, 7 is the thick source electrode, 8 is the thick drain electrode, 9 is the thin source electrode, and 10 is the thin drain electrode. DETAILED DESCRIPTION OF THE INVENTION

[0033] The present invention will be further described below with reference to the accompanying drawings through embodiments.

[0034] In the following description, the orientation or positional relationship indicated by terms such as "upper", "lower", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation.

[0035] In addition, regarding many details, such as the structure, materials, dimensions, processing technology, etc. of the device, so that those of ordinary skill in the art can understand, the present invention may also be implemented without following these specific details. Unless otherwise specified, each part of the device may be composed of materials known to those skilled in the art, or materials with similar functions developed in the future may be used.

[0036] Figure 1 And Figure 2 respectively show a schematic diagram of the device structure and a schematic diagram of the energy band structure of a super-short channel high-speed non-volatile flash memory based on two-dimensional materials. Figure 3 In, a preparation method of a super-short channel high-speed non-volatile flash memory based on two-dimensional materials and a schematic diagram of the structure of each step are shown. The specific steps are as follows:

[0037] (1) Define the gate pattern and position on the insulating substrate using photolithography technology, deposit the gate electrode by techniques such as physical vapor deposition, and obtain the patterned metal gate using the lift-off process;

[0038] (2) Deposit the first dielectric layer Al2O3 (with a thickness of 15 nanometers) as the blocking layer in the flash memory gate stack on the substrate with the patterned gate electrode by techniques such as atomic layer deposition;

[0039] (3) Deposit the second dielectric layer HfO2 (with a thickness of 2 nanometers) as the charge trapping layer in the flash memory gate stack on the Al2O3 dielectric layer by techniques such as atomic layer deposition;

[0040] (4) Transfer the third dielectric layer BN (with a thickness of 7 nanometers) as the tunneling layer in the flash memory gate stack on the second dielectric layer using the transfer method;

[0041] (5) Transfer the channel material MoS2 onto the third dielectric layer BN using the transfer method, and define the channel pattern and position using techniques such as photolithography and etching;

[0042] (6) Fabricate the thick source and thick drain with a thickness of 120 nanometers, which is achieved by a similar method as that for the gate electrode. In this step, during the deposition of the source and drain metals, the deposition direction is perpendicular to the substrate surface. Since advanced lithography is not used, the channel length obtained after this step is relatively large (e.g., in the micron range);

[0043] (7) Fabricate the thin source and thin drain with a thickness of 20 nanometers, which is achieved by a similar method as that for the gate electrode. In this step, when depositing the thin source and thin drain, there is an inclination angle (e.g., 3°) between the deposition direction and the normal direction of the substrate surface. Thus, the thick source and drain will block partial coverage of the thin source and thin drain on the channel, forming a gap and determining the final channel length. By adjusting the thickness of the thick source and thick drain and the inclination angle during the deposition of the thin metal, the final channel length can be adjusted. The final channel length is the product of the thickness of the thick source and thick drain and the tangent value of the inclination angle. With the above parameters in this embodiment, a sub-10-nanometer channel length can be achieved. Figure 4 The SEM characterization diagram of the obtained sub-10-nanometer channel length is shown.

[0044] For the ultra-short channel high-speed non-volatile flash memory device based on two-dimensional materials of the present invention, its specific programming and erasing operations are described as follows: For the programming operation, by applying a positive voltage pulse to the gate while keeping the source and drain grounded, a large amount of charges in the channel are injected into the charge trapping layer, thereby achieving high-speed programming at the nanosecond level for the state "1". At this time, the gate voltage is removed, and the charges are trapped in the trapping layer, realizing non-volatile storage of data. For the erasing operation, by applying a negative voltage pulse to the gate while keeping the source and drain grounded, the charges in the charge trapping layer are extracted and enter the channel, thereby achieving high-speed erasing at the nanosecond level for the state "0".

Claims

1. A super-short channel non-volatile flash memory device based on two-dimensional materials, characterized in that, Comprising: An insulator substrate; A gate electrode located on the surface of the insulating substrate; A first dielectric layer covering the gate electrode and the insulating substrate as a barrier layer; A second dielectric layer covering the first dielectric layer as a charge trapping layer; A third dielectric layer covering the second dielectric layer as a tunneling layer; A channel layer located on the surface of the third dielectric layer; A thick source layer and a thick drain layer located on the channel layer; A thin source layer and a thin drain layer located on the channel layer, the thick source layer, and the thick drain layer; For the first to third dielectric layers, by selecting the material dielectric constant and thickness, the device characteristic length is reduced to miniaturize the size, optimize the capacitance matching of the flash memory gate stack, and improve the tunneling efficiency by enhancing the electric field distribution, thereby increasing the programming speed; The short channel has a length of less than 10 nanometers.

2. The non-volatile flash memory device according to claim 1, characterized in that, The gate electrode material is selected from Cr, Ti, Sb, Au, Pt.

3. The non-volatile flash memory device according to claim 1, wherein: The material of the first gate dielectric layer is Al2O3, and the thickness is 10 - 20 nanometers; The material of the second gate dielectric layer is HfO2, and the thickness is 1 - 5 nanometers; The material of the third gate dielectric layer is BN, and the thickness is 6 - 8 nanometers; The material of the gate channel layer is selected from MoS2, WS2, WSe2.

4. The non-volatile flash memory device according to claim 1, wherein The material of the thick source layer and the thick drain layer is selected from Cr, Ti, Sb, Au, Pt, and the thickness is 80 - 160 nanometers.

5. The non-volatile flash memory device according to claim 1, wherein The material of the thin source layer and the thin drain layer is selected from Cr, Ti, Sb, Au, Pt, and the thickness is 15 - 50 nanometers.

6. The manufacturing method of the non-volatile flash memory device according to any one of claims 1-5, characterized in that, Specifically, the characteristic length is reduced through the design of the atomic-level thin channel and the gate stack, thereby promoting the miniaturization of the device size; The tunneling barrier is reduced through energy band design and van der Waals stacking of high-quality interfaces to achieve a programming / erasing speed of the order of 10 nanoseconds and non-volatile characteristics; The short channel of the device is realized through a two-step process of vertical deposition and inclined deposition, and the channel length is regulated by changing the electrode thickness and the deposition angle; The specific steps are as follows: (1) Define the gate pattern and position on the insulating substrate using photolithography technology, and deposit the gate electrode using physical vapor deposition technology; (2) Deposit the first dielectric layer on the substrate with the patterned gate electrode using atomic layer deposition technology; (3) Deposit the second dielectric layer on the first dielectric layer using atomic layer deposition technology; (4) Deposit or transfer the third dielectric layer onto the second dielectric layer using atomic layer deposition or transfer methods; (5) Transfer the channel onto the third dielectric layer using a transfer method, and define the channel pattern and position using photolithography and etching technologies; (6) Fabricate the thick source and thick drain using a process similar to that for fabricating the gate electrode; (7) Fabricate the thin-layer source and the thin-layer drain using a process similar to that for fabricating the gate electrode; here, when depositing the thin-layer source and the thin-layer drain, the deposition direction is kept at an inclined angle with respect to the normal direction of the substrate surface, so that the thick-layer source and drain block partial coverage of the thin-layer source and drain on the channel, forming a gap and determining the final channel length; by adjusting the thickness of the thick-layer source and drain and the inclined angle, the adjustment of the final channel length is achieved; the final channel length is the product of the thickness of the thick-layer source and drain and the tangent value of the inclined angle during the deposition of the thin-layer metal.

7. The preparation method according to claim 6, characterized in that, The inclined angle is 1° - 10°.

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