Low-substrate leakage current LIGBT (Lateral Insulated Gate Bipolar Translator) device with PN junction accumulation layer and preparation method

Abstract

The invention discloses a low-substrate leakage current LIGBT device with a PN junction accumulation layer and a preparation method thereof, and mainly solves the problems of substrate hole leakage, low withstand voltage and long turn-off time of an existing LIGBT device. The semiconductor device comprises a P-type substrate, an N-type drift region, a P + source region, an N + source region, a P-type base region, an N-type buffer region, a P + drain region, a source electrode, a grid electrode, a drain electrode and a substrate electrode, the P-type drift region and an accumulation dielectric layer are sequentially arranged above the N-type drift region to form a P-type and N-type longitudinal alternating drift region structure, the two sides of the P-type drift region are in contact with the P-type base region and the N-type buffer region respectively, and the P-type base region and the N-type buffer region are in contact with the substrate electrode. The hole leakage of the substrate is relieved; and two P-type regions and two N-type regions are arranged above the accumulation dielectric layer to form an accumulation layer comprising forward and reverse PN junctions, so that the device is prevented from being broken down in advance during forward conduction and forward blocking. The invention has the advantages of small electric leakage of the substrate, high voltage resistance, low loss and good heat dissipation performance, and can be used as a high-power device in electronic equipment and a system.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a low substrate leakage current LIGBT device and a preparation method thereof, which can be used as high-power devices in electronic devices and systems. Background Art

[0002] The laterally insulated gate bipolar transistor (LIGBT), as a power semiconductor device that combines the high integration, easy driving, and low power consumption characteristics of MOS transistors, as well as the strong current-carrying ability and high output power advantages of BJTs, plays a key role in electronic devices. Its structural design enables it to have high reliability under high voltage and high current conditions and is suitable for hard-switching applications with inductive loads, such as inverter bridge circuits, converter circuits, and chopper circuits. It can also be integrated with logic control circuits, drive circuits, etc. on the same chip and is suitable for intelligent power integrated circuits. However, the LIGBT faces a significant challenge: a large number of holes are injected from the P+ region near the drain into the drift region, and the potential difference between the drain and the substrate electrode provides a path for the injected holes to flow into the substrate. The high hole substrate leakage current will lead to additional power consumption, reduce the overall efficiency, limit its application in high-frequency and high-temperature fields, increase the internal heat of the device, thereby affecting its long-term reliability and lifespan, and also lead to a decrease in the switching speed, increase the switching loss, and affect the performance of the device in high-frequency applications. To isolate or reduce the substrate leakage current, researchers have successively invented structures such as SOI-LIGBT and double-layer partial SOI-LIGBT. However, the introduction of the buried oxide layer is not conducive to integration, resulting in limited application scope, poor heat dissipation, and high process cost.

[0003] In addition, although the participation of holes in conduction can improve the conduction performance, their accumulation in the drift region will cause serious current tailing phenomenon when the LIGBT is turned off, slowing down the turn-off speed of the device. Therefore, reducing the hole substrate leakage current and balancing the trade-off relationship between the conduction voltage drop and the turn-off speed of the device are important research directions for LIGBTs. Currently, researchers are actively exploring various solutions, such as optimizing the device structure, improving the process technology, balancing parameters, and using new materials and new structures to solve the problems of hole substrate leakage current and turn-off speed faced by LIGBTs, in order to promote its application and development in a wider range of fields.

[0004] The patent document with the application number CN202010698250.2 discloses a Schottky accumulation layer silicon carbide lateral field effect transistor and its manufacturing method. This device effectively combines a silicon carbide Schottky accumulation layer and a field plate. The silicon carbide Schottky accumulation layer can generate electrons with a relatively high concentration in the drift region to reduce the on-resistance of the device, while the field plate can effectively reduce the peak electric field at the gate edge, thereby increasing the breakdown voltage of the device. However, due to the high hardness of the silicon carbide material it uses and the great processing difficulty, which requires complex processes such as high temperature and high-energy ion implantation, the production cost of the device prepared using a silicon carbide substrate is relatively high.

[0005] The patent document with the application number CN201810863342.4 discloses a thin SOILIGBT structure with a junction drift region structure. When this structure conducts in the forward direction, the sidewalls of the concave groove block the holes in the drift region from being extracted by the gate, increasing the hole concentration at the gate end of the drift region. At the same time, it also promotes the injection of electrons into the drift region, significantly increasing the carrier concentration at the gate end. However, due to the parameter limitations of the high aspect ratio of the concave groove of this device, the accuracy and stability requirements for the processing equipment are extremely high, resulting in a high degree of process complexity. And although this structure uses SOI material to effectively isolate the substrate leakage current of the device, it is limited in the field of large-scale silicon-based integration, and the disadvantage of its poor heat dissipation is also prone to cause heat accumulation inside the device, affecting the normal working performance of the device. Summary of the Invention

[0006] The purpose of the present invention is to address the above deficiencies of the prior art and propose a low-substrate leakage current LIGBT structure with a PN junction accumulation layer and a preparation method to effectively control the flow of holes and electrons, reduce the substrate leakage current, improve the contradictory relationship between the on-voltage drop and the turn-off loss, and enhance the breakdown voltage and performance of the device.

[0007] The technical idea to achieve the above purpose is as follows: By forming a P-type drift region, an N-type drift region, and a P-type substrate structure from top to bottom to alleviate substrate hole leakage and improve the breakdown voltage; by forming an electron thin layer connecting the source and drain on the surface of the P-type drift region through a PN junction accumulation layer to reduce the on-voltage drop of the device. Also, because there is a pair of PN junctions and reverse PN junctions at both ends of the PN junction accumulation layer, it can prevent the device from breaking down prematurely during forward conduction and forward blocking, further improving the breakdown voltage of the device; by changing the Schottky contact barrier of the drain to regulate the injection concentration of holes and electrons; by using the P-type drift region to improve the switching response speed of the device.

[0008] According to the above idea, the technical solution of the present invention is as follows:

[0009] 1. A low substrate leakage current LIGBT device with a PN junction accumulation layer, comprising: a P-type substrate 1, an N-type drift region 2, a P+ source region 4, an N+ source region 5, a P-type base region 6, an N-type buffer region 7, a P+ drain region 8, a source electrode 14, a gate electrode 15, a drain electrode 16, and a substrate electrode 17, characterized in that:

[0010] A P-type drift region 3 and an accumulation dielectric layer 9 are sequentially arranged above the N-type drift region 2 to form a drift region structure with longitudinal alternation of P-type and N-type, and both sides of the P-type drift region 3 are respectively in contact with the P-type base region 6 and the N-type buffer region 7 to relieve substrate hole leakage;

[0011] Four regions, namely a first P-type region 10, a first N-type region 11, a second N-type region 12, and a second P-type region 13, are sequentially arranged in parallel above the accumulation dielectric layer 9 to form a PN junction accumulation layer, and the first N-type region 11 is adjacent to the second N-type region 12, the first P-type region 10 is adjacent to the first N-type region 11, and the second P-type region 13 is adjacent to the second N-type region 12, so as to form a PN junction and a reverse PN junction at both ends of the accumulation layer, avoid premature breakdown of the device during forward conduction and forward blocking, and improve the voltage withstand capacity of the device.

[0012] Further, for the P-type substrate 1, its material is any one of silicon, germanium, gallium arsenide, and silicon carbide, and its doping concentration is 1×10 14 cm -3 ~5×10 14 cm -3 ; the N-type drift region 2 is located in the upper part of the P-type substrate 1, and its doping concentration is 8×10 14 cm -3 ~1×10 15 cm -3 ; the P-type drift region 3 is located in the upper part of the N-type drift region 2, and its doping concentration is 4×10 14 cm -3 ~5×10 14 cm -3 ; the substrate electrode 17 is located on the back surface of the P-type substrate 1.

[0013] Further, the accumulation dielectric layer 9 is made of silicon dioxide or a high-K material, and its thickness is 0.04 - 0.1 micrometer; the thicknesses of the first P-type region 10, the first N-type region 11, the second N-type region 12, and the second P-type region 13 are 0.5 - 3 micrometers, and the doping concentrations of both the first P-type region 10 and the second P-type region 13 are 1×10 18 cm -3 ~1×10 20 cm -3 ; the doping concentration of the first N-type region 11 is 1×10 13 cm -3 ~7×1015 cm -3 ; The doping concentration of the second N-type region 12 is 1×10 15 cm -3 ~5×10 16 cm -3 .

[0014] Furthermore, the P+ source region 4 is adjacent to the P-type base region 6, and the doping concentration of the P+ source region 4 is 1×10 19 cm -3 ~1×10 20 cm -3 , the doping concentration of the P-type base region 6 is 1×10 16 cm -3 ~1×10 17 cm -3 ; The gate 15 is located on the upper surface of a part of the first P-type region 10 directly corresponding to the P-type base region 6; The N+ source region 5 is located in the upper partial region of the P+ source region 4, and its doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 ; The source electrode 14 covers the surfaces of the P+ source region 4 and the N+ source region 5; The N-type buffer region 7 is located on one side of the P-type drift region 3, its lower boundary does not exceed the lower boundary of the P-type drift region 3, and its doping concentration is 6×10 16 cm -3 ~2×10 17 cm -3 ; The P+ drain region 8 is located in the upper partial region of the N-type buffer region 7, and its doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 ; The drain electrode 16 is located on the upper surfaces of a part of the P+ drain region 8 and the second P-type region 13, and is in Schottky contact with the material surface, and the contact barrier is 5.03 eV.

[0015] 2. A method for manufacturing the device according to claim 1, characterized in that it comprises the following steps:

[0016] 1) Deposit metal on the back surface of the selected P-type substrate 1 to form a substrate electrode 17;

[0017] 2) Place the P-type substrate 1 deposited with the substrate electrode in a reaction chamber, and epitaxially grow an N-type epitaxial layer on the front surface of the P-type substrate 1 by homoepitaxy technology to form an N-type drift region 2;

[0018] 3) Epitaxially grow a P-type epitaxial layer on the front surface of the N-type drift region 2 by homoepitaxy technology to form a P-type drift region 3;

[0019] 4) In the P-type drift region 3, ion implantation is sequentially performed to form a P-type base region 6, a P+ source region 4, and an N-type buffer region 7, and the lattice damage is repaired by rapid thermal annealing;

[0020] 5) Ion implantation is performed on the surface of the P-type base region 6 to form an N+ source region 5, and ion implantation is performed on the surface of the N-type buffer region 7 to form a P+ drain region 8, and the lattice damage is repaired by rapid thermal annealing;

[0021] 6) A polysilicon material with a thickness of 0.5 to 3 microns is selected, a dielectric layer 9 is grown and accumulated on its bottom surface, and then it is bonded to the surface of the sample through a bonding process;

[0022] 7) Ion implantation is performed on the upper surface of the polysilicon to form a first P-type region 10, a first N-type region 11, a second N-type region 12, and a second P-type region 13, and the lattice damage is repaired by rapid thermal annealing, constituting

[0023] 8) Metal is deposited in the regions of the P+ source region 4 and the N+ source region 5 to form a source electrode 14; metal is deposited on the surface of the first P-type region 10 to form a gate electrode 15, and metal is deposited on the surfaces of the P+ drain region 8 and the second P-type region 13 to form a drain electrode 16;

[0024] 9) A passivation layer is deposited on the surface of the sample after the above steps and chemical mechanical polishing is performed to make the surface flat, completing the device fabrication.

[0025] Compared with the prior art, the present invention has the following advantages:

[0026] 1. Since the PN junction formed in the P-type drift region and the N-type drift region of the present invention will generate a built-in electric field opposite to the hole substrate leakage current, it can block the movement of holes towards the substrate during the normal operation of the device. At the same time, since the longitudinal distance between the N-type buffer region and the N-type drift region is close and its concentration is higher than that of the P-type drift region, the electric potentials of the N-type buffer region and the N-type drift region are similar and higher than that of the P-type drift region, which can further inhibit the movement of holes towards the substrate and significantly alleviate the substrate leakage.

[0027] 2. Since the PN junction accumulation layer forms an electron thin layer connecting the source electrode and the drain electrode on the surface of the P-type drift region during the normal operation of the device, the present invention can keep the device at a low on-state voltage drop. Also, since there is a pair of PN junctions and reverse PN junctions at both ends of the PN junction accumulation layer, the device can be prevented from premature breakdown during forward conduction and forward blocking, improving the device breakdown voltage.

[0028] 3. Since a P-type drift region is provided in the present invention, electrons can recombine in the P-type drift region during the turn-off process, thereby accelerating the disappearance of electrons and further optimizing the turn-off performance of the device.

[0029] 4. Since various metal materials with different work functions can be selected as the drain metal or the P+ drain region can be doped with different concentrations in the present invention, the Schottky contact barrier of the drain can be changed, so as to regulate the injection concentrations of holes and electrons.

[0030] 5. Since an N-type buffer region is introduced below the P+ drain region in the present invention, it can not only receive electrons flowing from the source to the drain, but also modulate the lateral and longitudinal electric fields of the device, further improving the breakdown voltage capability of the device.

[0031] The test results show that the present invention not only alleviates the contradictory relationship between the turn-off characteristics and the on-state loss of the device, realizes a good compromise between the two, but also alleviates the substrate hole leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a structural diagram of the low substrate leakage current LIGBT device with a PN junction accumulation layer according to the present invention;

[0033] Figure 2 is for the fabrication of the present invention Figure 1 a schematic flow chart of the implementation of the device;

[0034] Figure 3 is a distribution diagram of the hole current density along the longitudinal direction when the LIGBT device of the present invention is in the forward conduction state;

[0035] Figure 4 is a schematic diagram comparing the breakdown characteristics of the LIGBT device of the present invention with those of the traditional LIGBT device;

[0036] Figure 5 is a schematic diagram comparing the turn-off characteristics of the LIGBT device of the present invention with those of the traditional LIGBT device. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] The following further elaborates on the embodiments and effects of the present invention with reference to the accompanying drawings.

[0038] Refer to Figure 1 , the low substrate leakage current LIGBT structure with a PN junction accumulation layer according to the present invention includes: a P-type substrate 1, an N-type drift region 2, a P-type drift region 3, a P+ source region 4, an N+ source region 5, a P-type base region 6, an N-type buffer region 7, a P+ drain region 8, an accumulation dielectric layer 9, a first P-type region 10, a first N-type region 11, a second N-type region 12, and a second P-type region 13, a source electrode 14, a gate electrode 15, a drain electrode 16, and a substrate electrode 17, wherein:

[0039] The P-type substrate 1 is made of any one of silicon, germanium, and silicon carbide, and its doping concentration is 1×10 14 cm -3 ~5×10 14 cm -3;

[0040] The substrate electrode 17 is located on the back surface of the P-type substrate 1;

[0041] The N-type drift region 2 is located above the P-type substrate 1, and its doping concentration is 8×10 14 cm -3 ~1×10 15 cm -3 ;

[0042] The P-type drift region 3 is located above the N-type drift region 2, and its doping concentration is 4×10 14 cm -3 ~5×10 14 cm -3 ;

[0043] The P-type base region 6 is located on one side of the P-type drift region 3, and its doping concentration is 1×10 16 cm -3 ~1×10 17 cm -3 ;

[0044] The P+ source region 4 is located on the other side of the P-type base region 6, and its doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 ;

[0045] The N+ source region 5 is located in the upper partial area of the P+ source region 4, and its doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 ;

[0046] The N-type buffer region 7 is located on the other side of the P-type drift region 3, and its doping concentration is 6×10 16 cm -3 ~2×10 17 cm -3 ;

[0047] The P+ drain region 8 is located in the upper partial area of the N-type buffer region 7, and its doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 ;

[0048] The accumulation dielectric layer 9 is located above the P-type drift region 3, its thickness is 0.04 - 0.1 micrometers, and its material is silicon dioxide or high-K dielectric;

[0049] The first P-type region 10, the first N-type region 11, the second N-type region 12, and the second P-type region 13 are sequentially and parallelly disposed above the accumulation dielectric layer 9, and have a thickness of 0.5 to 3 micrometers. The first N-type region 11 is adjacent to the second N-type region 12, and the doping concentration of the first N-type region 11 is 1×10 13 cm -3 ~7×10 15 cm -3 , and the doping concentration of the second N-type region 12 is 1×10 18 cm -3 ~1×10 20 cm -3 ; the first P-type region 10 is adjacent to the first N-type region 11, the second P-type region 13 is adjacent to the second N-type region 12, and the doping concentrations of the first P-type region 10 and the second P-type region 13 are both 1×10 18 cm -3 ~1×10 20 cm -3 ;

[0050] The source electrode 14 is located on the surfaces of the P+ source region 4 and the N+ source region 5, and covers the regions of the P+ source region 4 and the N+ source region 5;

[0051] The gate electrode 15 is located on the upper surface of a part of the first P-type region 10 that corresponds exactly to the P-type base region 6;

[0052] The drain electrode 16 is located on the surface of the P+ drain region 8 and a part of the upper surface of the second P-type region 13, and is in Schottky contact with the material surface, and the contact barrier is 5.03 eV.

[0053] Referring to Figure 2 , the present invention provides three embodiments for manufacturing Figure 1 devices:

[0054] Embodiment 1: Fabricate a low substrate leakage current LIGBT structure on a P-type silicon substrate with a silicon dioxide accumulation dielectric layer thickness of 0.1 micrometer, a PN junction accumulation layer thickness of 2 micrometers, and a doping concentration of the N-type buffer region of 6×10 16 cm -3 .

[0055] Step 1, fabricate a P-type silicon substrate, and deposit metal Al on its back surface to form a substrate electrode 17, as Figure 2 (a).

[0056] 1.1) Select a high-purity single-crystal silicon wafer, first use acetone, then use a sulfuric acid and hydrogen peroxide mixture to remove surface organic substances and particles, then use deionized water to wash away residual chemical substances, and finally dry the substrate;

[0057] 1.2) Place liquid trimethyl borate (TMB) into an evaporator, and heat the evaporator to 40 °C to evaporate the liquid boron source to prepare a doping gas;

[0058] 1.3) Place the cleaned silicon wafer in a high-temperature diffusion furnace, and simultaneously introduce N2 with a flow rate of 2 L / min, O2 with a flow rate of 0.5 L / min, and TMB vapor with a flow rate of 0.2 L / min, and heat to 1000 °C for 1 hour to promote the entry of boron atoms into the interior of the silicon wafer. After the diffusion is completed, place the sample in a tube annealing furnace, heat the annealing furnace to 900 °C, and then introduce N2 with a flow rate of 2 L / min for 20 minutes to activate the boron atoms and repair the lattice damage to obtain a P-type silicon substrate 1;

[0059] 1.4) Fix the P-type silicon substrate on the sample stage of the evaporation coater with the back facing up, and then evacuate the evaporation chamber to a vacuum degree of 2×10 -6 Torr, and heat to 150 °C to remove the water vapor and impurities adsorbed on the surface;

[0060] 1.5) Place high-purity Al metal into the tungsten wire evaporation source of the evaporation coater, heat the evaporation source to 1300 °C, and keep it for 16 minutes to evaporate the metal and deposit it on the back of the substrate to form a substrate electrode 17.

[0061] Step 2, epitaxially grow an N-type epitaxial layer on the front surface of the P-type silicon substrate to form an N-type drift region, as shown in Figure 2 (b).

[0062] 2.1) Place the P-type silicon substrate with the deposited substrate electrode in a horizontal epitaxial furnace, with its front facing up, and then introduce H2 with a flow rate of 50 L / min, and heat the epitaxial furnace to 1200 °C to form a reducing atmosphere to prevent the oxidation of the substrate surface;

[0063] 2.2) Simultaneously introduce silicon source gases of SiCl4, SiHCl3, and SiH4 with a flow rate of 40 sccm into the reaction chamber. At high temperature, the silicon atoms released by the thermal decomposition of the silicon source gases are deposited on the surface of the substrate and epitaxially grow along the lattice structure of the substrate to form a single-crystalline silicon layer;

[0064] 2.3) Simultaneously introduce an N-type PH3 doping gas into the silicon source gases. After the doping gas decomposes, phosphorus P atoms are released and enter the epitaxial layer to form an N-type drift region 2.

[0065] Step 3, epitaxially grow a P-type epitaxial layer above the N-type drift region to form a P-type drift region 3, as shown in Figure 2 (c).

[0066] 3.1) Place the sample with the epitaxially grown N-type drift region in a horizontal epitaxial furnace, heat the epitaxial furnace to 1150 °C and introduce H2 with a flow rate of 50 L / min to form a reducing atmosphere to prevent the oxidation of the substrate surface;

[0067] 3.2) Simultaneously introduce the silicon source gases of SiCl4, SiHCl3, and SiH4 at 40 sccm into the reaction chamber. At high temperature, the silicon atoms released by the thermal decomposition of the silicon source gases deposit on the surface of the N-type drift region and epitaxially grow along the lattice structure of the N-type drift region to form a single-crystalline silicon layer;

[0068] 3.3) Simultaneously introduce the P-type BF3 doping gas into the silicon source gases. After the doping gas decomposes, boron B atoms are released and enter the epitaxial layer to form the P-type drift region 3.

[0069] Step 4, sequentially perform ion implantation in the P-type drift region to form a P-type base region, a P+ source region, and an N-type buffer region, as shown in Figure 2 (d).

[0070] 4.1) Place the sample with the epitaxially grown P-type drift region in an ion implanter. Use a high-energy boron ion beam with a beam current of 1 mA, an implantation energy of 42.5 keV, and a dose of 1.92×10 13 ions / cm -2 to bombard the surface of the material to implant boron ions. The implantation area is 16 μm 2 , and the duration is 0.49 ns to form a P-type base region 6 with a concentration of 2×10 16 cm -3 ;

[0071] 4.2) Use a high-energy boron ion beam with a beam current of 1 mA, an implantation energy of 10 keV, and a dose of 9.53×10 15 ions / cm -2 to bombard and implant boron ions on the surface of the P-type base region. The implantation area is 1 μm 2 , and the duration is 15.25 ns to form a P+ source region 4 with a concentration of 1×10 20 cm -3 ;

[0072] 4.3) Use a high-energy phosphorus ion beam with a beam current of 1 mA, an implantation energy of 35 keV, and a dose of 8.94×10 13 ions / cm -2 to bombard and implant phosphorus ions on the other side surface of the P-type drift region. The implantation area is 25 μm 2 , and the duration is 3.57 ns to form an N-type buffer region 7 with a concentration of 6×10 16 cm -3 ;

[0073] Step 5, perform ion implantation on the surface of the P-type base region to form an N+ source region, and perform ion implantation on the surface of the N-type buffer region to form a P+ drain region, as shown in Figure 2 (e).

[0074] 5.1) Bombard and implant phosphorus ions with a high-energy phosphorus ion beam with a beam current of 1 mA, an implantation energy of 10 keV, and a dose of 9.53×10 15 ions / cm -2 on the right surface of the P+ source region. The implantation area is 1 μm 2 , and the duration is 15.25 ns to form an N+ source region 5 with a concentration of 1×10 20 cm -3 ;

[0075] 5.2) Bombard and implant boron ions with a high-energy boron ion beam with a beam current of 1 mA, an implantation energy of 10 keV, and a dose of 1.09×10 15 ions / cm -2 on the surface of the N-type buffer region. The implantation area is 1 μm 2 , and the duration is 1.74 ns to form a P+ drain region 8 with a concentration of 4×10 18 cm -3 .

[0076] Step 6: Select polysilicon with a thickness of 2 microns, grow a 0.1-micron accumulation dielectric layer on its lower surface, and then bond it to the surface of the sample through a bonding process, as shown in Figure 2 (f).

[0077] 6.1) Select high-purity polysilicon with a thickness of 2 μm, use RCA chemical reagents to remove surface organic substances and particles, and then use deionized water to thoroughly clean and remove residual chemical substances;

[0078] 6.2) Place the cleaned polysilicon in a CVD reaction chamber, introduce silicon source gases such as SiH4 and oxidants such as O2, deposit at 500 °C with a rate of about 50 nm / min. After 2 minutes of deposition, a 0.1-micron SiO2 dielectric layer is formed on the surface of the polysilicon. After deposition, place the polysilicon with the accumulation dielectric layer in an annealing furnace and anneal at 800 °C for 50 minutes to improve the film density and electrical properties.

[0079] 6.3) After annealing, clean the surface of the polysilicon and the accumulation dielectric layer with RCA chemical reagents to remove contaminants and particles;

[0080] 6.4) Place the sample with the formed P+ drain region and the polysilicon with the accumulation dielectric layer in a direct bonding machine. At room temperature, bring the accumulation dielectric layer into contact with the surface of the sample to achieve preliminary bonding through intermolecular forces; finally, anneal at 200 °C to form a strong Si-O-Si bonding interface between the accumulation dielectric layer and the surface of the sample.

[0081] Step 7, ion implantation is successively performed on the upper surface of the polysilicon to form a first P-type region, a first N-type region, a second N-type region, and a second P-type region, as shown in Figure 2 (g).

[0082] 7.1) Place the bonded sample in an ion implanter, and bombard and implant boron ions on the surface of the polysilicon side with a beam current of 1 mA, an implantation energy of 10 keV, and a dose of 2.7×10 15 ions / cm -2 The high-energy boron ion beam has an implantation area of 1 μm 2 , a duration of 1.74 ns, and forms a first P-type region 10 with a concentration of 1×10 19 cm -3 ;

[0083] 7.2) On the other surface of the polysilicon, bombard and implant boron ions with a beam current of 1 mA, an implantation energy of 10 keV, and a dose of 2.7×10 15 ions / cm -2 The high-energy boron ion beam has an implantation area of 1 μm 2 , a duration of 1.74 ns, and forms a second P-type region 13 with a concentration of 1×10 19 cm -3 ;

[0084] 7.3) On the other surface of the first P-type region, bombard and implant phosphorus ions with a beam current of 1 mA, an implantation energy of 50 keV, and a dose of 1.5×10 12 ions / cm -2 The high-energy phosphorus ion beam has an implantation area of 1600 μm 2 , a duration of 3.84 ms, and forms a first N-type region 11 with a concentration of 5×10 14 cm -3 ;

[0085] 7.4) On the other surface of the second P-type region, bombard and implant phosphorus ions with a beam current of 1 mA, an implantation energy of 10 keV, and a dose of 2.7×10 15 ions / cm -2 The high-energy phosphorus ion beam has an implantation area of 1 μm 2 , a duration of 1.74 ns, and forms a second N-type region 12 with a concentration of 1×10 19 cm -3 .

[0086] Step 8, fabricate electrodes, as shown in Figure 2 (h).

[0087] 8.1) Place the sample after ion implantation into a thermal oxidation furnace to form a lead hole oxide film. After cleaning with chemical reagents, apply photoresist, expose, develop, and etch to form a metal deposition area.

[0088] 8.2) Fix the sample with the metal deposition area divided on the sample stage of the evaporation coater with the back facing up. Then evacuate the evaporation chamber to a vacuum degree of 2×10 -6 Torr, and heat to 150 °C to remove the water vapor and impurities adsorbed on the surface. Place high-purity Al metal into the tungsten wire evaporation source of the evaporation coater, heat the evaporation source to 1300 °C, and keep it for 16 minutes to evaporate the metal and deposit it on the surface of the area between the P+ source region and the N+ source region to form the source electrode 14. At the same time, deposit it on the upper surface of a part of the first P-type region 10 corresponding exactly to the P-type base region 6.

[0089] 8.3) Continue to fix the sample on the sample stage of the evaporation coater with the back facing up. Then evacuate the evaporation chamber to a vacuum degree of 5×10 -6 Torr, and heat to 150 °C to remove the water vapor and impurities adsorbed on the surface. Place high-purity Ni metal into the tungsten wire evaporation source of the evaporation coater, heat the evaporation source to 1600 °C, and keep it for 10 minutes to evaporate the metal and deposit it on the surfaces of the P+ drain region and the second P-type region to form the Schottky drain electrode 16.

[0090] Step 9: Deposit a passivation layer and perform chemical mechanical polishing to complete the device fabrication.

[0091] 9.1) Place the sample after depositing the electrodes into the PECVD reaction chamber, and simultaneously introduce the reaction gases SiH4, NH3, and N2O. Apply a radio frequency power of 2000 W at 300 °C to decompose the Si atoms and N atoms to deposit the passivation layer Si3N4 on the surface of the sample.

[0092] 9.2) Perform chemical mechanical polishing on the sample with the passivation layer deposited:

[0093] First, fix the sample on the polishing head of the polishing machine to ensure that its surface is parallel to the polishing pad. The polishing liquid made by mixing abrasive particles SiO2, chemical reagent H2O2, pH regulator, dispersant and other components evenly is sprayed on the polishing pad, so that after the polishing pad contacts the surface of the sample, the H2O2 in the polishing liquid softens the surface through chemical action.

[0094] Then apply pressure to the polishing pad to make it rotate, so that the SiO2 in the polishing liquid ensures that the surface of the sample becomes flat through mechanical action.

[0095] Finally, clean the polished sample with deionized water and cleaning agent to remove the residual polishing liquid and complete the device fabrication.

[0096] Embodiment 2: A low substrate leakage current LIGBT structure with a PN junction accumulation layer is fabricated on a P-type germanium substrate. The thickness of the high-K dielectric accumulation layer is 0.07 micrometers, the thickness of the PN junction accumulation layer is 1.5 micrometers, and the doping concentration of the N-type buffer region is 8×10 16 cm -3 .

[0097] Step 1: Use germanium material as the P-type substrate of the device, and deposit metal Ti on its back to form the substrate electrode 17, as shown in Figure 2 (a).

[0098] Select a high-purity single-crystal germanium wafer. First, use acetone, then use a mixed solution of sulfuric acid and hydrogen peroxide to remove surface organic substances and particles. Then, use deionized water to wash and remove residual chemical substances. Finally, dry the substrate;

[0099] Put liquid trimethyl borate TMB into an evaporator, and heat the evaporator to 40°C to evaporate the liquid boron source to prepare a doping gas;

[0100] Place the germanium wafer in a high-temperature diffusion furnace, and simultaneously introduce N2 with a flow rate of 2 L / min, O2 with a flow rate of 0.5 L / min, and TMB vapor with a flow rate of 0.2 L / min, and heat to 1000°C for 1 hour to push boron atoms into the interior of the germanium wafer. After the diffusion is completed, place the sample in a tube annealing furnace, heat the annealing furnace to 900°C, and then introduce N2 with a flow rate of 2 L / min for 20 minutes to activate boron atoms and repair lattice damage, obtaining the P-type germanium substrate 1;

[0101] Fix the P-type germanium substrate on the sample stage of the evaporation coater with the back facing up, and then evacuate the evaporation chamber to a vacuum degree of 3×10 -7 Torr, and heat to 150°C to remove adsorbed water vapor and impurities on the surface;

[0102] Put high-purity Ti metal into the tungsten wire evaporation source of the evaporation coater, heat the evaporation source to 1800°C, and keep it for 3 minutes to evaporate the metal and deposit it on the back of the substrate to form the substrate electrode 17;

[0103] Step 2: Epitaxially grow an N-type epitaxial layer on the front surface of the P-type substrate to form an N-type drift region, as shown in Figure 2 (b).

[0104] Place the P-type germanium substrate with the substrate electrode deposited on it face up in a quartz boat of a horizontal epitaxial furnace, heat the epitaxial furnace to 1100°C, and simultaneously introduce H2 with a flow rate of 100 L / min to form a reducing atmosphere to prevent oxidation of the substrate surface;

[0105] Then, a germanium source gas of GeH4 at 5 L / min is simultaneously introduced into the reaction chamber. At high temperature, germanium atoms released by the thermal decomposition of the germanium source gas are deposited on the substrate surface and epitaxially grow along the lattice structure of the substrate to form a single-crystalline germanium layer;

[0106] Then, an N-type PH3 doping gas at 30 sccm is simultaneously introduced into the germanium source gas. After the doping gas decomposes, phosphorus P atoms are released and enter the epitaxial layer to form an N-type drift region 2.

[0107] Step three, a P-type drift region is formed in the N-type drift region by ion implantation technology, as shown in Figure 2 (c).

[0108] Place the sample with the N-type drift region epitaxially grown face up in the quartz boat of the horizontal epitaxial furnace. Heat the epitaxial furnace to 1100 °C and simultaneously introduce H2 at 100 L / min to form a reducing atmosphere;

[0109] Then, a germanium source gas of GeH4 at 5 L / min is simultaneously introduced into the reaction chamber. At high temperature, germanium atoms released by the thermal decomposition of the germanium source gas are deposited on the substrate surface and epitaxially grow along the lattice structure of the substrate to form a single-crystalline germanium layer;

[0110] Then, a doping gas of P-type trimethylgallium and ammonia is simultaneously introduced into the germanium source gas. After the gas decomposes, gallium Ga atoms and nitrogen atoms are released and enter the epitaxial layer to form a P-type drift region 3.

[0111] Step four, a P-type base region, a P+ source region, and an N-type buffer region are sequentially formed by ion implantation in the P-type drift region, as shown in Figure 2 (d).

[0112] Place the sample with the P-type drift region epitaxially grown on the sample stage of the ion implanter. Introduce a gallium source gas into the vacuum chamber. Ionize the gas into gallium ions through an ionization source. Accelerate the ion beam under a high-voltage electric field of 42.5 KeV and bombard one side surface of the P-type drift region with a beam current of 1 mA. The injection dose is 1.92×10 13 ions / cm -2 with an injection area of 16 μm 2 and a duration of 0.49 ns of gallium ion beam to form a P-type base region 6 with a concentration of 2×10 16 cm -3 ;

[0113] On the surface of the P-type base region, bombard and inject gallium ions with a beam current of 1 mA, an injection energy of 10 KeV, a dose of 9.53×10 15 ions / cm -2 with an injection area of 1 μm 2 and a duration of 15.25 ns of high-energy gallium ion beam to form a concentration of 1×1020 cm -3 P+-type source region 4;

[0114] On the other surface of the P-type drift region, bombard and implant antimony ions with a high-energy antimony ion beam having a beam current of 1 mA, an implantation energy of 35 keV, a dose of 1×10 14 ions / cm -2 , an implantation area of 25 μm 2 , and a duration of 3.57 ns to form an N-type buffer region 7 with a concentration of 8×10 16 cm -3 .

[0115] Step Five, perform ion implantation on the surface of the P-type base region to form an N+-type source region, and perform ion implantation on the surface of the N-type buffer region to form a P+-type drain region, as shown in Figure 2 (e).

[0116] On the right surface of the P+-type source region, bombard and implant antimony ions with a high-energy antimony ion beam having a beam current of 1 mA, an implantation energy of 10 keV, a dose of 9.53×10 15 ions / cm -2 , an implantation area of 1 μm 2 , and a duration of 15.25 ns to form an N+-type source region 5 with a concentration of 1×10 20 cm -3 ;

[0117] On the surface of the N-type buffer region, bombard and implant gallium ions with a high-energy gallium ion beam having a beam current of 1 mA, an implantation energy of 10 keV, a dose of 1.09×10 15 ions / cm -2 , an implantation area of 1 μm 2 , and a duration of 1.74 ns to form a P+-type drain region 8 with a concentration of 4×10 18 cm -3 .

[0118] Step Six, grow an accumulation dielectric layer made of a high-K dielectric material with a thickness of 0.07 μm on the lower surface of the polysilicon, and bond it to the surface of the sample, as shown in Figure 2 (f).

[0119] Select high-purity polysilicon with a thickness of 1.5 μm, use RCA chemical reagents to remove surface organic substances and particles, and then use deionized water to thoroughly clean and remove residual chemical substances;

[0120] Place the cleaned polysilicon in the ALD reaction chamber. Use the precursor TEMAHf and the oxidant H2O to deposit layer by layer at 350 °C, with each cycle growing approximately 0.1 nm. The deposition pressure is 1 - 10 Torr. After 700 cycles, finally deposit a 0.07 - micron high - K thin layer on the polysilicon as the accumulation dielectric layer 9;

[0121] Put the polysilicon with the accumulation dielectric layer grown on it into a rapid thermal annealing furnace and anneal at 500 °C for 50 seconds to improve the film densification and electrical properties. After annealing, clean the surfaces of the polysilicon and the accumulation dielectric layer with RCA chemical reagents to remove contaminants and particles;

[0122] Then place the sample after forming the P + drain region and the polysilicon with the accumulation dielectric layer in a direct bonding machine. At room temperature, bring the accumulation dielectric layer into contact with the surface of the sample and achieve preliminary bonding through intermolecular forces. Finally, anneal at 300 °C to form a strong Si - O - Si bonding interface between the accumulation dielectric layer and the surface of the sample.

[0123] Step seven, sequentially perform ion implantation on the upper surface of the polysilicon to form a first P - type region, a first N - type region, a second N - type region, and a second P - type region, as shown in Figure 2 (g).

[0124] Place the bonded sample in an ion implanter. On the surface of one side of the polysilicon, bombard with a high - energy gallium ion beam with a beam current of 1 mA, an implantation energy of 10 KeV, a dose of 2.7×10 15 ions / cm -2 , an implantation area of 1 μm 2 , and a duration of 1.74 ns to implant gallium ions and form a first P - type region 10 with a concentration of 1×10 19 cm -3 ;

[0125] On the surface of the other side of the polysilicon, bombard with a high - energy gallium ion beam with a beam current of 1 mA, an implantation energy of 10 KeV, a dose of 2.7×10 15 ions / cm -2 , an implantation area of 1 μm 2 , and a duration of 1.74 ns to implant gallium ions and form a second P - type region 13 with a concentration of 1×10 19 cm -3 ;

[0126] On the surface of the other side of the first P - type region, bombard with a high - energy gallium ion beam with a beam current of 1 mA, an implantation energy of 50 KeV, a dose of 1.5×10 12 ions / cm -2 , an implantation area of 1600 μm 2, bombard with a high-energy antimony ion beam with a duration of 3.84 ms to inject antimony ions, forming a first N-type region 11 with a concentration of 5×10 14 cm -3 ;

[0127] On the other side surface of the second P-type region, bombard with a high-energy antimony ion beam with a beam current of 1 mA, an injection energy of 10 keV, a dose of 2.7×10 15 ions / cm -2 , an injection area of 1 μm 2 , and a duration of 1.74 ns to inject antimony ions, forming a second N-type region 12 with a concentration of 1×10 19 cm -3 .

[0128] Step eight, fabricate electrodes, as shown in Figure 2 (h).

[0129] Put the ion-implanted sample into a thermal oxidation furnace to form a lead hole oxide film. After cleaning with chemical reagents, then through coating, exposure, development, and etching to form a metal deposition area;

[0130] Fix the sample after dividing the metal deposition area on the sample stage of the evaporation coater with the back facing up, and then evacuate the evaporation chamber to a vacuum degree of 2×10 -6 Torr, and heat to 150 °C to remove the water vapor and impurities adsorbed on the surface; put high-purity Ti metal into the tungsten wire evaporation source of the evaporation coater, heat the evaporation source to 1300 °C, and keep it for 16 minutes to evaporate the metal and deposit it on the surface of the area between the P+ source region and the N+ source region, forming a source electrode 14, and at the same time deposit on the upper surface of a part of the first P-type region 10 corresponding to the P-type base region 6;

[0131] Continue to fix the sample on the sample stage of the evaporation coater with the back facing up, and then evacuate the evaporation chamber to a vacuum degree of 5×10 -6 Torr, and heat to 150 °C to remove the water vapor and impurities adsorbed on the surface; put high-purity Ti metal into the tungsten wire evaporation source of the evaporation coater, heat the evaporation source to 1600 °C, and keep it for 10 minutes to evaporate the metal and deposit it on the surface of the P+ drain region and the second P-type region, forming a Schottky drain electrode 16.

[0132] Step nine, deposit a passivation layer and perform chemical mechanical polishing to complete the device fabrication.

[0133] Put the sample after depositing the electrodes into the PECVD reaction chamber, and simultaneously introduce reaction gases SiH4, NH3, and N2O. Apply a radio frequency power of 1800 W at 400 °C, with a deposition rate of about 100 nm / min. After 10 minutes of deposition, form a 1-μm passivation layer Si3N4 on the surface of the sample;

[0134] Chemically mechanically polish the sample with a passivation layer deposited thereon:

[0135] First, fix the sample on the polishing head of the polishing machine to ensure that its surface is parallel to the polishing pad. The polishing liquid, which is made by uniformly mixing components such as abrasive particles SiO2, chemical reagent H2O2, pH regulator, and dispersant, is evenly sprayed on the polishing pad. After the polishing pad contacts the surface of the sample, H2O2 in the polishing liquid softens the surface through chemical action;

[0136] Then, apply pressure to the polishing pad to make it rotate, so that SiO2 in the polishing liquid ensures the surface of the sample becomes flat through mechanical action;

[0137] Finally, clean the polished sample with deionized water and cleaning agent to remove the residual polishing liquid and complete the device fabrication.

[0138] Example 3: Fabricate a low substrate leakage current LIGBT structure with a PN junction accumulation layer on a P-type silicon carbide substrate, where the thickness of the silicon dioxide accumulation dielectric layer is 0.05 microns, the thickness of the PN junction accumulation layer is 1 micron, and the doping concentration of the N-type buffer region is 1×10 17 cm -3 of the PN junction accumulation layer.

[0139] Step A: Use silicon carbide material as the P-type substrate of the device, and deposit metal Al on its back to form the substrate electrode 17, as shown in Figure 2 (a).

[0140] A1) Select a high-purity single-crystal silicon carbide wafer. First, use acetone, and then use a mixture of sulfuric acid and hydrogen peroxide to remove surface organic substances and particles. Then, use deionized water to clean and remove the residual chemical substances. Finally, dry the substrate;

[0141] A2) Put liquid trimethyl borate TMB into the evaporator, and heat the evaporator to 40°C to evaporate the liquid boron source to prepare the doping gas;

[0142] A3) Place the silicon carbide wafer in a high-temperature diffusion furnace, and simultaneously introduce N2 with a flow rate of 2 L / min, O2 with a flow rate of 0.5 L / min, and TMB vapor with a flow rate of 0.2 L / min, and heat to 1000°C for 1 hour to push boron atoms into the interior of the silicon carbide wafer. After the diffusion is completed, place the sample in a tube annealing furnace, heat the annealing furnace to 900°C, and then introduce 2 L / min of N2 for 20 minutes to activate boron atoms and repair lattice damage, obtaining the P-type silicon carbide substrate 1;

[0143] A4) Fix the P-type silicon carbide substrate on the sample stage of the evaporation coater with the back facing up, and then evacuate the evaporation chamber to a vacuum degree of 3×10 -6 Torr, and heat to 150°C to remove the adsorbed water vapor and impurities on the surface;

[0144] A5) Place high-purity Al metal in the tungsten wire evaporation source of the evaporation coater, heat the evaporation source to 1300 °C, and keep it for 16 minutes to evaporate the metal and deposit it on the back of the substrate, forming the substrate electrode 17.

[0145] Step B, epitaxially grow an N-type epitaxial layer on the front of the P-type substrate to form an N-type drift region, as Figure 2 (b).

[0146] B1) Place the P-type silicon carbide substrate with the substrate electrode deposited in a horizontal epitaxial furnace, face its front upward, then introduce H2 at 70 L / min, and heat the epitaxial furnace to 1200 °C to form a reducing atmosphere to prevent oxidation of the substrate surface;

[0147] B2) Simultaneously introduce a mixed gas composed of silicon source gas of H2 and SiH4 and carbon source gas of CH4 into the reaction chamber. At high temperature, carbon atoms and silicon atoms released by the thermal decomposition of the mixed gas are deposited on the substrate surface and epitaxially grow along the lattice structure of the substrate to form a single-crystal silicon carbide layer;

[0148] B3) Simultaneously introduce N-type PH3 doping gas into the silicon source and carbon source gases. After the doping gas decomposes, phosphorus P atoms are released and enter the epitaxial layer to form the N-type drift region 2.

[0149] Step C, epitaxially grow a P-type epitaxial layer above the N-type drift region to form a P-type drift region 3, as Figure 2 (c).

[0150] C1) Place the sample with the N-type drift region epitaxially grown in a horizontal epitaxial furnace, heat the epitaxial furnace to 1100 °C and introduce H2 at 70 L / min to form a reducing atmosphere to prevent oxidation of the substrate surface; then simultaneously introduce a mixed gas composed of silicon source gas of H2 and SiH4 and carbon source gas of CH4 into the reaction chamber. At high temperature, carbon atoms and silicon atoms released by the thermal decomposition of the mixed gas are deposited on the substrate surface and epitaxially grow along the lattice structure of the substrate to form a single-crystal silicon carbide layer;

[0151] C2) Simultaneously introduce P-type trimethylgallium doping gas and ammonia gas into the silicon source and carbon source gases. After the gases decompose, gallium Ga atoms and nitrogen atoms are released and enter the epitaxial layer to form the P-type drift region 3.

[0152] Step D, sequentially perform ion implantation in the P-type drift region to form a P-type base region, a P+ source region, and an N-type buffer region, as Figure 2 (d).

[0153] D1) Place the sample with the P-type drift region epitaxially grown in an ion implanter, with a beam current of 1 mA, an implantation energy of 70 keV, and a dose of 1.92×10 13ions / cm -2 A high-energy gallium ion beam of -2 bombards the surface of one side of the P-type drift region at a place 16 μm deep for 0.49 ns to form a P-type base region 6 with a concentration of 2×10 2 ions / cm 16 cm -3 ;

[0154] D2) A high-energy gallium ion beam with a beam current of 1 mA, an implantation energy of 20 keV, and a dose of 9.53×10 15 ions / cm -2 bombards the surface of the P-type base region at a place 1 μm deep for 15.25 ns to form a P+ source region 4 with a concentration of 1×10 2 ions / cm 20 cm -3 ;

[0155] D3) A high-energy antimony ion beam with a beam current of 1 mA, an implantation energy of 70 keV, and a dose of 1×10 14 ions / cm -2 bombards the surface of the other side of the P-type drift region at a place 25 μm deep for 3.57 ns to form an N-type buffer region 7 with a concentration of 1×10 2 ions / cm 17 cm -3 ;

[0156] Step E: Ion implantation is performed on the surface of the P-type base region to form an N+ source region, and ion implantation is performed on the surface of the N-type buffer region to form a P+ drain region, as shown in Figure 2 (e).

[0157] E1) A high-energy antimony ion beam with a beam current of 1 mA, an implantation energy of 20 keV, and a dose of 9.53×10 15 ions / cm -2 bombards the surface of the right side of the P+ source region at a place 1 μm deep for 15.25 ns to form an N+ source region 5 with a concentration of 1×10 2 ions / cm 20 cm -3 ;

[0158] E2) A high-energy gallium ion beam with a beam current of 1 mA, an implantation energy of 20 keV, and a dose of 1.09×10 15 ions / cm -2 bombards the surface of the N-type buffer region at a place 1 μm deep for 1.74 ns to form a P+ drain region 8 with a concentration of 4×10 2 ions / cm 18 cm -3 ;

[0159] Step F: A 0.05-μm-thick silicon dioxide accumulation dielectric layer is grown on the lower surface of the polysilicon, and then it is bonded to the surface of the sample, as shown inFigure 2 (f).

[0160] F1) Select high-purity polysilicon with a thickness of 1 μm, use RCA chemical reagents to remove surface organic substances and particles, and then use deionized water to thoroughly clean and remove residual chemical substances;

[0161] F2) Place the cleaned polysilicon in a CVD reaction chamber, introduce the silicon source gas TEOS and the oxidant N2O, and perform deposition at a deposition rate of 10 nm / min for 5 minutes at a temperature of 600 °C to form an accumulation dielectric layer with a thickness of 0.05 μm and a material of silicon dioxide on the polysilicon;

[0162] F3) Place the polysilicon deposited with the accumulation dielectric layer in an annealing furnace and anneal at 900 °C for 40 minutes to improve the film densification and electrical properties. After annealing, clean the surface of the polysilicon with the accumulation dielectric layer using RCA chemical reagents to remove pollutants and particles;

[0163] F4) Place the sample after forming the P+ drain region and the polysilicon with the accumulation dielectric layer in a direct bonding machine, contact the surface of the accumulation dielectric layer with the surface of the sample at room temperature, and achieve preliminary bonding through the intermolecular force; finally, anneal at 400 °C to form a strong Si-O-Si bonding interface between the accumulation dielectric layer and the surface of the sample.

[0164] Step G, perform ion implantation on the upper surface of the polysilicon in sequence to form a first P-type region, a first N-type region, a second N-type region, and a second P-type region, as shown in Figure 2 (g).

[0165] G1) Place the bonded sample in an ion implanter, and use a high-energy gallium ion beam with a beam current of 1 mA, an implantation energy of 10 KeV, and a dose of 2.7×10 15 ions / cm -2 to bombard the surface of the polysilicon on one side at a place 1 μm 2 for 1.74 ns to form a first P-type region 10 with a concentration of 1×10 19 cm -3 ;

[0166] G2) Use a high-energy gallium ion beam with a beam current of 1 mA, an implantation energy of 10 KeV, and a dose of 2.7×10 15 ions / cm -2 to bombard the surface of the other side of the polysilicon at a place 1 μm 2 for 1.74 ns to form a second P-type region 13 with a concentration of 1×10 19 cm -3 ;

[0167] G3) Bombard the other side surface of the first P-type region at a place 1600 μm away with a high-energy antimony ion beam with a beam current of 1 mA, an implantation energy of 50 keV, and a dose of 1.5×10 12 ions / cm -2 for 3.84 ms to form a first N-type region 11 with a concentration of 5×10 2 cm 14 ; -3

[0168] G4) Bombard the other side surface of the second P-type region at a place 1 μm away with a high-energy antimony ion beam with a beam current of 1 mA, an implantation energy of 10 keV, and a dose of 2.7×10 15 ions / cm -2 for 1.74 ns to form a second N-type region 12 with a concentration of 1×10 2 cm 19 ; -3

[0169] Step H, fabricate electrodes, as shown in Figure 2 (h).

[0170] H1) Place the ion-implanted sample in a thermal oxidation furnace to form a lead hole oxide film. After chemical reagent cleaning, then through spin coating, exposure, development, and etching to form a metal deposition area;

[0171] H2) Fix the sample after dividing the metal deposition area on the sample stage of the evaporation coater with the back facing up, and then evacuate the evaporation chamber to a vacuum degree of 2×10 -6 Torr, and heat to 150 °C to remove the water vapor and impurities adsorbed on the surface; Place high-purity Al metal in the tungsten wire evaporation source of the evaporation coater, heat the evaporation source to 1300 °C, and keep it for 16 minutes to evaporate the metal and deposit it on the surface of the area between the P+ source region and the N+ source region to form a source electrode 14, and at the same time deposit on the upper surface of the part of the first P-type region 10 corresponding to the P-type base region 6;

[0172] H3) Continue to fix the sample on the sample stage of the evaporation coater with the back facing up, and then evacuate the evaporation chamber to a vacuum degree of 3×10 -6 Torr, and heat to 150 °C to remove the water vapor and impurities adsorbed on the surface; Place high-purity Pt metal in the tungsten wire evaporation source of the evaporation coater, heat the evaporation source to 1800 °C, and keep it for 10 minutes to evaporate the metal and deposit it on the surfaces of the P+ drain region and the second P-type region to form a Schottky drain electrode 16.

[0173] Step I, deposit a passivation layer and perform chemical mechanical polishing to complete the device fabrication.

[0174] ​​I1) Place the sample after depositing the electrode into the PECVD reaction chamber, simultaneously introduce the reaction gases SiH4, NH3, and N2O, and apply a radio frequency power of 2000 W. The decomposed Si atoms and N atoms are used to deposit a passivation layer of Si3N4 on the surface of the sample.

[0175] I2) Chemically mechanically polish the sample with the deposited passivation layer:

[0176] First, fix the sample on the polishing head of the polishing machine to ensure that its surface is parallel to the polishing pad. A polishing liquid made by uniformly mixing abrasive particles SiO2, chemical reagent H2O2, pH regulator, dispersant, etc. is evenly sprayed on the polishing pad, so that after the polishing pad contacts the surface of the sample, H2O2 in the polishing liquid softens the surface through chemical action.

[0177] Then, apply pressure to the polishing pad to make it rotate, so that SiO2 in the polishing liquid ensures the surface of the sample becomes flat through mechanical action.

[0178] Finally, clean the polished sample with deionized water and a cleaning agent to remove the residual polishing liquid and complete the device fabrication.

[0179] The effects of the present invention can be further illustrated by the following simulation experiment results:

[0180] I. Simulation conditions

[0181] The software used for the simulation is Sentaurus TCAD.

[0182] Set the breakdown voltage rating of the device to 600 V.

[0183] II. Simulation content

[0184] Simulation 1, under the above simulation conditions, simulate the current density of the hole leakage current in the substrate of the device of Embodiment 1 of the present invention and the traditional LIGBT device in the forward conduction state. The results are as Figure 3 shown. From Figure 3 it can be seen that the current density of the hole substrate leakage current of the traditional LIGBT is 146.3 A / cm 2 , while the current density of the hole substrate leakage current of the present invention is 0.006 A / cm 2 . The difference in the current density of the hole substrate leakage current between the two is within five orders of magnitude, indicating that the N-type drift region of the device of the present invention can well block the flow of holes from the drain to the substrate, thereby alleviating the problem of large substrate leakage current of the device.

[0185] Simulation 2, under the above simulation conditions, simulate the breakdown voltage characteristics of the device of Embodiment 1 of the present invention and the traditional LIGBT device respectively. The results are as Figure 4 shown. From Figure 4It can be seen that the breakdown voltage of the traditional LIGBT is 586.1V, while the breakdown voltage of the present invention is 729.9V. The voltage withstand capacity of the present invention is increased by 24.5% compared with the traditional LIGBT device.

[0186] Simulation 3: Under the above simulation conditions, the turn-off characteristics of the device of Embodiment 1 of the present invention and the traditional LIGBT device are respectively simulated, and the results are as Figure 5 shown. From Figure 5 it can be seen that the turn-off time of the traditional LIGBT is 231.4 nanoseconds, while the turn-off time of the present invention is 91.7 nanoseconds. The turn-off characteristics of the device of the present invention are improved by 60.4% compared with the traditional LIGBT device.

[0187] The above are only several preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, after understanding the content and principle of the present invention, various modifications or substitutions in form and details may be made without departing from the principle and structure of the present invention. For example, in addition to silicon, the device manufacturing material may also be materials such as germanium, gallium arsenide, silicon carbide, or heteroepitaxial materials. However, these corrections and changes based on the idea of the present invention are still within the protection scope of the present invention.

Claims

1. A low substrate leakage current LIGBT device with a PN junction accumulation layer, comprising: P-type substrate (1), N-type drift region (2), P+ source region (4), N+ source region (5), P-type base region (6), N-type buffer region (7), P+ drain region (8), source electrode (14), gate electrode (15), drain electrode (16) and substrate electrode (17), characterized in that: Above the N-type drift region (2), a P-type drift region (3) and an accumulation dielectric layer (9) are successively provided to form a drift region structure with alternating P-type and N-type longitudinally, and both sides of the P-type drift region (3) are respectively in contact with the P-type base region (6) and the N-type buffer region (7) to relieve substrate hole leakage. Above the accumulation dielectric layer (9), four regions of a first P-type region (10), a first N-type region (11), a second N-type region (12) and a second P-type region (13) are successively arranged in parallel to form a PN junction accumulation layer, and the first N-type region (11) is adjacent to the second N-type region (12), the first P-type region (10) is adjacent to the first N-type region (11), and the second P-type region (13) is adjacent to the second N-type region (12) to form a PN junction and a reverse PN junction at both ends of the accumulation layer, avoiding premature breakdown when the device is in forward conduction and forward blocking, and improving the breakdown voltage capability of the device.

2. The LIGBT structure according to claim 1, characterized in that: The P-type substrate (1) is made of any one of silicon, germanium, gallium arsenide, and silicon carbide, and its doping concentration is 1×10 14 cm -3 ~5×10 14 cm -3 ; The N-type drift region (2) is located above the P-type substrate (1), and its doping concentration is 8×10 14 cm -3 ~1×10 15 cm -3 ; The P-type drift region (3) is located above the N-type drift region (2), and its doping concentration is 4×10 14 cm -3 ~5×10 14 cm -3 ; The substrate electrode (17) is located on the back surface of the P-type substrate (1).

3. The LIGBT structure according to claim 1, characterized in that: The accumulation dielectric layer (9) is made of silicon dioxide or high-K material and has a thickness of 0.04 - 0.1 microns. The thicknesses of the first P-type region (10), the first N-type region (11), the second N-type region (12) and the second P-type region (13) are 0.5 to 3 microns, and the doping concentrations of the first P-type region (10) and the second P-type region (13) are both 1×10 18 cm -3 ~1×10 20 cm -3 ; The doping concentration of the first N-type region (11) is 1×10 13 cm -3 ~7×10 15 cm -3 ; The doping concentration of the second N-type region (12) is 1×10 15 cm -3 ~5×10 16 cm -3 。 4. The LIGBT structure according to claim 1, characterized in that: The P+ source region (4) is adjacent to the P-type base region (6), and the doping concentration of the P+ source region (4) is 1×10 19 cm -3 ~1×10 20 cm -3 , and the doping concentration of the P-type base region (6) is 1×10 16 cm -3 ~1×10 17 cm -3 ; The gate electrode (15) is located on the upper surface of the part of the first P-type region (10) corresponding exactly to the P-type base region (6). The N+ source region (5) is located in the upper partial region of the P+ source region (4), and its doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 ; The source electrode (14) covers the surfaces of the P+ source region (4) and the N+ source region (5). The N-type buffer (7) is located on one side of the P-type drift region (3), and its lower boundary does not exceed the lower boundary of the P-type drift region (3), and its doping concentration is 6×10 16 cm -3 ~2×10 17 cm -3 ; The P+ drain region (8) is located in the upper partial region of the N-type buffer region (7), and its doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 ; The drain electrode (16) is located on the upper surface of the part of the P+ drain region (8) and the second P-type region (13), in Schottky contact with the material surface, and the contact barrier is 5.03 eV.

5. A method for manufacturing the device according to claim 1, characterized in that, Including the following steps: 1) Deposit metal on the back surface of the selected P-type substrate (1) to form the substrate electrode (17). 2) Place the P-type substrate (1) deposited with the substrate electrode in the reaction chamber, and epitaxially grow an N-type epitaxial layer on the front surface of the P-type substrate (1) by homoepitaxy technology to form the N-type drift region (2). 3) Epitaxially grow a P-type epitaxial layer on the front surface of the N-type drift region (2) by homoepitaxy technology to form the P-type drift region 3. 4) Successively perform ion implantation in the P-type drift region (3) to form the P-type base region (6), the P+ source region (4) and the N-type buffer region (7), and repair the lattice damage by rapid thermal annealing. 5) Perform ion implantation on the surface of the P-type base region (6) to form the N+ source region (5), and perform ion implantation on the surface of the N-type buffer layer (7) to form the P+ drain region (8), and repair the lattice damage by rapid thermal annealing. 6) Select a polysilicon material with a thickness of 0.5 - 3 microns, grow an accumulation oxide layer (9) on its bottom surface, and then bond it to the surface of the sample through a bonding process. 7) Ion implantation is performed on the upper surface of the polysilicon to form a first P-type region (10), a first N-type region (11), a second N-type region (12), and a second P-type region (13), and the lattice damage is repaired by rapid thermal annealing to form a PN junction accumulation layer; 8) Metal is deposited in the regions of the P+ source region (4) and the N+ source region (5) to form a source electrode (14); metal is deposited on the surface of the first P-type region (10) to form a gate electrode (15), and metal is deposited on the surfaces of the P+ drain region (8) and the second P-type region (13) to form a drain electrode (16); 9) A passivation layer is deposited on the surface of the sample after the above steps and chemical mechanical polishing is performed to make the surface flat, completing the device fabrication.

6. The method according to claim 5, wherein: For the homoepitaxy technology in step 2), the process conditions are as follows: The carrier gas introduced into the reaction chamber is H2; The reaction gases are silicon source gases of SiCl4, SiHCl3, SiH4 and PH3 gas; The set ambient temperature is 1150°C to 1200°C.

7. The method according to claim 5, characterized in that: For the homoepitaxy technology in step 3), the process conditions are as follows: The carrier gas introduced into the reaction chamber is H2; The reaction gases are silicon source gases of SiCl4, SiHCl3, SiH4 and BH3 gas; The set ambient temperature is 1150°C to 1200°C.

8. The method according to claim 5, wherein: For the ion implantation in step 4), the material and concentration parameters are as follows: The P-type ion material implanted into the P-type base region (6) is any one of boron, aluminum, and gallium, and its concentration is 1×10 16 cm -3 ~1×10 17 cm -3 ; The P-type ion material implanted in the P+ source region (4) is any one of boron, aluminum, and gallium, and its concentration is 1×10 19 cm -3 ~1×10 20 cm -3 ; The N-type ion material implanted into the N-type buffer layer (7) is any one of phosphorus, arsenic, and antimony, and its concentration is 6×10 16 cm -3 ~2×10 17 cm -3 .

9. The method according to claim 5, characterized in that: For the ion implantation in step 5), the material and concentration parameters are as follows: The N-type ion material implanted in the N+ source region (5) is any one of phosphorus, arsenic, and antimony, and its concentration is 1×10 19 cm -3 ~1×10 20 cm -3 ; The P-type ionic material implanted in the P+ drain region (8) is any one of boron, aluminum, and gallium, and its concentration is 1×10 19 cm -3 ~1×10 20 cm -3 .

10. The method according to claim 5, wherein: For the ion implantation in step 7), the material and concentration parameters are as follows: The N-type ion material implanted in the first N-type region (11) is any one of phosphorus, arsenic, and antimony, and its concentration is 1×10 13 cm -3 ~7×10 15 cm -3 ; The N-type ion material implanted into the second N-type region (12) is any one of phosphorus, arsenic, and antimony, and its concentration is 1×10 15 cm -3 ~5×10 16 cm -3 ; The P-type ion materials implanted in the first P-type region (10) and the second P-type region (13) are any one of boron, aluminum, and gallium, and their concentrations are all 1×10 18 cm -3 ~1×10 20 cm -3 .

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