Power MOSFET device and manufacturing method thereof

Abstract

The invention provides a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a manufacturing method thereof. The device comprises a drain metal layer; the epitaxial structure is arranged on the drain electrode metal layer; the at least two grid electrode grooves are formed in one side, deviating from the drain electrode metal layer, of the epitaxial structure; gate polycrystalline silicon is arranged in the gate trench; the at least one source electrode groove is arranged between two adjacent grid electrode grooves, and source electrode polycrystalline silicon is arranged in the source electrode groove; and the source electrode metal layer is electrically connected with the source electrode polycrystalline silicon. According to the invention, under the condition that the channel density is not reduced, the source-drain capacitance can be increased, and the EMI characteristic of the device can be optimized by adjusting the resistance of the source polysilicon in the source trench.

Description

Technical Field

[0001] The present invention relates to the application field of semiconductor devices, and in particular to a power MOSFET device and a manufacturing method thereof. Background Art

[0002] Insulated gate field effect transistor (MOSFET) is widely used in various power systems due to its advantages such as fast switching speed, low power consumption, easy gate drive, low drive power, high input impedance and good frequency response. At present, super junction MOSFET devices are often used in the medium and high voltage range.

[0003] In topologies such as PFC and LLC, super junction MOSFET devices are often used as switches to operate in a fast switching state. Their internal current and voltage will change dramatically in a short period of time, causing large electromagnetic interference to other components of the circuit. Therefore, it is crucial to optimize the EMI electromagnetic interference characteristics of MOSFET devices. Summary of the invention

[0004] In view of the above problems existing in the prior art, the present invention proposes a power MOSFET device and a manufacturing method thereof, which mainly solves the problem that the existing MOSFET device will generate large electromagnetic interference when switching, thereby affecting circuit performance.

[0005] In order to achieve the above purpose and other purposes, the technical solution adopted by the present invention is as follows.

[0006] The present application provides a power MOSFET device, comprising: a drain metal layer; an epitaxial structure, which is arranged on the drain metal layer; at least two gate trenches, which are arranged on a side of the epitaxial structure away from the drain metal layer; gate polysilicon is arranged in the gate trench; at least one source trench, which is arranged between two adjacent gate trenches, and source polysilicon is arranged in the source trench; and a source metal layer, which is electrically connected to the source polysilicon.

[0007] In one embodiment of the present application, the epitaxial structure includes a substrate and a drift region arranged on one side of the substrate, the drift region includes a plurality of pillars perpendicular to the substrate and arranged side by side, and two adjacent pillars have different doping types, and each of the pillars is provided with a gate trench or a source trench.

[0008] In an embodiment of the present application, a body region, a source region, and a contact region are provided between the gate trench and the source trench. The source region and the contact region are arranged side by side on a side of the body region facing away from the drift region, and one side of the source region is in contact with the side wall of the gate trench, and one side of the contact region is in contact with the side wall of the source trench. Wherein, the depths of the source trench and the gate trench are greater than the depth of the bottom of the body region in the epitaxial structure.

[0009] In an embodiment of the present application, the resistance of the source polysilicon is greater than the resistance of the gate polysilicon.

[0010] In an embodiment of the present application, the gate polysilicon is electrically isolated from the body region, the source region, and the source metal layer through a gate oxide layer; the source polysilicon is electrically isolated from the body region and the source region through a source oxide layer.

[0011] In an embodiment of the present application, the materials of the device include silicon, silicon carbide, gallium nitride, gallium arsenide, indium phosphide, gallium oxide, or silicon germanium.

[0012] In an embodiment of the present application, the doping type of the substrate is the second type, the doping type of the body region is the first type, the doping type of the source region is the second type, and the doping type of the contact region is the first type.

[0013] In an embodiment of the present application, the first type is P-type, and the second type is N-type; the drift region and the body region are moderately doped, and the doping concentration magnitude ∈ (1e16 cm-3, 1e18 cm-3], and the substrate, the source region, and the contact region are heavily doped, and the doping concentration magnitude > 1e18 cm-3.

[0014] The present application also provides a method for manufacturing a power MOSFET device, including: fabricating an epitaxial structure; fabricating at least two gate trenches on one side of the epitaxial structure, and depositing gate polysilicon in the gate trenches; fabricating at least one source trench, the source trench being disposed between two adjacent gate trenches, and depositing source polysilicon in the source trench; fabricating a source metal layer, which is electrically connected to the source polysilicon; and fabricating a drain metal layer on a side of the epitaxial structure facing away from the gate trenches.

[0015] As described above, a power MOSFET device and a manufacturing method thereof proposed by the present application have the following beneficial effects.

[0016] The present application introduces a source trench between adjacent gate trenches. Without reducing the channel density, the source-drain capacitance can be increased, and by adjusting the resistance of the source polysilicon in the source trench, the EMI characteristics of the device can be optimized. Description of the Drawings

[0017] Figure 1 This is a schematic structural diagram of a power MOSFET device in an embodiment of the present application.

[0018] Figure 2 This is a schematic diagram of the RC network of the power MOSFET device in an embodiment of the present application.

[0019] Figure 3 This is a schematic structural diagram of a power MOSFET device in another embodiment of the present application.

[0020] Figure 4 is Figure 3 a schematic diagram of the RC network of the corresponding device. Figure 5 This is a schematic flowchart of the manufacturing method of the power MOSFET device in an embodiment of the present application.

[0021] Explanation of the reference numerals in the drawings: 1 - Drain metal layer; 2 - Substrate; 301 - Second - type drift region; 302 - First - type drift region; 4 - Trench oxide layer; 51 - Gate polysilicon; 52 - Source polysilicon; 6 - Body region; 7 - Source region; 8 - Contact region; 9 - Top insulating dielectric layer; 10 - Source metal layer. Detailed implementation manners

[0022] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0023] It should be noted that the drawings provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0024] Please refer to Figure 1 , Figure 1The schematic diagram of the structure of a power MOSFET device in an embodiment of the present application. The MOSFET device in the embodiment of the present application includes: a drain metal layer 1; an epitaxial structure, which is arranged on the drain metal layer 1; at least two gate trenches, which are arranged on the side of the epitaxial structure away from the drain metal layer 1; gate polysilicon 51 is arranged in the gate trench; at least one source trench, which is arranged between two adjacent gate trenches, and source polysilicon 52 is arranged in the source trench; and a source metal layer 10, which is electrically connected to the source polysilicon 52.

[0025] In one embodiment, the epitaxial structure includes a substrate 2 and a drift region disposed on one side of the substrate 2, wherein the drift region includes a plurality of pillars perpendicular to the substrate 2 and disposed side by side, and two adjacent pillars have different doping types, and each pillar is provided with a gate trench or a source trench. Taking a structure with three pillars as an example, the pillars on both sides can be set to N-type doping (i.e., the second type drift region 301), the middle pillar is set to P-type doping (i.e., the first type drift 302), the two N-type pillars are provided with gate trenches, the P-type pillar is provided with a source trench, and the same applies to other situations.

[0026] In one embodiment, a body region 6, a source region 7 and a contact region 8 are arranged between the gate trench and the source trench, and the source region 7 and the contact region 8 are arranged side by side on the side of the body region 6 away from the drift region, and one side of the source region 7 contacts the side wall of the gate trench, and one side of the contact region 8 contacts the side wall of the source trench, wherein the depth of the source trench and the gate trench is greater than the depth of the bottom of the body region 6 in the epitaxial structure. The contact region 8 is an ohmic contact. One side of the source region 7 is connected to the side wall of the gate trench, and the other side is connected to one side of the contact region 8, and the other side of the contact region 8 is connected to the side wall of the source trench. The source polysilicon 52 can be electrically connected to the source metal layer 10 through the contact region 8 openings on both sides (i.e., the contact window range in the figure).

[0027] In one embodiment, the gate polysilicon 51 is electrically isolated from the body region 6, the source region 7 and the source metal layer 10 by the gate oxide layer; the source polysilicon 52 is electrically isolated from the body region 6 and the source region 7 by the source oxide layer. The source oxide layer and the gate oxide layer can both be made of silicon dioxide (i.e., the trench oxide layer 4 in the figure). The gate oxide layer at the top of the gate trench (i.e., the top insulating dielectric layer 9) can cover the side of the source region 7 away from the body region 6.

[0028] In one embodiment, the doping type of the substrate 2 is the second type, the doping type of the body region 6 is the first type, the doping type of the source region 7 is the second type, and the doping type of the contact region 8 is the first type; the first type is P-type and the second type is N-type; the drift region and the body region 6 are moderately doped with a doping concentration magnitude ∈ (1e16 cm-3, 1e18 cm-3], and the substrate 2, the source region 7, and the contact region 8 are heavily doped with a doping concentration magnitude > 1e18 cm-3.

[0029] In one embodiment, the materials of the device include silicon, silicon carbide, gallium nitride, gallium arsenide, indium phosphide, gallium oxide, or silicon germanium.

[0030] Please refer to Figure 2 , Figure 2 which is a schematic diagram of the RC network of the power MOSFET device in an embodiment of the present application. In one embodiment, by adjusting the doping concentration of the source polysilicon 52, the resistance of the source polysilicon 52 can be made greater than the resistance of the gate polysilicon 51. Through the additional source trench, the parallel capacitance branch between the source and the drain can be increased, thereby increasing the source-drain capacitance of the device. By adjusting the doping concentration of the source polysilicon, the resistance value in the source-drain resistive-capacitive network can be increased, and finally the RC absorption network time constant of the device can be increased, thereby optimizing the EMI characteristics of the device.

[0031] Please refer to Figure 3 , Figure 3 which is a schematic structural diagram of the power MOSFET device in another embodiment of the present application. Figure 3 The difference from Figure 1 is only that: multiple spaced and independent source trenches are provided between adjacent gate trenches.

[0032] Please refer to Figure 4 , Figure 4 which is Figure 3 the schematic diagram of the RC network of the corresponding device. By forming multiple source trenches to form multiple RC parallel branches, the source-drain capacitance of the device can be further increased, and the EMI characteristics of the device can be optimized.

[0033] Based on the technical solutions of the embodiments of the present application above, without reducing the channel density, an additional source trench structure can be introduced between the gate trenches of the conventional trench MOSFET cell and below the lithography range of the Contact contact hole, so as to increase the C DS capacitance; the resistance R S of the polycrystalline material in the source trench can be adjusted by doping, and by adjusting the size of C DS *R S in the absorption network, the EMI characteristics of the device can be optimized.

[0034] Please refer to Figure 5 , Figure 5The following is a flow chart of a method for manufacturing a power MOSFET device in an embodiment of the present application. The method comprises the following steps: Step S500, fabricating an epitaxial structure; Step S510, forming at least two gate trenches on one side of the epitaxial structure, and depositing gate polysilicon in the gate trenches; Step S520, manufacturing at least one source trench, the source trench being disposed between two adjacent gate trenches, and depositing source polysilicon in the source trench; Step S530, manufacturing a source metal layer, which is electrically connected to the source polysilicon; Step S540 , forming a drain metal layer on a side of the epitaxial structure away from the gate trench.

[0035] In one embodiment, the source trench structure and the gate trench structure may be defined on the same mask and fabricated simultaneously, or may be defined and fabricated using separate masks, and their widths are independent of each other.

[0036] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A power MOSFET device, characterized in that, Comprising: A drain metal layer; An epitaxial structure disposed on the drain metal layer; At least two gate trenches disposed on a side of the epitaxial structure facing away from the drain metal layer; gate polysilicon is disposed in the gate trenches; At least one source trench disposed between two adjacent gate trenches, and source polysilicon is disposed in the source trench; A source metal layer electrically connected to the source polysilicon.

2. The power MOSFET device according to claim 1, characterized in that, The epitaxial structure includes a substrate and a drift region disposed on one side of the substrate. The drift region includes a plurality of pillars arranged side by side in a direction perpendicular to the substrate, and two adjacent pillars have different doping types. Each pillar is provided with one of the gate trenches or the source trench.

3. The power MOSFET device according to claim 2, wherein A body region, a source region, and a contact region are disposed between the gate trench and the source trench. The source region and the contact region are arranged side by side on a side of the body region facing away from the drift region, and one side of the source region is in contact with a sidewall of the gate trench, and one side of the contact region is in contact with a sidewall of the source trench. Wherein, the depths of the source trench and the gate trench are greater than the depth of the bottom of the body region in the epitaxial structure.

4. The power MOSFET device according to claim 1, characterized in that, The resistance of the source polysilicon is greater than the resistance of the gate polysilicon.

5. The power MOSFET device according to claim 3, wherein The gate polysilicon is electrically isolated from the body region, the source region, and the source metal layer through a gate oxide layer; the source polysilicon is electrically isolated from the body region and the source region through a source oxide layer.

6. The power MOSFET device according to claim 1, characterized in that, The materials of the device include silicon, silicon carbide, gallium nitride, gallium arsenide, indium phosphide, gallium oxide, or silicon germanium.

7. The power MOSFET device according to claim 3, wherein The doping type of the substrate is the second type, the doping type of the body region is the first type, the doping type of the source region is the second type, and the doping type of the contact region is the first type.

8. The power MOSFET device according to claim 7, wherein The first type is P-type, and the second type is N-type; the drift region and the body region are moderately doped, and the doping concentration magnitude ∈ (1e16 cm-3, 1e18 cm-3], and the substrate, the source region, and the contact region are heavily doped, and the doping concentration magnitude > 1e18 cm-3.

9. A method for manufacturing a power MOSFET device, characterized in that, Comprising: Fabricating an epitaxial structure; Fabricating at least two gate trenches on one side of the epitaxial structure, and depositing gate polysilicon in the gate trenches; Fabricating at least one source trench, the source trench being disposed between two adjacent gate trenches, and depositing source polysilicon in the source trench; Fabricating a source metal layer electrically connected to the source polysilicon; Fabricating a drain metal layer on a side of the epitaxial structure facing away from the gate trenches.

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