Selective improvements in selective metals with RF pulses

Abstract

Embodiments of the present invention relate to methods of removing metal oxides from a substrate surface by exposing the substrate surface to a hydrogen (H2) plasma and an RF pulse. In some embodiments, an upper surface of a substrate surface has at least one feature defining a trench having a top surface, a bottom surface, and two opposing sidewalls. A hydrogen (H2) plasma and RF pulses remove substantially all of the metal oxides, such as tungsten oxide (WOx), molybdenum oxide (MoOx), or ruthenium oxide (RuOx), from the substrate surface without compromising the dielectric and / or critical dimension (CD) and / or profile of the structure. A metal fill may then be selectively deposited in the trench.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to improved methods for forming interconnects. In particular, embodiments of the present invention relate to adding RF pulses in plasma pre-cleaning for selective metal deposition. Background Art

[0002] Gap fill processes are integrated into several semiconductor manufacturing processes. Gap fill processes can be used to fill gaps (or features) with insulating or conductive materials. For example, shallow trench isolation, inter-metal dielectric layers, passivation layers, dummy gates are typically implemented by gap fill processes.

[0003] As device geometries continue to shrink (e.g., critical dimensions <20 nm, <10 nm, and further) and the thermal budget is reduced, due to the limitations of traditional deposition processes, defect-free filling of the space becomes increasingly difficult.

[0004] Typically incoming substrates have residues thereon from previous processes, from native oxide formation on metals, and from etch residues from via / trench hole formation. Native oxides such as tungsten oxide (WOx) are formed as a result of etching vias / trenches and vacuum breakage. To improve the process performance of metal filling, e.g., low line resistance, high yield, and high reliability, any residues and / or native oxides must be removed. Therefore, a pre-cleaning process is needed to clean native oxides (such as tungsten oxide (WOx)) to minimize the resistance capacitance ("resistance" or "resistivity") in integrated circuits.

[0005] Current pre-cleaning processes involve exposing the substrate to a plasma of argon (Ar) and hydrogen (H2) to remove native oxides. These pre-cleaning processes are performed in the presence of an external bias at the substrate surface, which can damage the dielectric and critical dimension (CD) / profile of the structure and result in lower selectivity during subsequent metal deposition. In particular, the high-energy components in the H2 plasma cause damage to the dielectric, leaving defects. These defects become nucleation sites for W growth, causing growth on non-preferred dielectric surfaces and resulting in a loss of selectivity.

[0006] Therefore, there is a need in the art for improved processes for cleaning materials and structures on semiconductor substrates without damaging the dielectric and reducing selectivity. Summary of the Invention

[0007] One or more embodiments relate to a method of forming a semiconductor device. The method includes: exposing a substrate surface to a hydrogen (H2) plasma and an RF pulse to pre-clean the substrate surface, forming a clean surface; and depositing a metal fill on the clean surface.

[0008] Additional embodiments relate to a method of processing for forming semiconductor devices. In one or more embodiments, the method of processing includes: pre-cleaning a substrate by exposing the substrate to a hydrogen (H2) plasma and an RF pulse to form a clean substrate having at least one feature formed therein, the at least one feature including sidewalls of a first dielectric layer and a second dielectric layer, and a bottom surface including a metal layer having a metal oxide layer formed on a top surface of the metal layer; and depositing a metal fill on the clean substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A more specific description of the invention, briefly summarized above, may be obtained by reference to the embodiments, some of which are shown in the accompanying drawings, such that the above features of the invention may be understood in detail. However, it will be noted that the accompanying drawings only show typical embodiments of the invention and are therefore not to be regarded as limiting its scope, as the invention may admit of other equivalent embodiments. The embodiments described herein are illustrative by way of example and not limitation in the illustrations of the accompanying drawings, in which like reference numerals indicate like elements.

[0010] Figure 1 A process flow diagram showing a method according to one or more embodiments of the invention;

[0011] Figure 2 A cross-sectional view of a feature on a substrate showing a method according to one or more embodiments of the invention;

[0012] Figure 3 A cross-sectional view of a feature on a substrate showing a method according to one or more embodiments of the invention; and

[0013] Figure 4 A cross-sectional view of a feature on a substrate showing a method according to one or more embodiments of the invention. DETAILED DESCRIPTION

[0014] Before describing several exemplary embodiments of the invention, it is to be understood that the invention is not limited to the details of construction or processing steps set forth in the following description. The invention is capable of other embodiments and of being practiced or carried out in various ways.

[0015] As used herein, "substrate" refers to any substrate on which film processing is performed during a manufacturing process or to a surface of a material formed on a substrate. For example, substrate surfaces on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, without limitation, semiconductor wafers.

[0016] The substrate may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the surface of the substrate. In addition to film treatments directly on the surface of the substrate itself, in the present invention, any of the disclosed film treatment steps may also be performed on top of a lower layer formed on the substrate, as will be described in more detail later, and the term "substrate surface" is intended to include such a lower layer as indicated by the context. Thus, for example, where a film / layer or portion of a film / layer has been deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0017] As used herein, the term "substrate surface" refers to any substrate surface on which a layer can be formed. The substrate surface may have one or more features formed therein or thereon, one or more layers formed thereon, and combinations of the foregoing. The shape of the feature can be any suitable shape, including but not limited to spikes, trenches, and cylindrical vias. As used in this way, the term "feature" refers to any intentional surface irregularity. Suitable examples of features include but are not limited to trenches, spikes, and vias, where a trench has a top surface, two opposing sidewalls, and a bottom surface, a spike has a top and two sidewalls extending upward from the surface, and a via has sidewalls extending downward from the surface and a bottom. In some embodiments, the bottom of the via includes an open bottom defined or bounded by underlying material, such as a dielectric material, which also defines the two sidewalls, or the underlying material at the bottom can be a conductor, such as a metal (e.g., copper), which can be the same as or different from the sidewall material.

[0018] The term "on" indicates direct contact between elements. The term "directly on" indicates direct contact between elements and no intervening element.

[0019] As used herein, "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate or a portion of the substrate surface is separately exposed to two or more reactive compounds introduced into the reaction zone of a processing chamber. In time-domain ALD processing, the exposure to each reactive compound is separated by a time delay to allow each compound to adhere and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are referred to as being sequentially exposed to the substrate. In spatial ALD processing, different portions of the substrate surface or materials on the substrate surface are simultaneously exposed to these two or more reactive compounds such that at any given point on the substrate, it is not substantially simultaneously exposed to more than one reactive compound. As used in this specification and the appended claims, as will be understood by those of ordinary skill in the art, the term "substantially" means that there is a small portion of the substrate that may be simultaneously exposed to multiple reactive gases due to diffusion, and this simultaneous exposure is not intentional.

[0020] In one aspect of time-domain ALD processing, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone, followed by a first time delay. Next, a second precursor or compound B is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas such as argon is introduced into the processing chamber to purge the reaction zone or remove any residual reactive compounds or reaction by-products from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process such that only the purge gas flows during the time delay between pulses of the reactive compounds. The reactive compounds are pulsed until a desired film or film thickness is formed on the substrate surface. In either scenario, the ALD process of pulsing compound A, the purge gas, compound B, and the purge gas is one cycle. A cycle can start with either compound A or compound B, and continue in the respective order of the cycle until a film of a predetermined thickness is achieved.

[0021] In an embodiment of spatial ALD processing, a first reactive gas and a second reactive gas (e.g., nitrogen) are simultaneously delivered to the reaction zone, but are separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas delivery device such that any given point on the substrate is exposed to the first reactive gas and the second reactive gas.

[0022] In one or more embodiments, a film is deposited conformally on a surface. As used herein, the term "conformal" or "conformally" refers to a film with a thickness that adheres to and uniformly covers an exposed surface, and the variation in this thickness relative to the average thickness of the film is less than 5%, less than 2%, or less than 1%. For example, a thick film may have a thickness variation of less than . This thickness and variation include at least the edges, corners, sides, and bottoms of recesses. For example, conformal films deposited by ALD in various embodiments of the present invention provide coverage of a deposition region of substantially uniform thickness on a complex surface.

[0023] Embodiments of the present invention advantageously provide a method for removing metal oxides from a substrate surface with RF plasma pulses. Advantageously, the present invention provides a process for pre-cleaning materials and structures on a semiconductor substrate without damaging the dielectric and / or critical dimension (CD) / profile of the structure.

[0024] Current pre-cleaning processes involve exposing a substrate to a plasma of argon (Ar) and hydrogen (H2) to remove native oxides. These pre-cleaning processes are performed in the presence of an external bias at the substrate surface, which can damage the dielectric and critical dimension (CD) / profile of the structure and result in lower selectivity during subsequent metal deposition. Specifically, the high-energy components in the H2 plasma cause damage to the dielectric, leaving defects. The defects become nucleation sites for W growth, causing growth on non-preferred dielectric surfaces and resulting in selectivity loss.

[0025] In one or more embodiments, it has been unexpectedly found that adding RF pulses during H2 plasma pre-cleaning removes metal oxides from the substrate surface without damaging the dielectric surface. Advantageously, the RF pulses can alter the plasma ion energy distribution, reducing the high-energy ion density, thus causing less damage to the dielectric surface. In one or more embodiments, the RF pulses increase the ratio of low-energy ions to radicals. The low-energy ions and radicals can remove surface contaminants and reduce metal oxides, e.g., WOx. Additionally, the low-energy ions and radicals effectively reduce dielectric damage during the pre-cleaning process but still maintain effective cleaning.

[0026] Further embodiments of the present invention are illustrated by the accompanying drawings, which show a substrate surface, features formed on the substrate surface, and a process for removing metal oxides from the substrate surface and the surfaces of the features, in accordance with one or more embodiments of the present invention. The processes shown are merely exemplary possible uses for the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the applications shown.

[0027] Figure 1 A process flow diagram of a method 10 is shown in accordance with one or more embodiments. In one or more embodiments, method 10 begins at operation 12 by providing a substrate. As used in this specification and the appended claims, the term "being provided" means making the substrate available for processing (e.g., positioned in a processing chamber). At operation 14, the substrate surface is pre-cleaned using RF pulses in a hydrogen (H2) plasma. At operation 16, a metal is selectively deposited on the clean surface.

[0028] Figures 2-4 are cross-sectional views of an exemplary apparatus during a processing method 10 in accordance with one or more embodiments of the present invention. Referring Figure 2 , at operation 12, a substrate 100 is provided for processing. In some embodiments, the substrate 100 is a wafer, e.g., a semiconductor substrate. In one or more embodiments, the substrate 100 includes a first dielectric layer 102 and a second dielectric layer 104. In one or more embodiments, the substrate 100 has at least one feature 106 formed therein.

[0029] In one or more embodiments, one or more of the first dielectric layer 102 and the second dielectric layer 104 are deposited using any suitable deposition technique, such as, but not limited to, chemical vapor deposition (“CVD”), physical vapor deposition (“PVD”), molecular beam epitaxy (“MBE”), metalorganic chemical vapor deposition (“MOCVD”), atomic layer deposition (“ALD”), spin coating, or other deposition techniques known to those skilled in the art of microelectronic device fabrication.

[0030] As used herein, the term “dielectric” refers to a layer of material that is an electrical insulator that can be polarized in an electric field. In one or more embodiments, one or more of the first dielectric layer 102 and the second dielectric layer 104 independently comprise one or more of oxides, carbon-doped oxides, silicon oxide (SiOx), silicon nitride (SiN), silicon oxide / silicon nitride, carbides, carbon oxides, nitrides, nitrogen oxides, oxynitrides, polymers, phosphosilicate glass, fluorosilicate (SiOF) glass, organosilicate glass (SiOCH), silicon carbonitride (SiCN). In one or more embodiments, one or more of the first dielectric layer 102 and the second dielectric layer 104 include, without limitation, films deposited by furnace, CVD, PVD, ALD, and spin-on coating (SoC). In one or more embodiments, one or more of the first dielectric layer 102 and the second dielectric layer 104 may be exposed to in-situ or ex-situ pre-treatment and post-treatment processes to dope, implant, implant, heat, freeze, polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and / or bake the surface or bulk of the dielectric. In one or more specific embodiments, one or more of the first dielectric layer 102 comprises silicon oxide (SiOx), and the second dielectric layer 104 comprises silicon nitride (SiOx). The silicon nitride (SiN) may be doped or undoped.

[0031] As used in this specification and the appended claims, the term “oxide” or the like means that the material contains the indicated element. This term should not be construed to imply a specific ratio of elements. Thus, “oxide” or the like may contain elements in stoichiometric ratios or non-stoichiometric ratios.

[0032] For illustrative purposes, Figure 2-4 a substrate 100 is shown having a single feature 106. However, those skilled in the art will recognize that there will be more than one feature and that multiple features will each be affected in a similar manner by the disclosed methods.

[0033] As used herein, the term "feature" refers to intentional surface irregularities. The shape of feature 106 can be any suitable shape, including but not limited to trenches, vias that conduct current between layers when filled with metal, and lines that conduct current within the same device layer. In some embodiments, feature 106 defines a gap in dielectric layer (silicon nitride layer) 104. As used herein, the term "feature" refers to any intentional surface irregularity. Suitable examples of features include but are not limited to trenches having a top, two sidewalls, and a bottom, and spikes having a top and two sidewalls. A feature can have any suitable aspect ratio (the ratio of the depth of the feature to the width of the feature). In some embodiments, the aspect ratio is greater than or equal to about 1:1, 2:1, 3:1, 4:1, 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, or 40:1.

[0034] A feature can have any suitable critical dimension (CD). As used herein, the term "critical dimension (CD)" refers to the width of a feature or an opening. In one or more embodiments, the critical dimension width, w1, of feature 106 is in to range, or in to range.

[0035] In one or more embodiments, at least one feature 106 has a width w1. Feature 106 is formed in top surface 103 of substrate 100. Feature 106 also has one or more sidewalls 106s and extends a feature depth D from top surface 106 to bottom 110, which is the top surface of metal 104. Although straight, vertical sidewalls 106s are shown in the figures, the disclosed method can also be implemented on slanted, irregular, or recessed sidewalls.

[0036] In some embodiments, the opening width W of opening 212 is less than or equal to about 50 nm, less than or equal to about 30 nm, less than or equal to about 20 nm, less than or equal to about 10 nm, or less than or equal to about 7 nm. In some embodiments, the opening width w1 is in the range of about 8 nm to about 20 nm.

[0037] In some embodiments, the feature depth D of feature 106 is greater than or equal to about 20 nm, greater than or equal to about 50 nm, greater than or equal to about 60 nm, greater than or equal to about 75 nm, greater than or equal to about 100 nm, greater than or equal to about 150 nm, or up to about 200 nm. In some embodiments, the opening width w1 is in the range of about 60 nm to about 100 nm.

[0038] In one or more embodiments, the bottom 110 of feature 106 comprises the top surface of metal 104. Metal 104 may comprise any suitable metal known to those skilled in the art. In one or more embodiments, metal 104 comprises one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), copper (Cu), cobalt (Co), or tantalum (Ta).

[0039] Referring Figure 2 , in one or more embodiments, substrate 100 typically has a native oxide formed thereon during the formation of metal layer 104 and exposure to air. Thus, in one or more embodiments, metal oxide layer 108 is formed on the top surface of metal layer 104. A native oxide such as tungsten oxide (WOx) is formed due to etching of vias / trenches and vacuum breakage. In one or more embodiments, metal oxide layer 108 comprises the oxide of the underlying metal layer. Thus, in one or more embodiments, metal oxide layer 108 comprises one or more of tungsten oxide (WOx), molybdenum oxide (MoOx), ruthenium oxide (RuOx), copper oxide (CuOx), cobalt oxide (CoOx), or tantalum oxide (TaOx).

[0040] Referring Figure 1 With Figure 3 , in operation 14, substrate 100 is pre-cleaned by exposure to a plasma having RF pulses. The pre-cleaning results in the removal of metal oxide layer 108, leaving a clean surface at the bottom of feature 106.

[0041] In one or more embodiments, the plasma comprises one or more of hydrogen (H2) and argon (Ar). In a particular embodiment, the plasma comprises a hydrogen (H2) plasma.

[0042] In one or more unillustrated embodiments, the plasma system comprises an inlet to input one or more process gases into the plasma source through a mass flow controller. The plasma source, including a showerhead, is coupled to a processing chamber to receive one or more process gases to generate a plasma. The plasma source is coupled to an RF power supply. The plasma source uses a high-frequency electric field through the showerhead to generate a hydrogen (H2) plasma in the processing chamber. The plasma bias power is coupled to the pedestal through an RF match to energize the plasma.

[0043] In one or more embodiments, it has been found that exposing substrate 100 to a hydrogen plasma with continuous RF pulses results in high ion energy, causing damage to one or both of the first dielectric layer 102 and the second dielectric layer 104 and reducing selectivity during subsequent metal fill deposition.

[0044] Thus, in one or more embodiments, an RF pulse is introduced while the ion energy is reduced. In one or more embodiments, the pulse frequency is in the range of 100 Hz to 10 kHz. In one or more embodiments, the duty cycle during which the RF pulse is on is in the range of greater than 0% to less than 50%, or in the range of 15% to 50%.

[0045] In one or more embodiments, exposing the substrate 100 to an RF pulse with a hydrogen plasma advantageously removes substantially all of the metal oxide layer 108 from the substrate surface. When used in this manner, "substantially all of the metal oxide" means that after the substrate surface is exposed to an RF pulse with a hydrogen plasma, the total composition of the metal oxide remaining on the substrate surface is less than about 5%, including less than about 4%, less than about 3%, less than about 2%, less than about 1%, less than about 0.5%, and less than about 0.1%.

[0046] Referring Figure 1 to Figure 4 , in one or more embodiments, at operation 16, the metal fill 112 is deposited on the clean metal surface 110 and on the first dielectric layer 102 and on the second dielectric layer 104. The metal fill 112 can include any suitable metal known to those skilled in the art. In some embodiments, the metal fill 112 comprises a transition metal. In some embodiments, the metal fill 112 comprises one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), copper (Cu), cobalt (Co), tantalum (Ta), or an alloy of the foregoing. In some embodiments, depositing the metal fill 112 on the clean metal surface comprises one or more of atomic layer deposition (ALD) and chemical vapor deposition (CVD). In some embodiments, the substrate surface is simultaneously exposed to a first precursor and a second precursor. In some embodiments, the substrate surface is sequentially exposed to a first precursor and a second precursor.

[0047] In some embodiments, depositing the metal fill 112 comprises atomic layer deposition (ALD), which includes exposing the substrate surface to a first precursor, a purge gas, a second precursor, and one or more cycles of a purge gas.

[0048] In some embodiments, depositing the metal fill 112 comprises spatial ALD processing, where a first reaction gas and a second reaction gas are simultaneously delivered to a reaction zone but separated by an inert gas curtain and / or a vacuum curtain. In some embodiments, depositing the metal film comprises co-flowing the first reaction gas and the second reaction gas. In some embodiments, depositing the metal film comprises chemical vapor deposition (CVD).

[0049] A further aspect of the present invention relates to a method that is part of a gap filling process. In some embodiments, a metal fill 112 is deposited on one or more high aspect ratio gap features, including vertical gap features and / or horizontal gap features, and the metal fill 112 in the gap feature 106 forms a horizontal interconnect through which current flows. Without wishing to be bound by theory, features such as feature 106 filled with metal fill 112 conformally deposited on a clean metal surface 110 result in improved electrical operation of the integrated circuit by minimizing power loss and overheating in the integrated circuit, where the clean metal surface 110 has been exposed to RF pulses with a hydrogen plasma according to one or more embodiments of the methods described herein.

[0050] Referring Figure 4 , the metal fill 112 can be conformally deposited on the clean metal surface 110 to fill the feature 106. In some embodiments, the metal fill 112 is conformally deposited on the clean metal surface 110 to a desired thickness to fill the feature 106 by one or more of atomic layer deposition (ALD), chemical vapor deposition (CVD), or pulsed CVD (pCVD).

[0051] The gap filling process can include any suitable gap filling process known to those skilled in the art. In one or more embodiments, the gap filling process includes exposing the semiconductor structure 100 to a metal precursor and a reactant. In some embodiments, the metal precursor includes one or more of a molybdenum precursor, a tungsten precursor, a cobalt precursor, and a ruthenium precursor.

[0052] In some embodiments, the gap filling process is a bottom-up gap filling process. In other embodiments, the gap filling process includes a conformal gap filling process.

[0053] In some embodiments, the metal fill 112 is laterally enclosed by two opposing sidewalls 106s of the trench 106. When used in this manner, "laterally enclosed" means that the deposited material does not extend beyond the intersection between the top surface and the two opposing sidewalls 106s. In some embodiments, the metal fill 112 extends beyond the trench 106. In some embodiments, the metal fill 112 fills the trench 106. When used in this manner, a film that "fills the trench" has a volume that occupies at least 95%, at least 98%, or at least 99% of the volume of the trench 106. In some embodiments, the metal fill 112 filling the trench 106 has a fill height in the range of 30 nm to 75 nm, including in the range of 40 nm to 60 nm.

[0054] Embodiments of the present invention advantageously provide a metal film (e.g., metal fill 112) that is void and crack free or substantially void and crack free. As used in this manner, "substantially void" means that, on an atomic basis, less than about 5%, including less than about 4%, less than about 3%, less than about 2%, less than about 1%, less than about 0.5%, and less than about 0.1% of the total composition of the conformally deposited metal film (e.g., metal fill 112) includes voids and / or cracks.

[0055] The methods described herein may be performed in any suitable processing chamber known to those of skill in the art. The processing chamber may be a SiCoNi TM pre-cleaning chamber available from Applied Materials, Inc. of Santa Clara, California. The processing chamber may be a Selectra TM etching chamber available from Applied Materials, Inc. of Santa Clara, California. The methods described herein may be performed in, for example, an atomic layer deposition (ALD) processing chamber (including a spatial ALD processing chamber), a chemical vapor deposition (CVD) processing chamber, or a pulsed CVD (pCVD) processing chamber.

[0056] In some embodiments, the operations of the methods described herein are each performed within the same processing chamber or within the same processing system. In some embodiments, the operations of the methods described herein are each performed within different processing chambers. In some embodiments, the different processing chambers are connected as part of a processing system. The operations of the methods described herein are each performed within different processing chambers, and each of the different processing chambers is part of a separate processing system. In some embodiments, the operations of the methods described herein are performed without an intervening vacuum break.

[0057] In some embodiments, one or more of the operations of the methods described herein are performed in situ without breaking the vacuum. In some embodiments, one or more of the operations of the methods described herein are performed ex situ. As used herein, the term "in situ" refers to the operations of the methods described herein being each performed within the same processing chamber or within different processing chambers that are connected as part of a processing system such that each of the operations of the methods described herein is performed without an intervening vacuum break. As used herein, the term "ex situ" refers to the operations of the methods described herein being each performed within the same processing chamber or within different processing chambers such that one or more of the operations of the methods described herein are performed with an intervening vacuum break.

[0058] One or more embodiments of the present invention relate to a non-transitory computer-readable medium including instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform the methods described herein, e.g., methods 100 and 200. In some embodiments, the non-transitory computer-readable medium including instructions, when executed by a controller of a processing chamber, causes the processing chamber to expose a substrate surface to a hydrogen (H2) plasma with pulsed RF to remove metal oxides to form a clean metal surface. In some embodiments, the non-transitory computer-readable medium including instructions, when executed by a controller of a processing chamber, causes the processing chamber to deposit a metal fill on the clean metal surface.

[0059] References throughout this specification to "one embodiment", "some embodiments", "one or more embodiments", or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases such as "in one or more embodiments", "in some embodiments", "in one embodiment", or "in an embodiment" throughout this specification are not necessarily referring to the same embodiment of the present invention. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0060] Although the present invention has been described herein with reference to specific embodiments, it will be understood that these embodiments are merely illustrative of the principles and applications of the present invention. Various modifications and variations can be made to the methods and apparatuses of the present invention without departing from the spirit and scope of the present invention, which will be apparent to those skilled in the art. Accordingly, it is intended that the present invention cover modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method of forming a semiconductor device, the method comprising the steps of: Exposing a substrate surface to a hydrogen (H2) plasma and an RF pulse to pre-clean the substrate surface, forming a clean surface; and Depositing a metal fill on the clean surface.

2. The method according to claim 1, wherein the substrate surface comprises a first dielectric layer, a second dielectric layer, and at least one feature formed in the substrate surface.

3. The method according to claim 2, wherein the first dielectric layer comprises silicon oxide (SiOx) and the second dielectric layer comprises silicon nitride (SiN).

4. The method according to claim 2, wherein the at least one feature comprises a bottom surface, the bottom surface comprising a metal layer.

5. The method according to claim 4, wherein the metal layer has a metal oxide layer formed thereon.

6. The method according to claim 5, wherein the hydrogen (H2) plasma and the RF pulse substantially remove all of the metal oxide layer from the metal layer.

7. The method according to claim 4, wherein the metal layer comprises one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), copper (Cu), cobalt (Co), and tantalum (Ta).

8. The method according to claim 5, wherein the metal oxide layer comprises one or more of tungsten oxide (WOx), molybdenum oxide (MoOx), ruthenium oxide (RuOx), copper oxide (CuOx), cobalt oxide (CoOx), and tantalum oxide (TaOx).

9. The method according to claim 1, wherein the metal fill comprises one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), copper (Cu), cobalt (Co), and tantalum (Ta).

10. The method according to claim 1, wherein the RF pulse has a pulse frequency in the range of 100 Hz to 10 kHz.

11. The method according to claim 10, wherein the RF pulse has a duty cycle in the range of 15% to 50%.

12. A processing method of forming a semiconductor device, the method comprising the steps of: Pre-cleaning the substrate by exposing the substrate to a hydrogen (H2) plasma and an RF pulse to form a clean substrate, the substrate having at least one feature formed therein, the at least one feature comprising a plurality of sidewalls of a first dielectric layer and a second dielectric layer, and a bottom surface comprising a metal layer, the metal layer having a metal oxide layer formed on a top surface of the metal layer; and Depositing a metal fill on the clean substrate.

13. The method according to claim 12, wherein the first dielectric layer comprises silicon oxide (SiOx) and the second dielectric layer comprises silicon nitride (SiN).

14. The method according to claim 12, wherein the hydrogen (H2) plasma and the RF pulse substantially remove all of the metal oxide layer from the metal layer.

15. The method according to claim 12, wherein the metal layer comprises one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), copper (Cu), cobalt (Co), and tantalum (Ta).

16. The method according to claim 12, wherein the metal oxide layer comprises one or more of tungsten oxide (WOx), molybdenum oxide (MoOx), ruthenium oxide (RuOx), copper oxide (CuOx), cobalt oxide (CoOx), and tantalum oxide (TaOx).

17. The method according to claim 12, wherein the metal fill comprises one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), copper (Cu), cobalt (Co), and tantalum (Ta).

18. The method according to claim 12, wherein the RF pulse has a pulse frequency in the range of 100 Hz to 10 kHz.

19. The method according to claim 18, wherein the RF pulse has a duty cycle in the range of 15% to 50%.

20. The method according to claim 12, wherein the metal fill is deposited in a bottom-up gap fill process.

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