Semiconductor processing chamber with metal or metalloid fluoride process exposure coating
A coating of YF3, MgF2, CeF4, or HfF4 on semiconductor processing chamber components addresses non-uniform fluorine radical distribution and corrosion, improving process uniformity and reducing maintenance requirements.
Patent Information
- Application Number
- CN202380083919.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-12-07
- Filing Date
- 2023-11-29
- Publication Date
- 2025-07-15
AI Technical Summary
The absorption of fluorine radicals during heat treatment process by existing semiconductor processing chamber components leads to inhomogeneity and corrosion, increasing cost and process inhomogeneity.
Metal or metallic fluoride coatings, such as YF3, MgF2, CeF4, HfF4 and LaF3, are deposited on the surface of the semiconductor processing chamber components, with thicknesses ranging from 10 nm to 290 nm and formed by atomic layer deposition or chemical vapor deposition processes.
It reduces the absorption of fluorine radicals, improves process uniformity, reduces component corrosion and cost, and extends component service life.
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Figure CN120322844A_ABST
Abstract
Description
Cross - Reference to Related Applications
[0001] This application claims the priority of U.S. Application No. 63 / 430,747, filed on December 7, 2022, which is incorporated herein by reference for all purposes. Background Art
[0002] The background description provided here is for the purpose of generally presenting the background of the present disclosure. The work of the currently named inventors within the scope described in this background art section and aspects of the specification that could not be determined to be prior art at the time of filing the application are neither expressly nor impliedly admitted to be prior art against the present disclosure.
[0003] The present disclosure relates to the manufacture of semiconductor devices. More specifically, the present disclosure relates to semiconductor processing chambers that can be used for heat treatment.
[0004] During semiconductor wafer processing, semiconductor processing chambers are used to process semiconductor devices. Some semiconductor processes can use heat treatment instead of plasma processes. Some heat treatments can use thermally generated fluorine - containing radicals. Summary of the Invention
[0005] To achieve the above, and in accordance with the purposes of the present disclosure, a component for use in a semiconductor processing chamber is provided. A process - exposed coating is located on the surface of the component body, wherein the process - exposed coating includes at least one of YF3, MgF2, CeF4, HfF4, and LaF3, and wherein the process - exposed coating has a thickness in the range of 10 nm to 290 nm.
[0006] In another aspect, a method for manufacturing a component for use in a plasma processing chamber is provided. At least one of atomic layer deposition and chemical vapor deposition deposits a process - exposed coating on the surface of the component body, wherein the process - exposed coating includes at least one of YF3, MgF2, CeF4, HfF4, and LaF3, and wherein the process - exposed coating has a thickness in the range of 10 nm to 290 nm.
[0007] These and other features of the present disclosure will be described in more detail below in conjunction with the drawings and in the detailed description. Brief Description of the Drawings
[0008] The present disclosure is depicted by way of example (and not limitation) in the figures of the accompanying drawings, where like reference numerals represent similar elements, and wherein:
[0009] Figure 1 is a high - level flowchart used in some embodiments.
[0010] Figure 2A-D is a schematic diagram of a component body processed according to an embodiment.
[0011] Figure 3 is a schematic diagram of a plasma processing system that can be used in some embodiments.
[0012] In the figures, like reference numerals are sometimes used to indicate like structural elements. It should also be understood that the illustrations in the figures are schematic and not drawn to scale. Detailed Description
[0013] The present disclosure will now be described in detail with reference to some preferred embodiments as illustrated in the accompanying drawings. To provide a thorough understanding of the invention, numerous specific details are set forth in the following description. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without some or all of these specific details. In other instances, well-known processing steps and / or structures have not been described in detail in order not to obscure the present disclosure.
[0014] During thermal atomic layer etching, fluorine radicals are thermally generated and used for atomic layer etching. The fluorine radicals may be absorbed by various semiconductor processing chamber components, causing the semiconductor processing chamber components to become fluorine radical absorbers. When the semiconductor chamber components act as fluorine radical absorbers, more fluorine radicals are required, increasing costs, and the fluorine radical distribution becomes less uniform, resulting in more process non-uniformity and increased defects. In addition, the fluorine radicals may corrode the semiconductor processing chamber components.
[0015] Some embodiments provide components of a semiconductor processing chamber that act as attenuated fluorine radical absorbers. Some embodiments provide components of a semiconductor processing chamber that are subject to less fluorine radical corrosion.
[0016] For ease of understanding, Figure 1 is a process flow diagram used in some embodiments that provides components for a semiconductor processing chamber. In some embodiments, a component body is provided (step 104). Figure 2AIt is a schematic cross-sectional view of a part of the component body 204 of the component 200. The component body 204 has a surface 208. In some embodiments, the component body 204 includes at least one of a metal material and a ceramic material. In some embodiments, the metal material includes at least one of aluminum, iron, titanium, nickel, and molybdenum. In some embodiments, the component body 204 includes multiple layers of different materials, such as different metals. In some embodiments, when the metal material is iron, the component body 204 includes stainless steel. In some embodiments, the ceramic material includes at least one of alumina, yttria, lanthanum zirconium oxide (LZO), yttria-stabilized zirconia (YSZ), zirconia toughened alumina (ZTA), zirconia, and machinable silicate and aluminate glasses, such as those of Corning's
[0017] Optionally, in some embodiments, an intermediate layer is deposited on the surface 208 of the component body 204 (step 108). Figure 2B It is a schematic cross-sectional view of a part of the component 200 after an intermediate layer 212 is deposited on the surface 208 of the component body 204. In some embodiments, the intermediate layer includes ceramics. In some embodiments, the intermediate layer is an adhesion layer. In some embodiments, the oxide of the substrate is used, but due to the availability of Al2O3, alumina (Al2O3) is used in some embodiments. In some embodiments, the intermediate layer 212 including a glass or a metal matrix composite (MMC) is selected to provide stress relief. In some embodiments, the intermediate layer includes an MMC, such as AlSiC, or a matrix of Al2O3 and aluminum (Al). In some embodiments, the intermediate layer 212 has a thickness in the range of 0.5 nm to 1 micrometer (μm). In some embodiments, the intermediate layer 212 is deposited by at least one of atomic layer deposition, chemical vapor deposition, cold spraying, glazing, hybrid aerosol deposition, detonation spraying, and physical vapor deposition. In applications, in cases where the surface to be coated of the component has a complex three-dimensional shape (such as a nozzle or a gas diffusion plate, where the interior of the pores needs to be coated), only conformal deposition processes are used. In some embodiments, the intermediate layer 212 is deposited by a conformal deposition process of at least one of atomic layer deposition or chemical vapor deposition.
[0018] A coating is deposited on the surface of the component body (step 112). In some embodiments, the deposition process deposits a metal or metalloid fluoride coating, where the metal or metalloid is at least one of yttrium, magnesium, cerium, hafnium, and lanthanum. In some embodiments, the metal or metalloid fluoride coating is deposited by at least one of atomic layer deposition (ALD) or chemical vapor deposition (CVD). In some embodiments, the metal or metalloid fluoride coating is directly deposited on the surface of the component body. In some embodiments, the metal or metalloid fluoride coating is deposited on an intermediate layer on the surface of the component body. In some embodiments, the metal or metalloid fluoride coating includes at least one of yttrium trifluoride (YF3), magnesium fluoride (MgF2), cerium(IV) fluoride (CeF4), hafnium fluoride (HfF4), and lanthanum trifluoride (LaF3). In some embodiments, the metal or metalloid fluoride coating includes at least one of yttrium trifluoride (YF3), cerium(IV) fluoride (CeF4), hafnium fluoride (HfF4), and lanthanum trifluoride (LaF3). Figure 2C is a schematic cross-sectional view of a portion of component 200 after a metal or metalloid fluoride coating 216 is deposited on intermediate layer 212 on surface 208 of component body 204. In some embodiments, the YF3 coating is deposited by an atomic layer process. In some embodiments, the metal or metalloid fluoride coating has a thickness in the range of 10 nm to 290 nm. In some embodiments, the metal or metalloid fluoride coating has a thickness in the range of 10 nm to 150 nm. In some embodiments, the metal or metalloid fluoride coating has a thickness in the range of 10 nm to 100 nm. In various embodiments, the metal or metalloid fluoride coating 216 is crystalline, amorphous, or a combination thereof. The crystalline material can be single crystal or polycrystalline.
[0019] Figure 2D is a schematic cross-sectional view of a portion of component 200 provided in some embodiments. In some embodiments, component 200 is part of a showerhead having a channel 224 that serves as a gas channel. The gas channel can have a high aspect ratio, where the depth-to-width aspect ratio is at least 5:1. Due to using ALD or CVD to deposit the metal or metalloid fluoride coating 216, the metal or metalloid fluoride coating 216 can be deposited on non-conformal surfaces, where some surfaces are not along the line of sight. Additionally, in some embodiments, the ALD or CVD process provides a metal or metalloid fluoride coating 216 that has a purity of at least 99% by weight and a porosity of less than 0.1% by volume. In some embodiments, the purity of the metal or metalloid fluoride coating 216 is at least 99.9% by weight, such that the metal or metalloid fluoride coating 216 consists essentially of one or more of YF3, MgF2, CeF4, HfF4, and LaF3.
[0020] Install component 200 in a semiconductor processing chamber (step 116). Component 200 is used in a semiconductor processing chamber to process multiple wafers (step 120). In some embodiments, the semiconductor process is a thermal etching process, such as thermal atomic layer etching. In some embodiments, the first stack has a film layer that is etched using thermal atomic layer etching. In some embodiments, the first stack is removed and a second stack is disposed in the semiconductor processing chamber, where layers are etched using thermal atomic layer etching. In some embodiments, fluorine radicals are provided during thermal atomic layer etching. In some embodiments, the metal or metalloid fluoride coating 216 does not absorb fluorine radicals, such that the metal or metalloid fluoride coating 216 does not act as an absorber of fluorine radicals, thereby providing more uniform etching of the upper layer of the substrate. In some embodiments, the more uniform etching provides uniformity at different locations on the wafer and uniformity between wafers. In some embodiments, the metal or metalloid fluoride coating 216 reduces the time and number of cycles required for component conditioning or seasoning, because some conditioning or seasoning processes can be fluorination of the component surface. The reduction in conditioning or seasoning time allows the chamber to process more wafers during the useful life of the component and the chamber. Additionally, the metal or metalloid fluoride coating 216 reduces corrosion caused by fluorine radicals, thereby reducing chamber corrosion and resulting contaminants. In some embodiments, the semiconductor processing exposes the metal or metalloid fluoride coating 216 to a halogen gas without radicals. To enable the metal or metalloid fluoride coating 216 to prevent component 200 from becoming an absorber of fluorine radicals, in some embodiments, the metal or metalloid fluoride coating 216 is a process-exposed coating or a top coating, where there is no other coating between the metal or metalloid fluoride coating 216 and the semiconductor manufacturing process using fluorine radicals.
[0021] In some embodiments, the intermediate layer 212 is at least one of a bonding layer, a sealing layer, and a stress relief layer. The bonding layer increases the adhesion between the surface 208 of the component body 204 and the metal or metalloid fluoride coating 216. The sealing layer seals the surface 208 of the component body 204. The stress relief layer absorbs stress generated by at least one of the component body 204 or the metal or metalloid fluoride coating 216. In some embodiments, the metal or metalloid fluoride coating 216 eliminates the need to provide a chamber cleaning process between wafers.
[0022] Figure 3FIG. 0 is a schematic diagram of a semiconductor processing chamber 300 used to process substrates in some embodiments. In some embodiments, the semiconductor processing chamber 300 includes a gas distribution plate 306 that provides a gas inlet, and an electrostatic chuck (ESC) 316 that is within the semiconductor processing chamber 304 and is surrounded by a chamber wall 350. Within the semiconductor processing chamber 304, a stack 307 is located on top of the ESC 316. The ESC 316 can provide a bias voltage from an ESC power supply 348. A gas source 310 is connected to the semiconductor processing chamber 304 through the gas distribution plate 306. An ESC temperature controller 351 is connected to the ESC 316 and provides temperature control of the ESC 316. A radio frequency (RF) power supply 330 provides RF power to the ESC 316 and an upper electrode. In some embodiments, the upper electrode is the gas distribution plate 306. In some embodiments, power supplies of 400 kilohertz (kHz), 13.56 megahertz (MHz), 1 MHz, 2 MHz, 60 MHz, and / or optionally 27 MHz make up the RF power supply 330 and the ESC power supply 348. A controller 335 is controllably connected to the RF power supply 330, the ESC power supply 348, an exhaust pump 320, and the gas source 310. A high flow liner 360 is a liner within the semiconductor processing chamber 304 that confines the gas from the gas source and has slots 362. The slots 362 maintain a controlled gas flow from the gas source 310 to the exhaust pump 320. An example of such a semiconductor processing chamber is an etch system manufactured by Lam Research Corporation (Fremont, CA). The processing chamber can be a capacitively coupled plasma (CCP) reactor or an inductively coupled plasma (ICP) reactor.
[0023] In various embodiments, the components can be various parts of a plasma processing chamber, such as a confinement ring, an edge ring, an electrostatic chuck, a ground ring, a chamber liner (such as a pinnacle), a door liner, a showerhead, or other components. Other components of other types of plasma processing chambers can be used. For example, in some embodiments, a plasma rejection ring on an angled etch chamber can be coated. In another example, the plasma processing chamber can be an inductive plasma processing chamber where the component is a dielectric inductive power window. In some embodiments, one or more but not all surfaces are coated.
[0024] Although the present disclosure has been described with respect to several preferred embodiments, there are still changes, substitutions, modifications, and various different alternatives that fall within the scope of the present disclosure. It is noted that there are many alternative ways to implement the methods and apparatuses of the present disclosure. Accordingly, the appended claims are intended to be construed to include all such changes, substitutions, and various different alternatives that are within the true spirit and scope of the present disclosure. As used herein, the phrase "A, B, or C" should be interpreted to mean a logic of "A or B or C" using the non-exclusive logical "or (OR)", and should not be interpreted to mean only one of A or B or C. Each step in a process may be an optional and non-essential step. One or more steps may be removed or steps may be in a different order in different embodiments. Additionally, various embodiments may provide different steps simultaneously rather than sequentially.
Claims
1. A component for use in a semiconductor processing chamber, comprising: A component body; And A process-exposed coating located on the surface of the component body, wherein the process-exposed coating comprises at least one of YF3, MgF2, CeF4, HfF4, and LaF3, and wherein the process-exposed coating has a thickness in the range of 10 nm to 290 nm.
2. The component according to claim 1, wherein the process-exposed coating has a purity of at least 99% by weight.
3. The component according to claim 1, wherein the process-exposed coating has a porosity of less than 0.1% by volume.
4. The component according to claim 1, wherein the component body comprises at least one of a metallic material and a ceramic material.
5. The component according to claim 1, wherein the process-exposed coating has a thickness in the range of 10 nm to 100 nm.
6. The component according to claim 1 further comprises: An intermediate layer located between the component body and the process-exposed coating.
7. The component according to claim 6, wherein the intermediate layer is at least one of a bonding layer, a sealing layer, and a stress-relieving layer.
8. The component according to claim 1, wherein the process-exposed coating is exposed to a thermal etching process.
9. The component according to claim 1, wherein the process-exposed coating is crystalline.
10. The component according to claim 1, wherein the process-exposed coating is amorphous.
11. A method of manufacturing a component for use in a plasma processing chamber, the method comprising: Providing a component body; And Depositing a process-exposed coating on the surface of the component body by at least one of atomic layer deposition and chemical vapor deposition, wherein the process-exposed coating comprises at least one of YF3, MgF2, CeF4, HfF4, and LaF3, and wherein the process-exposed coating has a thickness in the range of 10 nm to 290 nm.
12. The method according to claim 11, wherein the component body comprises at least one of a metallic material and a ceramic material.
13. The method according to claim 11, wherein the process-exposed coating has a thickness in the range of 10 nm to 100 nm.
14. The method according to claim 11, further comprising depositing an intermediate layer on the surface of the component body before depositing the process-exposed coating by at least one of atomic layer deposition and chemical vapor deposition.
15. The method according to claim 14, wherein the intermediate layer is at least one of a bonding layer and a stress-relieving layer.
16. The method according to claim 11, further comprising installing the component in a semiconductor processing chamber.
17. The method according to claim 16, further comprising exposing the process-exposed coating to a thermal etching process.
18. The method according to claim 11, wherein the deposition by at least one of atomic layer deposition and chemical vapor deposition uses atomic layer deposition.