3D memory cell and array architecture and process

Abstract

Various 3D memory cells, array architectures, and processes are disclosed. In one embodiment, a memory cell structure is provided that is formed by alternately depositing a plurality of semiconductor layers and a plurality of sacrificial layers to form a stack; forming a vertical bit line hole through the stack using a deep trench process; forming a floating body in the semiconductor layer through the bit line hole by using an isotropic doping process; depositing a conductor material to fill the bit line holes; the sacrificial layer is removed; depositing a gate dielectric layer between the semiconductor layers; and depositing a gate material onto the gate dielectric layer.

Description

[0001] Priority Claimed

[0002] This application is a United States Continuation-in-Part (CIP) application of U.S. application Ser. No. 17 / 937,432, filed Sep. 30, 2022, and titled “Memory Cell and Array Architectures”.

[0003] This application claims the benefit of priority under 35 U.S.C. 119(e) of U.S. Provisional Patent Application Ser. No. 63 / 398,807, filed Aug. 17, 2022, and titled “Memory Cell and Array Architectures and Operation Conditions”; U.S. Provisional Patent Application Ser. No. 63 / 406,255, filed Sep. 14, 2022, and titled “3D Cell and Array Structures”; U.S. Provisional Patent Application Ser. No. 63 / 413,493, filed Oct. 5, 2022, and titled “3D Cell and Array Structures”; U.S. Provisional Patent Application Ser. No. 63 / 418,698, filed Oct. 24, 2022, and titled “3D Cell and Array Structures”; U.S. Provisional Patent Application Ser. No. 63 / 445,670, filed Feb. 14, 2023, and titled “3D Cell and Array Structures”; U.S. Provisional Patent Application Ser. No. 63 / 445,672, filed Feb. 14, 2023, and titled “3D Cell and Array Structures”; U.S. Provisional Patent Application Ser. No. 63 / 449,938, filed Mar. 3, 2023, and titled “Novel 3D DRAM Cell, Array and Technology”; U.S. Provisional Patent Application Ser. No. 63 / 458,059, filed Apr. 7, 2023, and titled “3D Cell and Array Structures and Processes”; and U.S. Provisional Patent Application Ser. No. 63 / 460,289, filed Apr. 18, 2023, and titled “3D Cell and Array Structures and Processes”, the entire contents of which are incorporated herein by reference.

[0004] The application with application number 17 / 937,432 claims the priority benefits of the U.S. Provisional Patent Application No. 63 / 398,807, titled "Memory Cell and Array Architectures and Operation Conditions", filed on August 17, 2022, the U.S. Provisional Patent Application No. 63 / 295,874, titled "Alpha-RAM (α-RAM) or Alpha-DRAM (α-DRAM) Technology", filed on January 1, 2022, the U.S. Provisional Patent Application No. 63 / 291,380, titled "3D DRAM-replacement Technologies", filed on December 18, 2021, the U.S. Provisional Patent Application No. 63 / 254,841, titled "3D DRAM-replacement Technologies", filed on October 12, 2021, and the U.S. Provisional Patent Application No. 63 / 251,583, titled "3D DRAM-replacement Technologies", filed on October 1, 2021. The entire contents of these patent applications are incorporated herein by reference.

[0005] Cross-reference to Related Applications

[0006] This application is related to the following co-pending application, titled "3D MEMORY CELLS AND ARRAY ARCHITECTURES", Attorney Docket No. SIONS.PT9.CIP1, filed on May 2, 2023. Technical Field

[0007] Exemplary embodiments of the present invention generally relate to the field of memory, and more particularly, the present invention relates to memory cell and array architectures and associated processes. Background Art

[0008] As the complexity and density of electronic circuits increase, memory size, complexity, and cost are important considerations. One way to increase memory capacity is to use three-dimensional (3D) array structures. 3D array structures have currently been successfully used in NAND flash memory. However, for dynamic random access memory (DRAM), due to its special one-transistor-one-capacitor (1T1C) cell structure, a cost-effective 3D array structure has not been achieved. Summary of the Invention

[0009] In various exemplary embodiments, three-dimensional (3D) memory cells, array structures, and associated processes are disclosed. In one embodiment, a novel 3D array structure for implementing DRAM using floating body cells is disclosed. The array structure is formed using a deep trench process similar to 3D NAND flash. Thus, ultra-high density DRAM can be achieved. In one embodiment, 3D NOR-type memory cells and array structures are provided. The disclosed memory cells and array structures are applicable to many technologies. For example, the memory cells and array structures of the present invention are applicable to dynamic random access memory (DRAM), floating body cell (FBC) memory, NOR-type flash memory, and thyristors.

[0010] In one exemplary embodiment, a memory cell structure is provided, including: a first semiconductor material; a floating body semiconductor material having an inner side surrounding and connected to the first semiconductor material; and a second semiconductor material having an inner side surrounding and connected to the floating body semiconductor material. The memory cell structure further includes: a first dielectric layer connected to the top surface of the floating body material; a second dielectric layer connected to the bottom surface of the floating body material; a front gate connected to the first dielectric layer; and a back gate connected to the second dielectric layer.

[0011] In one exemplary embodiment, a three-dimensional (3D) memory array is provided, including a plurality of memory cells separated by dielectric layers to form a memory cell stack. Each memory cell in the memory cell stack includes: a bit line formed of either a first semiconductor material or a first conductor material; a floating body semiconductor material having an inner side surrounding and connected to the bit line; a source line formed of either a second semiconductor material or a second conductor material, having an inner side surrounding and connected to the floating body semiconductor material; and a word line formed of a third conductor material, coupled to the floating body semiconductor through a dielectric layer to form a gate of the memory cell. Additionally, the bit lines of the memory cell stack are connected to form vertical bit lines.

[0012] In one exemplary embodiment, a memory cell structure is formed by the following process: alternately depositing a plurality of semiconductor layers and a plurality of sacrificial layers to form a stack; forming vertical bit line holes through the stack using a deep trench process; forming a floating body in the semiconductor layers through the bit line holes using an isotropic doping process; depositing a conductor material to fill the bit line holes; removing the sacrificial layers; depositing a gate dielectric layer between the semiconductor layers; and depositing a gate material onto the gate dielectric layer.

[0013] Additional features and advantages of the exemplary embodiments of the present invention will become apparent from the detailed description, drawings, and claims set forth below. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Exemplary embodiments of the present invention will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the invention. However, it should not be regarded as limiting the invention to the specific embodiments, but only for explanation and understanding.

[0015] Figure 1A An embodiment of the cell structure of a three-dimensional (3D) NOR-type array constructed according to the present invention is shown.

[0016] Figure 1B Shown is Figure 1A An embodiment of the internal cell structure of the cell shown.

[0017] Figure 1C Another embodiment of the cell structure constructed according to the present invention is shown.

[0018] Figure 1D Shown is Figure 1C The cell structure of, in which some parts of the cell are removed.

[0019] Figure 1E Another embodiment of the cell structure constructed according to the present invention is shown.

[0020] Figure 1F Shown is Figure 1E The internal cell structure of the cell shown, in which some parts of the cell are removed.

[0021] Figure 1G Another embodiment of the cell structure constructed according to the present invention is shown.

[0022] Figure 1H Shown is Figure 1G The internal cell structure of the cell shown, in which some parts of the cell are removed.

[0023] Figure 1I Another embodiment of the cell structure constructed according to the present invention is shown.

[0024] Figure 1J Shown is Figure 1I The internal cell structure of the cell shown, in which some parts of the cell are removed.

[0025] Figure 1K Another embodiment of the cell structure constructed using a junctionless thin film transistor according to the present invention is shown.

[0026] Figure 1L Shown is a cross-sectional view of the cell structure shown taken along the section indication line A-A'. Figure 1K An embodiment of the cross-sectional view.

[0027] Figure 1MAnother embodiment of a cell structure using a junctionless thin film transistor according to the present invention is shown.

[0028] Figure 1N A cross-sectional view of the cell structure taken along the cross-section indication line A-A' is shown. Figure 1M The cross-sectional view of the cell structure shown.

[0029] Figure 1O Another embodiment of a cell structure using a junctionless thin film transistor according to the present invention is shown.

[0030] Figure 1P A cross-sectional view of the cell structure taken along the cross-section indication line A-A' is shown. Figure 1O The cross-sectional view of the cell structure shown.

[0031] Figure 1Q An exemplary embodiment of a three-dimensional (3D) NOR-type memory cell structure configured using a floating body cell (FBC) according to the present invention is shown.

[0032] Figure 1R Shown is Figure 1Q The cell structure shown, in which the front gate and the gate dielectric layer are removed.

[0033] Figure 1S A cell formed using a PMOS transistor is shown.

[0034] Figure 1T Shown is based on Figure 1Q An embodiment of an array structure of the cell structure shown.

[0035] Figure 1U Another embodiment of an array structure according to the present invention is shown.

[0036] Figure 1V Shown is Figure 1T The equivalent circuit diagram of the array structure shown.

[0037] Figure 1W Shown is Figure 1T Another embodiment of the equivalent circuit diagram of the array structure shown.

[0038] Figure 2A Another embodiment of a cell structure constructed for a 3D NOR-type flash memory according to the present invention is shown.

[0039] Figure 2B Shown is Figure 2A The internal cell structure of the cell shown, in which some parts of the cell are removed.

[0040] Figure 2C Another embodiment of a cell structure constructed for a 3D non-volatile random access memory according to the present invention is shown.

[0041] Figure 2D shows Figure 2C the internal cell structure of the illustrated embodiment, where some parts of the cell are removed.

[0042] Figures 3A to 3C shows an embodiment of a 3D array structure constructed according to the present invention.

[0043] Figures 4A to 4I shows an embodiment of a brief process step for forming a 3D array including Figure 1A the cell structure shown.

[0044] Figures 5A to 5C shows an embodiment of a brief process step for forming an array using Figure 1E the cell structure shown.

[0045] Figures 6A to 6F shows an embodiment of a brief process step for forming an array using Figure 1I the cell structure shown.

[0046] Figures 7A to 7D shows an embodiment of a brief process step for forming an array including Figure 1I the cell structure shown.

[0047] Figures 8A to 8E shows an embodiment of a brief process step for forming an array including Figure 1G another embodiment of the cell structure shown.

[0048] Figures 9A to 9C shows another embodiment of a brief process step for forming Figures 1E to 1F the cell structure shown.

[0049] Figures 10A to 10E shows another embodiment of a brief process step performed for forming an array including Figure 1K the cell structure shown.

[0050] Figures 11A to 11D shows another embodiment of a brief process step for a configuration configured to form an array including Figure 1M the cell structure shown.

[0051] Figures 12A to 12E shows another embodiment of a brief process step for a configuration configured to form an array including Figure 1O the cell structure shown. Detailed Description

[0052] Those of ordinary skill in the art will recognize that the following detailed description is illustrative only and is not intended to be limiting in any way. Other embodiments of the present invention will occur readily to those of skill in the art who have benefited from the present disclosure. Reference will now be made in detail to the implementation of exemplary embodiments of the present invention as illustrated in the accompanying drawings. Throughout the drawings and the following detailed description, the same reference numerals will be used to refer to the same or like parts.

[0053] In various exemplary embodiments, three-dimensional (3D) memory cells, array structures, and associated processes are disclosed. For example, 3D NOR-type cells and array structures and processes are disclosed. The various embodiments of the present invention can be applied to many technologies. For example, aspects of the present invention can be applied to use floating body cells (FBCs), NOR-type flash memories, ferroelectric random access memories (FRAMs), resistive random access memories (RRAMs), phase change memories (PCMs), magnetoresistive random access memories (MRAMs), and dynamic random access memories (DRAMs) with memory elements referred to as "synapses" in in-memory computing or neural network arrays for artificial intelligence (AI) applications. In addition, embodiments of the present invention can be applied to other memory applications not listed.

[0054] Figure 1A An embodiment of the cell structure of a three-dimensional (3D) NOR-type array constructed in accordance with the present invention is shown. Figure 1A The cell structure shown includes: a semiconductor layer (which includes silicon or polysilicon) forming a vertical bit line (BL) 101, a floating body 102 formed of silicon or polysilicon, and a horizontal source line (SL) 103 formed of silicon or polysilicon. The cell also includes a front gate 104a, a rear gate 104b, a first gate dielectric layer 105a, and a second gate dielectric layer 105b. In one embodiment, the gates 104a and 104b are formed of a conductor material such as metal or heavily doped polysilicon. The front gate 104a and the rear gate 104b can be connected to a horizontal word line (WL).

[0055] The cell can be formed as an NMOS or PMOS transistor. For the NMOS cell embodiment, the bit line 101 and the source line 103 are N+-type doped, while the floating body 102 is P-type doped. For the PMOS cell embodiment, the bit line 101 and the source line 103 are P+-type doped, while the floating body 102 is N-type doped.

[0056] Figure 1B is shown Figure 1AAn embodiment of the internal cell structure of the cell shown, in which the front gate 104a, the gate dielectric layer 105a, and a part of the BL 101 are removed. Although the embodiment shows that the shapes of the bit line 101 and the floating body 102 are circular, in other embodiments, the bit line 101 and the floating body 102 can also have any suitable shapes, such as square, rectangular, triangular, hexagonal, etc. These variations are within the scope of the embodiment.

[0057] Depending on the cell type and technology, the gate dielectric layers 105a and 105b can be formed of a variety of different materials and structures. For example, in one embodiment, the cell can be formed as a floating body cell for DRAM applications. For this embodiment, the gate dielectric layers 105a and 105b are thin gate oxide layers or high-K material layers, such as hafnium oxide (HfO2). In another embodiment, the gate dielectric layers 105a and 105b are formed of other suitable materials to form NOR-type flash memories, ferroelectric random access memories (FRAMs), resistive random access memories (RRAMs), phase change memories (PCMs), magnetoresistive random access memories (MRAMs), etc., as Figures 2A to 2D shown.

[0058] Figure 1C Another embodiment of the cell structure constructed according to the present invention is shown. This embodiment is similar to Figure 1A the embodiment in

[0059] Figure 1D shown, except that a metal vertical bit line 101 is formed by a metal core at the center of the semiconductor layer 109 to reduce the bit line resistance. Figure 1C The cell structure of

[0060] Figure 1E Another embodiment of the cell structure constructed according to the present invention is shown. This embodiment is similar to Figures 1C to 1DThe embodiments shown. In one embodiment, the drain region 107 is formed of silicon or polysilicon having a heavily doped type opposite to the doping type of the floating body 102. For example, "opposite type of doping" means that P-type (positive) doping is opposite to N-type (negative) doping. For example, if the floating body 102 includes P-type doping, the drain region 107 includes N-type doping, which is the opposite type of doping. If the floating body 102 includes N-type doping, the drain region 107 includes P-type doping, which is the opposite type of doping. The terms "heavily doped" and "lightly doped" are relative terms describing the amount of doping. When a semiconductor is doped with an excessive amount of electrons or holes, it is called a heavily doped semiconductor, represented by N+ or P+ respectively. When a semiconductor is doped with a small amount of electrons or holes, it is called a lightly doped semiconductor, represented by N- or P- respectively. As Figure 1E shown, the vertical bit line holes are filled with metal to form the metal bit line 101 to reduce the bit line resistance.

[0061] Figure 1F shows Figure 1E the internal cell structure of the cell shown, in which the front gate 104a, the gate dielectric layer 105a, and a part of the metal bit line 101 are removed.

[0062] Figure 1G shows another embodiment of the cell structure constructed according to the present invention. This embodiment is similar to Figures 1C to 1D the embodiment shown, except that the source line 103 is formed of a conductor material such as metal to reduce the source line resistance. A source region 108 including a semiconductor material such as silicon or polysilicon is formed between the metal source line 103 and the floating body 102. The source region 108 has a heavily doped type opposite to the doping type of the floating body 102.

[0063] Figure 1H represents Figure 1G the internal cell structure of the cell shown in, in which the front gate 104a, the gate dielectric layer 105a, and a part of the metal BL 101 and the semiconductor layer 109 are removed.

[0064] Figure 1I shows another embodiment of the cell structure constructed according to the present invention. This embodiment is similar to Figures 1A to 1B the embodiment shown, except that the bit line 101 and the source line 103 are formed of metal. The floating body 102 is formed of a semiconductor material such as silicon or polysilicon. In one embodiment, the floating body 102 has a heavy doping of N+ or P+ type. This forms a junctionless unit transistor. In another embodiment, the floating body 102 has a light doping of N- type or P- type. This forms a Schottky junction unit transistor.

[0065] Figure 1J shows Figure 1IThe internal cell structure of the shown cell, in which the front gate 104a, the gate dielectric layer 105a, and a part of the BL 101 are removed.

[0066] Figure 1K Another embodiment of a cell structure constructed using a junctionless thin-film transistor according to the present invention is shown. This embodiment is similar to the one shown, except that a semiconductor layer 115 including silicon, polysilicon, germanium (Ge), indium gallium zinc oxide (IGZO), tungsten-doped indium oxide semiconductor, or any other suitable semiconductor material surrounds the BL 101 and an insulator 116 including an oxide or a nitride. Figures 1A to 1B In one embodiment, the semiconductor layer 115 is heavily doped with N-type or P-type to form the channel of the cell transistor. In one embodiment, the bit line 101 and the source line 103 are formed of a conductor material such as metal or heavily doped polysilicon. Figure 1K The cross-section indicating line A-A' is also shown.

[0067] Figure 1L It shows along Figure 1K the cross-section indicating line A-A' shown Figure 1K an embodiment of a cross-sectional view of the cell structure shown.

[0068] Figure 1M Another embodiment of a cell structure using a junctionless thin-film transistor according to the present invention is shown. This embodiment is similar to the one shown, except for the semiconductor region 109. Figures 1A to 1B The semiconductor region 109 is formed of a material different from that of the floating body 102. For example, if the floating body 102 is formed of silicon or polysilicon, the semiconductor region 109 is formed of silicon germanium (SiGe), silicon carbide (SiC), or any other suitable semiconductor material. This configuration forms a heterostructure junction between the two materials and forms a quantum well for storing charges, such as holes, inside the semiconductor region 109. This increases the data retention time of the cell.

[0069] Figure 1N It shows along Figure 1M the cross-section indicating line A-A' shown in Figure 1M a cross-sectional view of the cell structure shown.

[0070] Figure 1QAn exemplary embodiment of a three-dimensional (3D) NOR-type memory cell structure configured using a floating body cell (FBC) according to the present invention is shown. For example, a 3D NOR-type array may include a multi-layer floating body cell array that increases memory capacity. A floating body cell is essentially a transistor having a floating body. The floating body stores charges such as electrons or holes to represent data. The cell structure includes a control gate, a drain, a source, and a floating body. In a 3D memory array, the control gate, drain, and source of the cell are connected to a word line (WL), a bit line (BL), and a source line (SL), respectively.

[0071] In Figure 1Q the cell structure shown, N+ silicon or polysilicon forms the bit line (BL) 101, and a P- floating body 102 is used for charge storage. N+ silicon or polysilicon forms the source line (SL) 103. The cell can be formed as Figure 1Q the double-gate transistor shown or Figure 1R the single-gate transistor shown. For Figure 1Q the double-gate transistor shown, the cell structure includes two control gates, respectively referred to as a front gate 104a and a back gate 104b. Both the front gate 104a and the back gate 104b are coupled to the floating body 102 through gate dielectric layers 105a and 105b, respectively. The gate dielectric layer is an insulating layer between the gate and the body of the transistor. When an appropriate voltage is applied to the front gate 104a or the back gate 104b, a front gate channel (FGC) 1014 or a back gate channel (BGC) 1012 is formed in the surface of the floating body 102 below the gate dielectric layers 105a and 105b to conduct current between the bit line 101 and the source line 103. In one embodiment, the front gate 104a and the back gate 104b are connected to different word lines (WL).

[0072] In one embodiment, the P- floating body 102 includes as Figure 1QMultiple surfaces are shown. The inner surface 1002 surrounds and is connected to the BL 101. The outer surface 1004 is connected to the source line 103. The top surface 1008 is connected to the dielectric layer 105a, and the bottom surface 1006 is connected to the dielectric layer 105b. Thus, in one embodiment, a memory cell structure is provided, comprising: a first semiconductor material BL 101; a floating body semiconductor material 102 having an inner surface 1002 that surrounds and is connected to the first semiconductor material BL 101; and a second semiconductor material SL 103 having an inner surface 1010 that surrounds and is connected to the floating body semiconductor material 102. The memory cell structure further includes: a first dielectric layer 105a connected to the top surface 1008 of the floating body material 102; a second dielectric layer 105b connected to the bottom surface 1006 of the floating body material 102; a front gate 104a connected to the first dielectric layer 105a; and a back gate 104b connected to the second dielectric layer 105b. In various embodiments, minor modifications can be made to the disclosed structure, such as adding a lightly doped drain (LDD), halo implantation, pocket implantation, or channel implantation, all of which are included within the scope of the present invention.

[0073] Figure 1R is shown Figure 1Q The cell structure shown, in which the front gate 104a, the gate dielectric layer 105a, and a portion of the bit line 101 are removed. The P - floating body 102 forms a donut shape as shown. Although this embodiment shows the shapes of the bit line 101 and the floating body 102 as circular, it is obvious that they can also have any desired shape, such as square, rectangular, triangular, hexagonal, etc. These variations will remain within the scope of the present invention.

[0074] In one embodiment, as Figure 1R shown, the cell structure includes only a single gate. As shown, the floating body 102 is only coupled to one gate 104b. Figure 1T An embodiment of a 3D array structure using this embodiment of the cell structure is shown.

[0075] Figure 1Q The embodiment shown uses an NMOS transistor as the cell. In Figure 1S Another embodiment shown, a PMOS transistor is used to form the cell. The bit line 101, the floating body 102, and the source line 103 are formed of P +, N -, and P + materials, respectively.

[0076] Figure 1T is shown based on Figure 1QAn embodiment of an array structure of the cell structure shown. The array structure includes vertical bit lines 101a to 101c and floating bodies 102a to 102e. The array structure further includes source lines 103a to 103e and word lines 104a to 104d. The array structure further includes a dielectric layer 105, which includes a gate oxide or a high-K material, such as HfOx.

[0077] In one embodiment, a three-dimensional (3D) memory array includes a plurality of memory cells separated by a dielectric layer to form a memory cell stack. For example, Figure 1T A 3D array with three memory cell stacks is shown, and a specific "memory cell" is identified. Each memory cell in the memory cell stack includes: a bit line 101, which is formed of either a first semiconductor material or a first conductor material; a floating body semiconductor material 102, which has an inner side surrounding and connected to the bit line; a source line 103, which is formed of either a second semiconductor material or a second conductor material, has an inner side surrounding and connected to the floating body semiconductor material 102; and a word line 104, which is formed of a third conductor material and is coupled to the floating body semiconductor 102 through a dielectric layer 105 to form the gate of the memory cell. Additionally, the bit lines of the memory cell stack are connected to form a vertical bit line (e.g., 101a).

[0078] Figure 1U Another embodiment of the array structure according to the present invention is shown. This embodiment is similar to Figure 1T the embodiment shown, except that the cell is a single-gate transistor. Figure 1U Insulating layers 106a and 106b formed of a material such as an oxide are also shown.

[0079] Figure 1V Shown is Figure 1T an equivalent circuit diagram of the array structure shown. For example, the equivalent circuit shows transistors 301a - 301h formed by Figure 1T the array structure shown. Referring again to Figure 1T the array structure in, the word line structures 104a to 104d are connected to word lines WL0 - WL3. The floating body structures 102a to 102e are floating bodies FB0 - FB4. The source line structures 103a to 103e are connected to source lines SL0 - SL4, and the bit line structure 101a is the vertical bit line (BL). In this embodiment, each floating body (e.g., FB0 - FB4) is coupled to two word lines. This array requires special bias conditions for read and write operations to avoid selecting two cells simultaneously.

[0080] Figure 1W Shown is Figure 1TAnother embodiment of the equivalent circuit diagram of the array structure shown. This embodiment is similar to the one shown, except that the odd-numbered bit lines WL1, WL3, etc. are connected to ground. This turns off the transistors 301c, 301d, 301g, and 301h. In this embodiment, each floating body is only coupled to one bit line. However, compared to the embodiment shown, the storage capacity of this embodiment is reduced by half. Figure 1V shown, which turns off the transistors 301c, 301d, 301g, and 301h. In this embodiment, each floating body is only coupled to one bit line. However, compared to the embodiment shown, the storage capacity of this embodiment is reduced by half. Figure 1V shown, the storage capacity of this embodiment is reduced by half.

[0081] Figure 2A Another embodiment of the cell structure for a 3D NOR flash memory constructed according to the present invention is shown. This embodiment is similar to the one shown, except that the gate dielectric layers 105a and 105b are replaced by charge trapping layers 160a and 160b including an oxide-nitride-oxide (ONO) layer. In one embodiment, the charge trapping layer 160b includes a tunnel oxide layer 161a that is thin enough to allow electron tunneling when a high electric field is applied. This changes the threshold voltage of the cell to represent the stored data. The nitride layer 161b traps electrons for data storage. The blocking oxide 161c is thick enough to prevent electron tunneling to the gates 104a and 104b. In another embodiment, the blocking oxide 161c includes a tunnel oxide layer, and the tunnel oxide layer 161a includes a blocking oxide layer. In this embodiment, during programming, electrons are injected from one of the selected gates 104a or 104b into the nitride layer 161b. Figures 1A to 1B shown, except that the gate dielectric layers 105a and 105b are replaced by charge trapping layers 160a and 160b including an oxide-nitride-oxide (ONO) layer. In one embodiment, the charge trapping layer 160b includes a tunnel oxide layer 161a that is thin enough to allow electron tunneling when a high electric field is applied. This changes the threshold voltage of the cell to represent the stored data. The nitride layer 161b traps electrons for data storage. The blocking oxide 161c is thick enough to prevent electron tunneling to the gates 104a and 104b. In another embodiment, the blocking oxide 161c includes a tunnel oxide layer, and the tunnel oxide layer 161a includes a blocking oxide layer. In this embodiment, during programming, electrons are injected from one of the selected gates 104a or 104b into the nitride layer 161b.

[0082] Figure 2B shows Figure 2B the internal cell structure of the cell shown, where the front gate 104a, the charge trapping layer 160a, and a part of the BL 101 are removed.

[0083] Although Figure 2B the shown ONO layers 161a - 161c are used as examples of the charge trapping layers 160a and 160b, in other embodiments, the charge trapping layers 160a and 160b include any suitable number of oxide layers and nitride layers. For example, in another embodiment, the charge trapping layers 160a and 160b include an oxide-nitride-oxide-nitride-oxide (ONONO) layer. In another embodiment, the charge trapping layers 160a and 160b include only one oxide and one nitride (ON) layer. These variations are within the scope of the embodiment.

[0084] In various embodiments, the charge trapping layers 160a and 160b are also used in Figures 1A to 1L the other cell embodiments shown to replace the gate dielectric layers 105a and 105b, thereby forming different types of NOR flash memory cells.

[0085] Figure 2C Another embodiment of a cell structure for a 3D non-volatile random access memory constructed according to the present invention is shown. This embodiment is similar to Figures 1A to 1B the embodiment shown, except that the gate dielectric layers 105a and 105b are replaced by non-volatile memory gate dielectric layers 170a and 170b. In one embodiment, the non-volatile memory gate dielectric layers 170a and 170b include multiple layers, such as 171a and 171b.

[0086] Figure 2D is shown Figure 2C the internal cell structure of the embodiment shown, in which the front gate 104a, the non-volatile memory gate dielectric layer 170a, and a portion of the BL 101 are removed.

[0087] In one embodiment of forming a ferroelectric random access memory (FRAM), the non-volatile memory gate dielectric layer 170b includes a ferroelectric layer 171a, such as lead zirconate titanate (PZT) or orthorhombic hafnium oxide (HfO2), or hafnium zirconium oxide (HfZrO2). The layer 171b includes a dielectric layer, such as hafnium oxide (HfO2). When a high voltage is applied to the gates 104a and 104b, the resulting electric field changes the polarity of the ferroelectric material in the ferroelectric layer 171a to change the threshold voltage of the cell for representing the stored data.

[0088] In another embodiment of forming a resistive random access memory (RRAM), the non-volatile memory gate dielectric layers 170a and 170b include an adjustable resistance layer 171a, such as hafnium oxide (HfOx), titanium oxide (TiOx), or tantalum oxide (TaOx), and a dielectric layer 171b, such as silicon oxide (SiO). In another embodiment of forming a phase change memory (PCM), the non-volatile memory gate dielectric layers 170a and 170b are formed of multiple layers, the multiple layers including at least one phase change layer 171a, such as a germanium antimony tellurium alloy or a chalcogenide glass Ge2Sb2Te5 (GST), and a heating layer 171b, such as tungsten (W), titanium (Ti), or polysilicon.

[0089] In another embodiment of forming a magnetoresistive random access memory (MRAM), the non-volatile memory gate dielectric layers 170a and 170 include multiple layers and a tunnel barrier layer (such as hafnium oxide (HfO2)) formed between the layers 171a and 171b, the multiple layers including ferromagnetic materials 171a and 171b, such as nickel iron (NiFe) or cobalt iron (CoFe) alloys. The materials of the non-volatile memory gate dielectric layers 170a and 170b described above are merely some examples, and any other suitable materials within the scope of the embodiment can also be used for the non-volatile memory gate dielectric layers 170a and 170b.

[0090] The non-volatile memory gate dielectric layers 170a and 170b shown in this embodiment can also be used together with Figures 1A to 1L all other unit embodiments shown to replace the gate dielectric layers 105a and 105b to form various types of non-volatile random access memory cells.

[0091] Figures 3A to 3C An embodiment of a 3D array structure constructed in accordance with the present invention is shown. Figure 3A Shown is the use of Figures 1C to 1D a 3D array formed using the cell structure shown in. However, in other embodiments, any other cell structure shown in Figures 1A to 2D can be utilized to form a 3D array structure. The 3D array includes a plurality of vertically stacked cell layers. The cells are connected to vertical bit lines, such as vertical bit lines 101a to 101d. The 3D array includes a plurality of word line layers 104a to 104h connected to the gates of the cells. The 3D array also includes a plurality of source line layers 103a to 103h. Each intersection of one of the vertical bit lines 101a to 101d and one of the source lines 103a to 103h forms a cell, such as cell 120.

[0092] Figure 3B Shown is an embodiment of a bit line connected to a 3D array structure constructed in accordance with the present invention Figure 3A shown. The vertical bit lines 101a to 101d are connected to the horizontal bit lines 130a to 130d through select gates (such as select gate 135a) and contacts (such as contact 137a). The horizontal bit lines 130a to 130d are formed of a conductive material such as metal or heavily doped polysilicon. The select gates (such as select gate 135a) are formed of vertical channel transistors. The select gate lines 136a to 136d are connected to the control gates of the vertical channel select gates (such as select gate 135a).

[0093] The word line layers 104a to 104h and the source line layers 103a to 103h are respectively connected to a word line decoder (not shown) and a source line voltage generator (not shown) by forming step structures for the word lines and the source lines at the edges of the array constructed as in a conventional 3D NAND flash memory.

[0094] Figure 3C Another embodiment of a 3D array structure according to the present invention is shown. The array is divided into a plurality of stacks by vertical slits 112a and 112b. Since each stack is connected to a different word line (such as 104 to 104h), the vertical bit lines (such as 101a to 101c) can be connected to the horizontal bit lines 130a to 130d without a vertical select gate (such as 135a) as shown in Figure 3B shown.

[0095] The 3D array structure can be used in various 3D NOR-type memory applications, such as dynamic random access memory (DRAM) using floating body cells (FBC), NOR-type flash memory, ferroelectric random access memory (FRAM), resistive random access memory (RRAM), phase change memory (PCM), and magnetoresistive random access memory (MRAM).

[0096] In addition, the 3D array structure can be applied to in-memory computing and 3D neural network arrays for artificial intelligence (AI) applications. For these applications, the vertical bit lines 101a to 101d, the word line layers 104a to 104h, and the source line layers 103a to 103h are connected to input neuron circuits and output neuron circuits. In addition to these applications, the novel 3D cell and array structures constructed according to the present invention are also applicable to any other applications.

[0097] Figures 4A to 4I An embodiment showing a brief process step of forming a 3D array including Figure 1A the shown cell structure is presented.

[0098] Figure 4A An illustration shows how multiple semiconductor layers 103a to 103g and multiple sacrificial layers 110a to 110f are alternately deposited to form a stack. In one embodiment, the semiconductor layers 103a to 103g include silicon or polysilicon layers. The sacrificial layers 110a to 110f include oxide or nitride layers.

[0099] In one embodiment, the semiconductor layers 103a to 103g are formed from amorphous silicon by using atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), or any other suitable deposition process (such as chemical vapor deposition (CVD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or any other suitable process).

[0100] In one embodiment, after deposition, an annealing process is applied to convert the amorphous silicon into polycrystalline silicon (polysilicon). In one embodiment, the annealing process utilizes low-temperature rapid thermal annealing (e.g., for 4 minutes at 700 degrees Celsius) or any other suitable annealing process.

[0101] The semiconductor layers 103a to 103g are doped during deposition by using an in-situ doping process. For NMOS cells, an N-type dopant, such as phosphine (PH3) or arsine (AsH3), is added during the deposition process. For PMOS cells, a P-type dopant, such as diborane (B2H6), is added during the deposition process.

[0102] In another embodiment, semiconductor layers 103a to 103g are formed by using a polysilicon deposition process (e.g., thermal decomposition of silane (SiH4) at 580 to 650 degrees Celsius). This process forms a polysilicon layer on the surfaces of sacrificial layers 110a to 110f and releases hydrogen (H2).

[0103] In another embodiment, single-crystalline silicon (monocrystalline silicon) is formed on the surfaces of sacrificial layers 110a to 110f by using a silicon epitaxial growth process to form semiconductor layers 103a to 103g. This process may require a longer process time because the silicon layer grows layer by layer.

[0104] Sacrificial layers 110a to 110f are formed by using a deposition process such as atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), or any other suitable deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD)).

[0105] Figure 4B Illustrated is how to define a pattern by using a lithography step to form a plurality of vertical bit line holes (or openings), such as bit line holes 111a to 111c, and then use an anisotropic etching process, such as a deep trench process or a dry etching process, to etch through the plurality of semiconductor layers 103a to 103g and sacrificial layers 110a to 110f to form vertical bit line holes 111a to 111c.

[0106] Figure 4C Illustrated is how to form floating bodies, such as floating bodies 102a to 102c, by using plasma-assisted doping (PLAD) or plasma immersion ion implantation (PIII), gas-phase doping, or any other suitable doping process. For NMOS cells, boron ions are implanted into N-type semiconductor layers 103a to 103g through vertical bit line holes 111a to 111c by using diborane and hydrogen (B2H6 / H2) plasma for reverse doping to form P-floating bodies 102a to 102c. For PMOS cells, phosphorus or arsenic ions are implanted into P-type semiconductor layers 103a to 103g by using phosphine (PH3) or arsine (AsH3) plasma for reverse doping to form N-floating bodies 102a to 102c.

[0107] Figure 4D Illustrated is how to fill the vertical bit line holes (e.g., Figure 4CVertical bit lines, such as vertical bit lines 101a to 101c, are formed by forming vertical bit line holes 111a to 111c as shown. The semiconductor is deposited using any suitable deposition process, such as atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PE-ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or any other suitable process. The semiconductor of the bit lines, such as bit lines 101a to 101c, is doped with the same type of heavy doping as the semiconductor layers 103a to 103g using an in-situ doping process. For NMOS cells, N-type dopants, such as phosphine (PH3) or arsine (AsH3), are added during the deposition of the bit lines. For PMOS cells, P-type dopants, such as diborane (B2H6), are added during the deposition of the bit lines.

[0108] Figures 4E to 4F Shown is the method for forming Figure 1C The process steps of the unit structure shown in FIG. Figure 1C After the process steps shown, perform Figure 4E The process steps shown in FIG. Figure 4A Semiconductor layers 107a to 107c (e.g., polysilicon or silicon) are formed on the sidewalls of the vertical bit line holes 111a to 111c by a described deposition process such as atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PE-ALD), or any other suitable deposition process, or by growing a single crystal silicon layer using an epitaxial growth process. The semiconductor layers 107a to 107c are doped with the same type of heavy doping as the semiconductor layers 103a to 103g by using an in-situ doping process. For NMOS cells, an N-type dopant, such as phosphine (PH3) or arsine (AsH3), is added during the deposition of the semiconductor layer 107. For PMOS cells, a P-type dopant, such as diborane (B2H6), is added during the deposition of the semiconductor layer 107.

[0109] Figure 4F How to fill the vertical bit line holes 111a to 111c with a high melting point metal such as tungsten (W) to form vertical bit lines such as vertical bit lines 101a to 101c is shown. Tungsten is deposited by using any suitable deposition process, such as chemical vapor deposition (CVP) with tungsten hexafluoride (WF6) reacted with hydrogen (H2) and silane (SiH4). Metal bit lines 101a to 101c reduce bit line resistance.

[0110] Before depositing metal in the vertical bit line holes 111a to 111c, an adhesive layer (not shown), such as a titanium and titanium nitride (Ti / TiN) layer, may be formed on the surfaces of the semiconductor layers 107a to 107c. The adhesive layer helps prevent the metal bit lines 101a to 101c from peeling off the semiconductor layers 107a to 107c and improves reliability. The TiN and Ti layers are formed using chemical vapor deposition (CVD) and ion metal plasma (IMP) physical vapor deposition (PVD), respectively. In various embodiments, the adhesive layer (e.g., the adhesive layer applied to the semiconductor layer 107) is optional and may be omitted if desired.

[0111] Figure 4G Illustrated is how to selectively remove the sacrificial layers 110a to 110f by using an isotropic etching process such as wet etching. If the sacrificial layers 110a to 110f are oxide layers (SiO2), etching may be performed using buffered hydrofluoric acid (HF), ammonium acid (NH4F), or a mixture of hydrofluoric acid (HF) and nitric acid (HNO3). If the sacrificial layers 110a to 110f are nitride layers (Si3N4), etching may be performed using concentrated hot phosphoric acid (H3PO4) at a temperature of 150 °C (degrees Celsius) to 180 °C.

[0112] Figure 4H Illustrated is how to form the gate dielectric layers 105a to 105f, such as gate oxide (SiO2) layers or high-K material layers such as hafnium oxide (HfO2), zirconium oxide (ZrO2), or titanium oxide (TiO2), on the surfaces of the sidewalls of the spaces previously occupied by the sacrificial layers 110a to 110f. A silicon dioxide (SiO2) layer is grown on the surfaces of the semiconductor layers 103a to 103g and the vertical bit lines such as 101a to 101c by using thermal oxidation or dry oxidation, or a thin layer of gate dielectric material is deposited on the surfaces of the spaces using atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), or any other suitable deposition process to form the gate dielectric layers 105a to 105f.

[0113] Figure 4IIllustrates how to fill the space previously occupied by the sacrificial layers 110a to 110f with a metal material, such as tungsten (W), tantalum (Ta), titanium (Ti), niobium (Nb) for NMOS cells, ruthenium (Ru) for PMOS cells, or a composition of metal nitrides (such as WN, TaN, TiN), or heavily doped polysilicon to form the metal word lines (or gates) 104a to 104f of the unit transistors. The metal word lines 104a to 104f are formed by using a deposition process such as atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or any other suitable process. As a result, the array includes a floating body cell structure as Figure 1C shown.

[0114] Figures 5A to 5C Illustrates an embodiment of the brief process steps for forming an array using the Figure 1E shown cell structure according to the present invention.

[0115] Figure 5A Illustrates the array structure formed after the Figures 4A to 4C shown process steps. The reader can refer to the Figures 4A to 4C detailed description to form the Figure 5A shown array structure.

[0116] Figure 5B Illustrates how to form the drain regions (such as 107a to 107c) by using plasma doping (PLAD) or gate-phase doping or any other suitable doping process to dope the opposite type of heavily doped dopant into the floating body (such as floating bodies 102a to 102c). This doping process is performed through vertical bit line holes such as bit line holes 111a to 111c. For NMOS cells, phosphine (PH3) or arsine (AsH3) plasma is used to inject phosphorus or arsenic ions into the P-type floating body (such as 102a to 102c) to reverse dope and form the N+ drain regions (such as 107a to 107c). For PMOS cells, diborane and hydrogen (B2H6 / H2) plasma is used to inject boron ions into the N-type floating body (such as 102a to 102c) to reverse dope and form the P+ drain regions (such as 107a to 107c).

[0117] After the process steps described with reference to Figure 5B , the Figures 4F to 4I shown process steps are performed to form the Figure 5C shown array structure. The reader can refer to the Figures 4F to 4I detailed description of these process steps. As a result, an array structure as Figure 1EAn array including a floating body cell structure as shown.

[0118] Figures 6A to 6F An embodiment showing a brief process step of forming an array using the cell structure as shown according to the present invention. Figure 1I An array structure formed after the process steps shown and described is shown. Readers can refer to

[0119] Figure 6A An array structure formed after the process steps shown and described. Readers can refer to Figure 6A A detailed description of the process steps shown and described to form the array structure shown. In this embodiment, the source line (SL) layers 103a to 103g are formed of a high melting point metal such as tungsten (W). Tungsten is deposited by using any suitable deposition process, such as a chemical vapor deposition (CVP) reaction of tungsten hexafluoride (WF6) with hydrogen (H2) and silane (SiH4). Figures 4A to 4B for a detailed description of the process steps to form Figure 6A the array structure shown. In this embodiment, the source line (SL) layers 103a to 103g are formed of a high melting point metal such as tungsten (W). Tungsten is deposited by using any suitable deposition process, such as a chemical vapor deposition (CVP) reaction of tungsten hexafluoride (WF6) with hydrogen (H2) and silane (SiH4).

[0120] Figure 6B An example showing how to perform an isotropic etching process (such as wet etching) through vertical bit line holes (such as 111a to 111c) to selectively etch the sacrificial layers 110a to 110f to form recesses (such as recesses 114a to 114c). The sizes of the recesses 114a to 114c are controlled by the etching rate of the etching solution and the etching time. If the first sacrificial layers 110a to 110f are formed of silicon oxide (SiO2), they can be etched by using buffered hydrofluoric acid with ammonium acid (NH4F) or a mixture of hydrofluoric acid and nitric acid (HNO3).

[0121] Figure 6C An example showing how to fill the recesses (such as recesses 114a to 114c) and the vertical bit line holes (such as vertical bit line holes 111a to 111c) with a semiconductor material 116 (such as polysilicon or silicon). In one embodiment, polysilicon is formed by using a polysilicon deposition process including the silicon epitaxial growth process described with reference to Figure 4A described. Readers can refer to Figure 4A a detailed description of the polysilicon deposition process. The semiconductor material 116 is doped by using an in-situ doping process. For NMOS cells, an N-type dopant such as phosphine (PH3) or arsine (AsH3) is added during the deposition process. For PMOS cells, a P-type dopant such as diborane (B2H6) is added during the deposition process.

[0122] Figure 6DIllustrates how to use the sacrificial layers 110a to 110f as a hard mask to perform an anisotropic etching process (e.g., dry etching) to selectively etch the semiconductor material 116 to reform the vertical bit line holes (e.g., vertical bit line holes 111a to 111c). Since the etching process is self-aligned, high yield can be achieved. After reforming the vertical bit line holes (e.g., vertical bit line holes 111a to 111c), the semiconductor material 116 in the recesses (e.g., recesses 114a to 114c) becomes the floating body of the unit transistor (e.g., floating bodies 102a to 102c).

[0123] Figure 6E Illustrates how to fill the vertical bit line holes (e.g., 111a to 111c) with a high melting point metal (e.g., tungsten (W)) to form vertical metal bit lines (e.g., metal bit lines 101a to 101c). Tungsten is deposited by reacting tungsten hexafluoride (WF6) with hydrogen (H2) and silane (SiH4) through any suitable deposition process (e.g., chemical vapor deposition (CVP)).

[0124] After filling the vertical bit line holes 111 to form the metal bit lines 101, the process steps shown and described in reference Figures 4G to 4I are performed to form Figure 6F the array structure shown. For example, the sacrificial layer 110 is removed, the gate dielectric layer 105 is deposited, and the metal word line 104 is formed. The reader can refer to Figures 4G to 4I for the detailed description of these process steps. In this embodiment, the vertical bit lines such as metal bit lines 101a to 101c and the source line layer 103a to 103g are formed of metal. As a result, an array including Figure 1I the floating body cell structure shown is formed.

[0125] Figures 7A to 7D Illustrates an embodiment of the brief process steps for forming an array including Figure 1I the cell structure shown according to the present invention.

[0126] Figure 7A Illustrates the array structure constructed after performing Figures 4A to 4D the process steps shown. The reader can refer to 4A to Figure 4D for the detailed description of those process steps. In this embodiment, the layers 113a to 113g are formed of a second sacrificial material such as an oxide or a nitride. The second sacrificial layers 113a to 113g and the first sacrificial layers 110a to 110f are configured to have different etching selectivities. For example, in one embodiment, the first sacrificial layers 110a to 110f are formed of an oxide, and the second sacrificial layers 103a to 103g are formed of a nitride.

[0127] Figure 7BIllustrates how to selectively remove the second sacrificial layers 113a to 113g by using an isotropic etching process (e.g., wet etching). If the second sacrificial layers 113a to 113g are formed of silicon oxide (SiO2), they can be etched by using buffered hydrofluoric acid (HF) with ammonium acid (NH4F) or a mixture of hydrofluoric acid (HF) and nitric acid (HNO3).

[0128] Figure 7C Illustrates how to deposit a high melting point metal (e.g., tungsten (W)) to fill the space previously occupied by the second sacrificial layers 113a to 113g to form the metal source line layers 103a to 103g. Tungsten is deposited by reacting tungsten hexafluoride (WF6) with hydrogen (H2) and silane (SiH4) using any suitable deposition process, such as chemical vapor deposition (CVD).

[0129] After the process of depositing the above metal, perform the process steps shown and described in reference Figures 4G to 4I to form the Figure 7D array structure shown. For example, remove the sacrificial layer 110, deposit the gate dielectric layer 105, and form the metal word line 104. The reader can refer to Figures 4G to 4I for a detailed description of these process steps. As a result, an array including the Figure 1I floating body cell structure shown is formed.

[0130] Figures 8A to 8E Illustrates another embodiment of the brief process steps for forming an array including the Figure 1G cell structure shown according to the present invention.

[0131] Figure 8A Illustrates the array structure formed after performing the Figures 4A to 4F process steps shown. The reader can refer to FIGS. 4A to Figure 4F for a detailed description of the process steps for forming this array structure. In this embodiment, the layers 113a to 113g are formed of a second sacrificial material such as an oxide or a nitride. The second sacrificial layers 113a to 113g and the first sacrificial layers 110a to 110f are configured to have different etching selectivities. For example, in one embodiment, the first sacrificial layers 110a to 110f are formed of an oxide and the second sacrificial layers 103a to 103g are formed of a nitride.

[0132] Figure 8B Illustrates how to selectively remove the second sacrificial layers 113a to 113g by using an isotropic etching process (e.g., wet etching). If the second sacrificial layers 113a to 113g are formed of silicon oxide (SiO2), they can be etched by using buffered hydrofluoric acid (HF) with ammonium acid (NH4F) or a mixture of hydrofluoric acid (HF) and nitric acid (HNO3).

[0133] Figure 8C Illustrates how source regions such as 108a to 108c are formed by using plasma doping (PLAD) or vapor doping processes or any other suitable doping process with a heavy dopant of the opposite type to invert the doping type of floating bodies such as 102a to 102c.

[0134] Figure 8D Illustrates how a high melting point metal such as tungsten (W) is deposited to fill the space previously occupied by the second sacrificial layers 113a to 113g to form metal source line layers 103a to 103g. Tungsten is deposited by reacting tungsten hexafluoride (WF6) with hydrogen (H2) and silane (SiH4) using any suitable deposition process, such as a chemical vapor deposition (CVP) reaction.

[0135] After depositing the metal as described above, perform Figures 4G to 4I the process steps shown to form Figure 8E the array structure shown. For example, remove the first sacrificial layer 110, deposit a gate dielectric layer 105, and form metal word lines 104. The reader may refer to Figures 4G to 4I for a detailed description of these process steps. As a result, an array including Figure 1G the floating body cell structure shown is formed.

[0136] Figures 9A to 9C Illustrates an alternative embodiment for forming source regions, such as regions 108a to 108c for an array having Figure 1G the cell structure shown. After performing the process steps shown and described with reference to Figure 8B perform Figure 9A the process steps shown.

[0137] Figure 9A Illustrates how semiconductor layers 108a to 108g, such as polysilicon or silicon, are formed on the surfaces of the sidewalls of the space previously occupied by the second sacrificial layers 113a to 113g. Each semiconductor layer 108 forms a source region, such as source regions 108a(1) to 108a(3), on the sidewalls of a floating body such as floating bodies 102a to 102c.

[0138] In one embodiment, the semiconductor layers 108 are formed by a polysilicon deposition process or a silicon epitaxial growth process as described with reference to Figure 4A The semiconductor layers 108 are doped using an in-situ doping process. For NMOS cells, an N-type dopant, such as phosphine (PH3) or arsine (AsH3), is added during the deposition process. For PMOS cells, a P-type dopant, such as diborane (B2H6), is added during the deposition process.

[0139] Figure 9B Illustrates how a high melting point metal such as tungsten (W) is deposited to fill the space previously occupied by the second sacrificial layers 113a to 113g to form the metal source line layers 103a to 103g. Tungsten is deposited by reacting tungsten hexafluoride (WF6) with hydrogen (H2) and silane (SiH4) using any suitable deposition process, such as chemical vapor deposition (CVP). After depositing the metal, the process steps described with reference to Figures 4G to 4I are illustrated and described to form Figure 9C the array structure shown. For example, the first sacrificial layer 110 is removed, the gate dielectric layer 105 is deposited, and the metal word line 104 is formed. The reader may refer to Figures 4G to 4I the detailed description of these process steps.

[0140] Figures 10A to 10E Illustrates another embodiment of the brief process steps performed to form an array including the Figure 1K cell structure shown.

[0141] Figure 10A Illustrates the array structure constructed after performing the Figures 6A to 6B process steps shown. The reader may refer to FIGS. 6A to Figure 6B for the detailed description of the process steps performed to form this array structure.

[0142] Figure 10B Illustrates how a semiconductor layer 115 (e.g., silicon, polysilicon, silicon germanium (SiGe), indium gallium zinc oxide (IGZO), tungsten-doped indium oxide semiconductor, or any other suitable semiconductor material) is formed on the sidewalls of the recesses 114 (e.g., recesses 114a to 114c) and the surfaces of the vertical bit line holes (e.g., 111a to 111c) by using the epitaxial process or deposition process described with reference to Figure 4A . The reader may refer to Figure 4A for the detailed description of these processes.

[0143] Figure 10C Illustrates that after forming the semiconductor layer 115, an insulating material 116 such as an oxide or nitride is deposited to fill the recesses (e.g., recesses 114a to 114c) and the vertical bit line holes 111a to 111c.

[0144] Figure 10D Illustrates how an anisotropic etching process such as dry etching is performed using the sacrificial layers 110a to 110f and the semiconductor layer 115 as a hard mask to selectively etch the insulating material 116 within the vertical bit line holes (e.g., bit line holes 111a to 111c). Since this etching process is self-aligned, this process achieves a high yield.

[0145] After the above etching process, vertical bit line holes such as bit line holes 111a to 111c are filled with a conductor material such as metal or polysilicon using a deposition process to form vertical bit lines such as bit lines 101a to 101c. Then, the process steps described with reference to Figures 4G to 4I are shown and described to form Figure 10E the array structure shown. For example, the first sacrificial layer 110 is removed, the gate dielectric layer 105 is deposited, and the metal word line 104 is formed. The reader can refer to Figures 4G to 4I the detailed description for these process steps. As a result, an array including a floating body cell structure as Figure 1K shown is formed.

[0146] Figures 11A to 11D FIG. shows an array configured to form an array including a Figure 1M cell structure shown according to the present invention.

[0147] Figure 11A FIG. shows an array structure obtained after performing the Figures 6A to 6B process steps shown. The reader can refer to FIGS. 6A to Figure 6B for the detailed description of the process steps performed to form this array structure.

[0148] Figure 11B FIG. shows how a first semiconductor layer 118 such as silicon or polysilicon is formed on the surface of the sidewalls of the recesses (e.g., recesses 114a to 114c) and on the vertical bit line holes (e.g., bit line holes 111a to 111c) by using a silicon epitaxial process or a polysilicon deposition process as described with reference to Figure 4A . The reader can refer to Figure 4A for the detailed description of these processes.

[0149] After the first semiconductor layer 118 is formed, a second semiconductor material 119 is deposited to fill the recesses (e.g., recesses 114a to 114c) and the vertical bit line holes (e.g., bit line holes 111a to 111c). In one embodiment, the second semiconductor material 119 is different from the first semiconductor layer 118. For example, in one embodiment, the first semiconductor layer 118 is formed of silicon or polysilicon, and the second semiconductor material 119 includes silicon germanium (SiGe), silicon carbide (SiC), or any other suitable semiconductor material.

[0150] Figure 11CIllustrates how to use sacrificial layers 110a to 110f as a hard mask to perform an anisotropic etching process (e.g., dry etching) to selectively etch the semiconductor layer 118 and the second semiconductor material 119 within the vertical bit line holes (e.g., bit line holes 111a to 111c). Since the etching process is self-aligned, it achieves a high process yield. After forming vertical bit line holes such as bit line holes 111a to 111c, the semiconductor layers 118a to 118c become the single floating body of each cell, and the second semiconductor materials 119a to 119c become the second semiconductor regions for charge storage.

[0151] After the etching process described above, perform Figures 4E to 4I the process steps shown to form Figure 11D the array structure shown. For example, remove the first sacrificial layer 110, deposit the gate dielectric layer 105, form the metal word line 104, deposit the semiconductor layer 107 and form the vertical bit line 101. The reader may refer to Figures 4E to 4I the detailed description for these process steps. As a result, an array including Figure 1M the floating body cell structure shown is formed.

[0152] Figures 12A to 12E Illustrates another embodiment of the brief process steps configured to form an array including Figure 1O the cell structure shown according to the present invention.

[0153] Figure 12A Illustrates the array structure obtained after performing Figures 4A to 4C the process steps shown. The reader may refer to FIGS. 4A to Figure 4C for the detailed description of the process steps for forming this array structure.

[0154] Figure 12B Illustrates how to perform an isotropic etching process (e.g., wet etching) through the vertical bit line holes (e.g., bit line holes 111a to 111c) to selectively etch the floating body (e.g., floating bodies 102a to 102c) to form recesses (e.g., recesses 114a to 114c). In another embodiment, the floating body 102 is formed after forming the recesses 114. In this embodiment, after performing Figure 4B the process steps shown, an isotropic etching process (e.g., wet etching) is performed through the vertical bit line holes (e.g., bit line holes 111a to 111c) to selectively etch the semiconductor layers 103a to 103g to form recesses (e.g., recesses 114a to 114c). Next, an isotropic doping process, such as plasma doping or vapor doping, is performed to dope the semiconductor layers 103a to 103g with a dopant of the opposite type to the semiconductor layers 103a to 103g to form a floating body, such as Figure 12BThe floating bodies 102a to 102c shown.

[0155] Figure 12C Illustrated is how to deposit a semiconductor material 109, such as semiconductors 109a to 109c of a material different from the floating body 102, to fill the vertical bit line holes 111 and the recesses 114 by using an appropriate deposition process. For example, in one embodiment, if the floating body 102 is formed of silicon or polysilicon, the semiconductor material 109 is formed of silicon germanium (SiGe) or silicon carbide (SiC).

[0156] Figure 12D Illustrated is how to perform an anisotropic etching process (such as dry etching) using the sacrificial layers 110a to 110f as a hard mask to selectively etch the semiconductor material 109 to reform the vertical bit line holes 111. Since this etching process is self-aligned, it achieves a high process yield. After reforming the vertical bit line holes 111, the residues of the semiconductor material in the recesses become semiconductor regions 109 (e.g., regions 109a to 109c), which form quantum wells to store charges, such as through storage holes, as described in reference Figure 1O as described.

[0157] Figure 12E Illustrated is the array structure obtained after performing the process steps shown in reference Figures 4E to 4I as shown. Readers may refer to Figures 4E to 4I for a detailed description of these process steps. For example, the first sacrificial layer 110 is removed, a gate dielectric layer 105 is deposited, a metal word line 104 is formed, a semiconductor layer 107 is deposited and a vertical bit line 101 is formed. As a result, an array including the Figure 1O floating body cell structure shown in Figure 12E as shown is formed.

[0158] Although the exemplary embodiments of the present invention have been shown and described, it will be apparent to those of ordinary skill in the art that, based on the teachings herein, changes and modifications can be made without departing from the exemplary embodiments and their broader aspects. Accordingly, the appended claims are intended to cover all such changes and modifications that fall within the true spirit and scope of the exemplary embodiments of the present invention.

Claims

1. A memory cell structure is formed by the following process: Alternately depositing a plurality of semiconductor layers and a plurality of sacrificial layers to form a stack; Forming a vertical bit line hole through the stack using a deep trench process; Forming a floating body in the semiconductor layer through the bit line hole using an isotropic doping process; Depositing a conductor material to fill the bit line hole; Removing the sacrificial layer; Depositing a gate dielectric layer between the semiconductor layers; And Depositing a gate material onto the gate dielectric layer.

2. The memory cell structure according to claim 1, wherein, The isotropic doping process includes one of plasma doping (PLAD), vapor doping, collision plasma doping, or plasma immersion ion implantation (PIII).

3. The memory cell structure according to claim 1, wherein, The floating body is formed to have a doping type opposite to that of the semiconductor layer.

4. The memory cell structure according to claim 1, wherein The bit line conductor includes one of a metal material or a polysilicon material.

5. The memory cell structure according to claim 1, further comprising an operation of depositing a semiconductor layer before depositing the conductor to fill the bit line hole.

6. The memory cell structure according to claim 1, further comprising an operation of forming a drain region in the floating body through the bit line hole using an isotropic doping process before depositing the conductor material to fill the bit line hole.

7. A memory cell structure is formed by the following process: Alternately depositing a plurality of conductor layers and a plurality of sacrificial layers to form a stack; Forming a vertical bit line hole through the stack using a deep trench process; Forming a recess in the conductor layer through the bit line hole using an isotropic etching process; Depositing a semiconductor to fill the bit line hole and the recess to form a floating body; Removing the semiconductor within the bit line hole to reform the bit line hole; Depositing a conductor to fill the bit line hole; Removing the sacrificial layer; Depositing a gate dielectric layer between semiconductor layers; And Depositing a gate material onto the gate dielectric layer.

8. The memory cell structure according to claim 7, wherein, The isotropic etching process includes a wet etching process.

9. The memory cell structure according to claim 7, wherein, The bit line conductor is one of metal or polysilicon.

10. The memory cell structure according to claim 7, further comprising an operation of depositing a semiconductor layer in the bit line hole before depositing the conductor to fill the bit line hole.

11. The memory cell structure according to claim 7, further comprising an operation of forming a drain region in the floating body through the bit line hole using an isotropic doping process before depositing the conductor to fill the bit line hole.

12. A memory cell structure includes: A plurality of semiconductor layers and sacrificial layers alternately deposited to form a stack; A vertical bit line hole formed through the stack; A floating body formed in the semiconductor layer through the bit line hole using an isotropic doping process; A conductor material deposited to fill the bit line hole; A gate dielectric layer deposited after removing the sacrificial layer and formed between the semiconductor layers; And A gate material deposited onto the gate dielectric layer.

Images