Miniature field effect chip, multi-ion detection field effect chip and preparation method

Abstract

The invention relates to a micro field effect chip, a multi-ion detection field effect chip and a preparation method, and the micro field effect chip comprises an insulating substrate layer and a sensor assembly which is stacked on the surface of the insulating substrate layer. The sensor assembly comprises a plurality of sensor elements arranged on the surface of the insulating substrate layer in an array; a single sensor element comprises a graphene channel layer and a metal contact layer which are arranged on the surface of the insulating substrate layer, and a top encapsulation layer covering the metal contact layer, and the metal contact layer comprises a source electrode and a drain electrode; the source electrode and the drain electrode are respectively arranged at the edges of two ends on the surface of the graphene channel layer; and the size of an exposed region in the graphene channel layer in the horizontal direction is in a micron level. According to the micro field effect chip provided by the invention, the spatial resolution of the chip is improved, the detection of micro-region ions is realized, and the high precision of the chip is improved.

Description

Technical Field

[0001] The present invention relates to the field of biosensors, and particularly to a micro field effect chip, a field effect chip for multi-ion detection, and a preparation method thereof. Background Art

[0002] An ion-selective field-effect transistor (ISFET) is an electrochemical sensor based on the combination of a semiconductor device and an ion-sensitive membrane (ion-selective thin film). Its working principle is that the ion-sensitive membrane specifically interacts with target ions in the solution to be measured, causing a change in the conductivity of the field-effect transistor channel, thereby realizing the detection of ion concentration. ISFETs have the advantages of high sensitivity, fast response, and easy integration, and are widely used in the fields of environmental monitoring, biomedical detection, food safety analysis, etc.

[0003] Although the ISFET technology has been relatively mature, it still faces the following key problems in practical applications:

[0004] On the one hand, the detection area size of the ion-selective field-effect transistor (ISFET) adopted in the prior art is large. The sensing channel of the traditional ISFET is usually in the centimeter level, resulting in low spatial resolution and difficulty in realizing micro-region detection (such as single-cell analysis, local ion concentration monitoring in a microfluidic chip, etc.), which limits its application in miniaturized scenarios. Graphene, as a two-dimensional carbon material, has the characteristics of high electron mobility, ultra-large specific surface area, excellent chemical stability, and atomic-level thickness, and is easy to be miniaturized, providing a good solution for the miniaturization and performance improvement of ISFETs. However, due to the easy generation of defects and residual photoresist during the miniaturization process of graphene, the detection area of the existing graphene-based ion-selective field-effect transistor (ISFET) is still in the centimeter level, and it has become a difficulty to further reduce the size of graphene.

[0005] On the other hand, the size of the ion-selective thin film (ISM) in the ion-selective field-effect transistor (ISFET) is large. The existing ion-selective thin films (such as PVC films) mostly adopt the drop-coating method or the spin-coating method, which are difficult to be compatible with miniaturized devices and cannot achieve high-precision patterning. Therefore, they often require a large amount of samples, have a single function, and poor process compatibility.

[0006] As the core sensor component of an ion-selective field-effect transistor (ISFET), the performance of a graphene field-effect transistor directly determines the sensitivity, selectivity, and long-term stability of ion sensing. However, the preparation process of traditional graphene field-effect transistors faces three major technical difficulties: (1) Miniaturized graphene is extremely prone to defects and even cracks, which affect the electrical performance of the device and even lead to device failure; (2) Due to reasons such as residual glue cracks, the contact resistance at the metal / graphene interface is high; (3) Metal electrodes are short-circuited in a liquid phase environment, resulting in the inability to form a miniaturized graphene field-effect transistor, thus seriously affecting the development of miniaturized field-effect chips.

[0007] Therefore, providing a miniaturized field-effect chip with high-precision patterning and a high-precision miniaturized ion-selective field-effect chip capable of multi-ion detection has become a technical problem that urgently needs to be solved at present. Summary of the Invention

[0008] To solve the above technical problems, the purpose of the present invention is to provide a miniaturized field-effect chip, a field-effect chip for multi-ion detection, and a preparation method thereof.

[0009] To achieve this purpose, the present invention adopts the following technical solutions:

[0010] In the first aspect, the present invention provides a miniaturized field-effect chip. The miniaturized field-effect chip includes an insulating base layer and a sensor assembly stacked on the surface of the insulating base layer. The sensor assembly includes a plurality of sensor elements arranged in an array on the surface of the insulating base layer; each sensor element includes a graphene channel layer and a metal contact layer provided on the surface of the insulating base layer, and a top encapsulation layer covering the metal contact layer. The metal contact layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively arranged at both ends of the surface of the graphene channel layer; taking the direction parallel to the surface of the insulating base layer as the horizontal direction, the size of the exposed area in the graphene channel layer in the horizontal direction is at the micron level.

[0011] In the present invention, the "top encapsulation layer covering the metal contact layer" means that the top encapsulation layer covers the surface of the metal contact layer away from the graphene channel layer and covers the periphery of the metal contact layer to encapsulate the metal contact layer.

[0012] In the present invention, the "exposed area in the graphene channel layer" means the area on the surface of the graphene channel layer away from the insulating base layer that is not covered by the metal contact layer and the top encapsulation layer.

[0013] The micro field effect chip provided by the present invention has a sensor assembly composed of a number of sensor elements arranged in an array on the surface of an insulating base layer. Among the sensor elements, the graphene channel layer serves as a semiconductor layer, which has the advantages of high electrical conductivity, zero bandgap, good mechanical properties, etc., and is an excellent material for the semiconductor channel of a field effect transistor; the metal layer can transmit and transfer electrical signals; the setting of the top encapsulation layer can prevent the internal structure of the chip from being eroded by external liquids, extend the service life of the chip in a solution environment to the greatest extent and improve the working stability. More importantly, for the chip with a specific structure set by the present invention, the size of the exposed area in the graphene channel layer is set to the micron level, which can improve the spatial resolution of the chip, realize the detection of micro-area ions, and the graphene channel layer at the micron level can accommodate small-sized ion-selective membranes, improving the high-precision of the chip.

[0014] Preferably, the insulating base layer includes a composite substrate layer and a flexible layer provided on the surface of the composite substrate layer.

[0015] In the present invention, a flexible layer is provided on the surface of the composite substrate layer of the insulating base layer to provide a flexible substrate. Compared with the traditional single silicon substrate, it can improve the adhesion between the graphene channel layer and the base layer, effectively avoid the influence of the chip performance caused by the fragmentation and shedding of graphene, and moreover, the flexible layer on the surface of the composite substrate layer can form a double-layer sandwich structure with the top encapsulation protection layer, enhancing the waterproof encapsulation effect of the chip, enabling the chip to have the advantage of still maintaining good performance after being soaked in a solution environment for a long time, and meeting the requirements of long-term stable operation in the in-vivo environment.

[0016] Preferably, the composite substrate layer includes a silicon layer and a silicon oxide layer arranged in sequence from bottom to top, and the silicon oxide layer is arranged close to the flexible layer.

[0017] Preferably, taking the direction perpendicular to the surface of the insulating base layer as the vertical direction, the thickness of the silicon layer in the vertical direction is 300 - 600 μm, such as 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm or 600 μm, etc.

[0018] Preferably, taking the direction perpendicular to the surface of the insulating base layer as the vertical direction, the thickness of the silicon oxide layer in the vertical direction is 10 - 20 μm, such as 10 μm, 12 μm, 14 μm, 16 μm, 18 μm or 20 μm, etc.

[0019] Preferably, in the horizontal direction, the structure of the flexible layer is a symmetric butterfly shape.

[0020] Preferably, the material of the flexible layer includes negative photoresist.

[0021] Preferably, the negative photoresist in the flexible layer includes SU8 negative photoresist.

[0022] Preferably, taking the direction perpendicular to the surface of the insulating base layer as the vertical direction, the thickness of the flexible layer in the vertical direction is 0.1 - 0.5 μm, such as 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm or 0.5 μm, etc.

[0023] Preferably, the sensor assembly is disposed on the surface of the flexible layer in the insulating base layer.

[0024] Preferably, in any one of the sensor elements, the source electrode and the drain electrode are both arranged in parallel with each other, and the exposed area on the surface of the graphene channel layer is disposed between the source electrode and the drain electrode.

[0025] Preferably, in the horizontal direction, the sensor assembly is provided with several layers of the sensor elements in a first direction, and the first direction is perpendicular to the direction in which the source electrode and the drain electrode are parallel to each other.

[0026] In the present invention, "the first direction is perpendicular to the direction in which the source electrode and the drain electrode are parallel to each other" means that the first direction is along the direction parallel to the common perpendicular line between the source electrode and the drain electrode.

[0027] Preferably, in the first direction, two adjacent layers of the sensor elements share a common source electrode, and two sensor elements of two adjacent layers sharing a common source electrode form a sensor unit.

[0028] Preferably, in the horizontal direction, several layers of the sensor units are arranged in the first direction.

[0029] Preferably, in the horizontal direction, each layer of the sensor assembly includes several sensor units arranged in parallel with each other in a second direction, and the sensor units in the same layer are equally spaced from each other in the second direction.

[0030] Preferably, in the horizontal direction, the common source electrodes of the sensor units in the same layer arranged in the second direction are continuous.

[0031] Preferably, the first direction and the second direction are perpendicular to each other, and both the first direction and the second direction are parallel to the surface of the insulating base layer.

[0032] In the present invention, any two of the first direction, the second direction and the stacking direction (i.e., the thickness direction of each layer) of the micro field effect chip are perpendicular to each other.

[0033] In the present invention, in the first direction in the horizontal direction, the sensor units of each layer may be arranged corresponding to each other or staggered, and those skilled in the art can select according to needs.

[0034] Preferably, taking the direction perpendicular to the surface of the insulating base layer as the vertical direction, the thickness of the graphene channel layer in the vertical direction is 0.5 - 5 nm, such as 0.5 nm, 1.0 nm, 2.0 nm, 3.0 nm, 4.0 nm or 5.0 nm, etc.

[0035] Preferably, the width of the exposed area in the graphene channel layer in the horizontal direction along the first direction is 2 - 20 μm, such as 2.0 μm, 5.0 μm, 10.0 μm, 15.0 μm or 20.0 μm, etc.

[0036] Preferably, the length of the exposed area in the graphene channel layer in the horizontal direction along the second direction is 5 - 32 μm, such as 5.0 μm, 10.0 μm, 15.0 μm, 20.0 μm, 25.0 μm, 30.0 μm or 32.0 μm, etc.

[0037] Preferably, the metal contact layer further includes a plurality of metal connection lines arranged in an array for connecting the drain in the sensor element and the bonding pad arranged at the edge of the micro field effect chip.

[0038] In the present invention, the drain in the sensing sensor element is connected to the bonding pad arranged at the edge of the micro field effect chip through the metal connection line, and the bonding pad is arranged to ensure the stable bonding of the chip and the external circuit.

[0039] In the present invention, the size of the bonding pad is not specifically limited, and those skilled in the art can select according to needs. For example, a square with a side length of 150 - 300 μm in the horizontal direction can be selected, such as 150 μm, 200 μm, 250 μm or 300 μm, etc.

[0040] Preferably, the material of the metal contact layer includes chromium and gold.

[0041] Preferably, the thickness of the metal contact layer is 10 - 150 nm, such as 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm or 150 nm, etc.

[0042] Preferably, the metal contact layer includes a chromium layer and a gold layer stacked in sequence from bottom to top.

[0043] The present invention provides a chromium layer at the bottom of the metal contact layer, which can increase the adhesion between the gold layer, the insulating base layer, and the graphene channel layer.

[0044] Preferably, the thickness of the chromium layer in the vertical direction is 1 - 10 nm, such as 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm, etc.

[0045] Preferably, the thickness of the gold layer in the vertical direction is 80 - 140 nm, such as 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, or 140 nm.

[0046] Preferably, the material of the top encapsulation layer includes negative photoresist.

[0047] Preferably, the negative photoresist in the top encapsulation layer includes SU8 negative photoresist.

[0048] Preferably, taking the direction perpendicular to the surface of the insulating base layer as the vertical direction, the thickness of the top encapsulation layer in the vertical direction is 0.3 - 1 μm, such as 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, or 1.0 μm.

[0049] In a second aspect, the present invention provides a method for manufacturing a micro - field - effect chip according to the first aspect, and the manufacturing method includes the following steps:

[0050] Sequentially arrange a plurality of graphene channel layers and a plurality of metal contact layers in an array on the surface of the insulating base layer, and set a top encapsulation layer covering each metal contact layer to form a plurality of sensor elements, and form a sensor assembly on the surface of the insulating base layer to obtain the micro - field - effect chip.

[0051] The metal contact layer includes a source electrode and a drain electrode provided at both end edges on the surface of the graphene channel layer; taking the direction parallel to the surface of the insulating base layer as the horizontal direction, the size of the exposed area in the graphene channel layer in the horizontal direction is at the micron level.

[0052] The method for manufacturing the micro - field - effect chip provided by the present invention sets a graphene channel layer, a metal contact layer, and a top encapsulation layer at corresponding positions on the surface of the insulating base layer to form a sensor assembly composed of a plurality of sensor elements, and obtains a field - effect chip with a highly precise patterned micro - structure. The manufacturing method adopted is simple, which is conducive to the industrial production of the micro - field - effect chip.

[0053] Preferably, the insulating base layer includes a composite substrate layer and a flexible layer disposed on the surface of the composite substrate layer.

[0054] Preferably, the specific preparation process of the insulating base layer includes: spin-coating a negative photoresist on the composite substrate layer, performing pre-soft baking, covering the pre-soft baked negative photoresist with a first photomask, and then performing exposure, post-baking, development, and hard baking to form the flexible layer on the surface of the composite substrate layer, thereby obtaining the insulating base layer.

[0055] Preferably, during the preparation process of the insulating base layer, the negative photoresist used includes SU8 negative photoresist.

[0056] Preferably, the pre-soft baking includes a first pre-soft baking and a second pre-soft baking performed in sequence.

[0057] Preferably, the temperature of the first pre-soft baking is 60 - 70 °C, such as 60 °C, 62 °C, 64 °C, 66 °C, 68 °C, or 70 °C, etc., and the time is 1 - 4 min, such as 1 min, 1.5 min, 2 min, 2.5 min, 3 min, 3.5 min, or 4 min, etc.

[0058] Preferably, the temperature of the second pre-soft baking is 80 - 100 °C, such as 80 °C, 85 °C, 90 °C, 95 °C, or 100 °C, etc., and the time is 1 - 4 min, such as 1 min, 1.5 min, 2 min, 2.5 min, 3 min, 3.5 min, or 4 min, etc.

[0059] Preferably, the first photomask includes a hollowed-out area and a masking area, and the shape of the hollowed-out area of the first photomask in the horizontal direction corresponds to the shape of the flexible layer in the horizontal direction.

[0060] Preferably, the post-baking includes a first post-baking and a second post-baking performed in sequence.

[0061] Preferably, the temperature of the first post-baking is 60 - 70 °C, such as 60 °C, 62 °C, 64 °C, 66 °C, 68 °C, or 70 °C, etc., and the time is 1 - 4 min, such as 1 min, 1.5 min, 2 min, 2.5 min, 3 min, 3.5 min, or 4 min, etc.

[0062] Preferably, the temperature of the second post-baking is 80 - 100 °C, such as 80 °C, 85 °C, 90 °C, 95 °C, or 100 °C, etc., and the time is 1 - 4 min, such as 1 min, 1.5 min, 2 min, 2.5 min, 3 min, 3.5 min, or 4 min, etc.

[0063] Preferably, after the development, fixing is further included.

[0064] Preferably, the reagent used for the development includes propylene glycol monomethyl ether acetate (PGMEA).

[0065] Preferably, the reagent used for the fixing includes isopropyl alcohol.

[0066] Preferably, the temperature of the hard baking is 170 - 190 °C, such as 170 °C, 172 °C, 174 °C, 176 °C, 178 °C, 180 °C, 182 °C, 184 °C, 186 °C, 188 °C or 190 °C, etc., and the time is 10 - 60 min, such as 10 min, 20 min, 30 min, 40 min, 50 min or 60 min, etc.

[0067] Preferably, before forming the flexible layer on the surface of the composite substrate layer, a metal marking layer is also fabricated on the composite substrate layer.

[0068] In the present invention, by providing the metal marking layer, it is used for fixing the mask plates required for each layer structure in the preparation process of the sensor assembly.

[0069] Preferably, the specific preparation process of the graphene channel layer includes: disposing a graphene layer on the surface of the insulating substrate layer, coating a positive photoresist on the graphene layer, covering a second photomask on the surface of the graphene layer coated with the positive photoresist, performing exposure, development and fixing, and then performing post-treatment to remove the graphene layer in the exposed area to obtain the patterned graphene channel layer.

[0070] Preferably, in the preparation process of the graphene channel layer, the coated positive photoresist includes a double-layer photoresist composed of LOR 3A photoresist and S1813 photoresist.

[0071] Preferably, the second photomask includes a hollowed-out area and a mask area, and the shape of the mask area in the second photomask in the horizontal direction corresponds to the shape of the graphene channel layer in the horizontal direction.

[0072] Preferably, in the preparation process of the graphene channel layer, the reagent for the development is ZX-238 developer.

[0073] Preferably, the power of the post-treatment is 100 - 240 W, such as 100 W, 120 W, 140 W, 160 W, 180 W, 200 W, 220 W, or 240 W, etc.

[0074] Preferably, the time of the post-treatment is 0.5 - 3 min, such as 0.5 min, 1 min, 1.5 min, 2 min, 2.5 min or 3 min, etc.

[0075] Preferably, the post-treatment is to etch the graphene layer in the exposed area using an oxygen plasma cleaner.

[0076] Preferably, after the post-treatment, the positive photoresist on the surface of the graphene that has not been removed is stripped.

[0077] Preferably, the reagent used for the stripping includes a solvent stripper.

[0078] Preferably, the specific process for forming the graphene layer on the surface of the insulating base layer includes: using a single-layer graphene film deposited on a copper foil, spin-coating a photoresist layer on the surface of the single-layer graphene film, removing the copper foil under the single-layer graphene film using an etching solution to obtain a composite graphene layer composed of the graphene film and the photoresist layer, washing the composite graphene layer, then transferring the washed composite graphene layer to the surface of the flexible layer in the insulating base layer, softening the photoresist layer by heat treatment, and then immersing the heat-treated component in an organic solvent to remove the photoresist layer, thereby forming a graphene layer on the surface of the insulating base layer.

[0079] Preferably, the photoresist layer is a PMMA (polymethyl methacrylate) layer.

[0080] Preferably, the organic solvent includes acetone.

[0081] Preferably, the temperature of the immersion is 60 - 80 °C, such as 60 °C, 65 °C, 70 °C, 75 °C or 80 °C, etc., and the time is 0.5 - 3 h, such as 0.5 h, 1 h, 1.5 h, 2 h, 2.5 h or 3 h, etc.

[0082] Preferably, before setting the metal contact layer, the surface of the graphene channel layer is also treated using an ultraviolet ozone cleaner to remove the residual positive photoresist on the surface of the graphene channel layer.

[0083] Preferably, the treatment time of the ultraviolet ozone cleaner is 10 - 20 min, such as 10 min, 12 min, 14 min, 16 min, 18 min or 20 min, etc.

[0084] Preferably, the specific preparation process of the metal contact layer includes: coating a positive photoresist on the component provided with the graphene channel layer, covering the coated positive photoresist with a third photomask, then performing exposure, development and fixation, and then depositing a metal by thermal evaporation deposition method, and then using a stripper to strip the metal in the unexposed area.

[0085] Preferably, the third photolithography mask plate includes a hollowed-out area and a mask area, and the shape of the hollowed-out area in the third photolithography mask plate in the horizontal direction corresponds to the shape of the metal contact layer in the horizontal direction.

[0086] Preferably, in the process of preparing the metal contact layer, the positive photoresist coated includes LOR 3A photoresist and S1813 photoresist.

[0087] Preferably, in the process of preparing the metal contact layer, the deposited metals include chromium metal and gold metal.

[0088] Preferably, in the process of preparing the metal contact layer, the developing reagent is ZX-238 developer.

[0089] Preferably, in the process of preparing the metal contact layer, the stripper is Remover PG stripper.

[0090] Preferably, the specific preparation process of the top encapsulation layer includes: spin-coating a negative photoresist on the top surface and the periphery of the component provided with the metal contact layer, performing a pre-soft bake, covering the pre-soft baked negative photoresist on the metal contact layer with a fourth photolithography mask plate, and then performing exposure, post-baking, development, and hard baking to form a top encapsulation layer covering each metal contact layer.

[0091] Preferably, in the process of preparing the top encapsulation layer, the negative photoresist includes SU8 negative photoresist.

[0092] Preferably, in the process of preparing the top encapsulation layer, the pre-soft bake includes a first pre-soft bake and a second pre-soft bake performed in sequence.

[0093] Preferably, in the process of preparing the top encapsulation layer, the temperature of the first pre-soft bake is 60-70 °C, such as 60 °C, 62 °C, 64 °C, 66 °C, 68 °C, or 70 °C, etc., and the time is 1-4 min, such as 1 min, 1.5 min, 2 min, 2.5 min, 3 min, 3.5 min, or 4 min, etc.

[0094] Preferably, in the process of preparing the top encapsulation layer, the temperature of the second pre-soft bake is 80-100 °C, such as 80 °C, 85 °C, 90 °C, 95 °C, or 100 °C, etc., and the time is 1-4 min, such as 1 min, 1.5 min, 2 min, 2.5 min, 3 min, 3.5 min, or 4 min, etc.

[0095] Preferably, the fourth photolithography mask includes a hollowed-out area and a masking area, and the shape of the hollowed-out area in the fourth photolithography mask in the horizontal direction corresponds to the shape of the top encapsulation layer in the horizontal direction.

[0096] Preferably, during the preparation of the top encapsulation layer, the post-baking includes a first post-baking and a second post-baking carried out in sequence.

[0097] Preferably, during the preparation of the top encapsulation layer, the temperature of the first post-baking is 60 - 70 °C, such as 60 °C, 62 °C, 64 °C, 66 °C, 68 °C or 70 °C, etc., and the time is 1 - 4 min, such as 1 min, 1.5 min, 2 min, 2.5 min, 3 min, 3.5 min or 4 min, etc.

[0098] Preferably, during the preparation of the top encapsulation layer, the temperature of the second post-baking is 80 - 100 °C, such as 80 °C, 85 °C, 90 °C, 95 °C or 100 °C, etc., and the time is 1 - 4 min, such as 1 min, 1.5 min, 2 min, 2.5 min, 3 min, 3.5 min or 4 min, etc.

[0099] Preferably, during the preparation of the top encapsulation layer, fixing is further included after development.

[0100] Preferably, the reagent used for development includes propylene glycol monomethyl ether acetate (PGMEA).

[0101] Preferably, the reagent used for fixing includes isopropyl alcohol.

[0102] Preferably, during the preparation of the top encapsulation layer, the temperature of the hard baking is 200 - 230 °C, such as 200 °C, 210 °C, 220 °C or 230 °C, etc., and the time is 20 - 200 min, such as 20 min, 40 min, 60 min, 80 min, 100 min, 120 min, 140 min, 160 min, 180 min or 200 min, etc.

[0103] In a third aspect, the present invention provides an ion-selective field-effect chip, and the ion-selective field-effect chip includes the micro field-effect chip described in the first aspect and several ion-selective thin films; the ion-selective thin films include at least one ion-selective thin film.

[0104] The ion-selective field-effect chip provided by the present invention, with the cooperation of the micro field-effect chip and multiple ion-selective thin films, can realize the detection of multiple target ions synchronously on a single chip, and is applicable to scenarios such as in vivo microenvironment monitoring, single-cell analysis, microfluidic water quality detection, and rapid screening of food ingredients.

[0105] Each of the plurality of ion-selective membranes employed in the present invention can select the same composition for the detection of a target ion, or select different components for the detection of multiple target ions. When multiple types of ion-selective membranes are used, they can be used for the detection of multiple target ions, and the formed chip is an ion-selective field-effect chip for multi-ion detection (i.e., a field-effect chip for multi-ion detection).

[0106] Preferably, the ion-selective membrane covers the top of the micro field-effect chip, at least covering the surface of the exposed area of the graphene channel layer in the micro field-effect chip.

[0107] In the present invention, the ion-selective membrane covers the surfaces of the graphene channel layer, the top encapsulation layer, and the insulating substrate layer in the micro field-effect chip.

[0108] Preferably, the shape of the ion-selective membrane in the horizontal direction is an S-shaped flow channel, continuously covering the sensor units in at least three layers of the ion-selective field-effect chips arranged in the first direction.

[0109] Preferably, the composition of the ion-selective membrane includes polyvinyl chloride, dioctyl sebacate, sodium tetraphenylborate, and an ionophore.

[0110] Preferably, based on the total mass of the ion-selective membrane being 100 wt%, the mass percentage content of the polyvinyl chloride is 30 - 35 wt%, such as 30 wt%, 31 wt%, 32 wt%, 33 wt%, 34 wt%, or 35 wt%, etc.

[0111] Preferably, based on the total mass of the ion-selective membrane being 100 wt%, the mass percentage content of the dioctyl sebacate is 60 - 70 wt%, such as 60 wt%, 62 wt%, 64 wt%, 66 wt%, 68 wt%, or 70 wt%, etc.

[0112] Preferably, based on the total mass of the ion-selective membrane being 100 wt%, the mass percentage content of the sodium tetraphenylborate is 0.5 - 2 wt%, such as 0.5 wt%, 0.6 wt%, 0.8 wt%, 1.0 wt%, 1.2 wt%, 1.4 wt%, 1.6 wt%, 1.8 wt%, or 2.0 wt%, etc.

[0113] Preferably, based on the total mass of the ion-selective membrane being 100 wt%, the mass percentage content of the ionophore is 1 - 10 wt%, such as 1 wt%, 2 wt%, 3 wt%, 4 wt%, 5 wt%, 6 wt%, 7 wt%, 8 wt%, 9 wt%, or 10 wt%, etc.

[0114] In the present invention, the type of the ionophore is selected according to the type of ions to be detected. Exemplarily, when detecting K ions, the ionophore of the ion-selective membrane used is valinomycin; when detecting Na ions, the ionophore of the ion-selective membrane used is sodium ionophore X; when detecting Ca ions, the ionophore of the ion-selective membrane used is calcium ionophore II.

[0115] Preferably, in the horizontal direction, the width of the ion-selective membrane in the first direction is 100 - 500 μm, such as 100 μm, 200 μm, 300 μm, 400 μm or 500 μm, etc.

[0116] Preferably, in the horizontal direction, the length of the ion-selective membrane in the second direction is greater than the sum of the sensor units arranged in the same layer.

[0117] In the present invention, the "horizontal direction" refers to the direction parallel to the surface of the insulating substrate layer; the "first direction" refers to the direction perpendicular to the direction in which the source electrode and the drain electrode are parallel to each other; the second direction refers to the direction perpendicular to the first direction in the horizontal direction.

[0118] Preferably, the ion-selective membrane includes any one or a combination of at least two of a sodium ion-selective membrane, a potassium ion-selective membrane or a calcium ion-selective membrane.

[0119] Preferably, the ion-selective membrane includes at least two ion-selective membranes.

[0120] Fourthly, the present invention provides a preparation method of an ion-selective field effect chip according to the third aspect. The preparation method includes:

[0121] Placing the micro field effect chip on a printed circuit board, precisely placing the PDMS chip containing a first microchannel on the surface of the micro field effect chip away from the printed circuit board, fixing the PDMS chip by using a fixing component, forming a plurality of ion-selective membrane channels between the PDMS chip and the micro field effect chip, injecting an ion-selective membrane precursor solution into the ion-selective membrane channels, and after curing, forming a plurality of ion-selective membranes on the micro field effect chip to obtain the ion-selective field effect chip; the shape and position of the first microchannel in the PDMS chip in the horizontal direction correspond to the shape and position of the ion-selective membrane in the ion-selective field effect chip.

[0122] The preparation method of the ion-selective field-effect chip provided by the present invention adopts the microchannel injection molding method. By assembling the PDMS chip and the micro field-effect chip, a high-precision ion-selective thin film channel is designed. Combining with the injection molding process and using the precise fluid control of the microscale channel, high-resolution patterning deposition of a multi-ion carrier solution can be achieved. At the same time, cross-contamination is avoided through in-situ curing, so as to precisely achieve the regional modification of the multi-ion selective thin film on the micro field-effect chip and realize the preparation of the ion-selective field-effect chip with high-precision patterning.

[0123] Preferably, the ion-selective membrane precursor solution includes polyvinyl chloride, dioctyl sebacate, sodium tetraphenylborate, an ionophore, and a solvent.

[0124] Preferably, in the ion-selective membrane precursor solution, the total volume ratio of polyvinyl chloride, dioctyl sebacate, sodium tetraphenylborate, and the ionophore to the volume of the solvent is 1:(5-15), such as 1:5, 1:6, 1:8, 1:10, 1:12, 1:14, or 1:15, etc.

[0125] Preferably, the solvent is tetrahydrofuran.

[0126] Preferably, in the PDMS chip, the first microchannel of the PDMS chip is arranged at the bottom of the PDMS chip, and the bottom surface of the PDMS chip is attached to the upper surface of the micro field-effect chip to form a plurality of ion-selective thin film channels.

[0127] Preferably, the shape of the first microchannel of the PDMS chip in the horizontal direction is S-shaped.

[0128] Preferably, the PDMS chip further includes a second microchannel and a third microchannel.

[0129] Preferably, the second microchannel and the third microchannel are respectively communicated with both ends of the first microchannel and extend to the top of the PDMS chip and extend outward, for injecting the ion-selective membrane precursor solution into the ion-selective thin film channel.

[0130] As a preferred technical solution of the present invention, the preparation process of the PDMS chip includes: placing a negative photoresist mold in a petri dish, placing the potting adhesive in a desiccator to defoam for 0.5 - 3 h, then pouring the defoamed potting adhesive into the petri dish with the negative photoresist mold placed therein, the height of the potting adhesive being 0.5 - 2 cm, then curing at 30 - 80 °C for 3 - 10 h. After curing, take out the SU8 mold and the petri dish, and cut out a PDMS chip with the same size as the micro field effect chip. Use a punch to punch holes at the starting and ending ends of each flow channel in the PDMS chip to form a second microchannel and a third microchannel for injecting the ion selective membrane precursor solution.

[0131] Preferably, the shape of the negative photoresist mold in the horizontal direction adopted in the preparation process of the PDMS chip corresponds to the shape of the ion selective thin film in the horizontal direction.

[0132] Preferably, the specific preparation process of the negative photoresist mold includes: designing a negative photoresist mask according to the ion selective thin film, spin-coating a negative photoresist on a substrate, soft baking at 60 - 80 °C for 5 - 15 min, soft baking at 90 - 100 °C for 5 - 15 min, performing exposure using the negative photoresist mask to form a negative photoresist pattern, then post-baking at 60 - 80 °C for 5 - 15 min, post-baking at 90 - 100 °C for 5 - 15 min. Then, develop using propylene glycol methyl ether acetate (PGMEA), fix using isopropyl alcohol, and then hard bake at 200 - 250 °C for 15 - 100 min to obtain the negative photoresist mold.

[0133] Preferably, the negative photoresist mold includes an SU8 mold, and the negative photoresist spin-coated on the substrate includes SU8 - 2050 photoresist.

[0134] In the present invention, the potting adhesive adopted is Dow Corning DC184 potting adhesive.

[0135] Preferably, the equipment adopted for the injection includes a syringe.

[0136] Preferably, after the injection is completed, the fixing component and the PDMS chip are removed, and then the curing is carried out.

[0137] Preferably, the temperature of the curing is 20 - 30 °C, such as 20 °C, 22 °C, 24 °C, 26 °C, 28 °C or 30 °C, etc.

[0138] Preferably, the time of the curing is 0.5 - 12 h, such as 0.5 h, 1 h, 4 h, 8 h or 12 h, etc.

[0139] Compared with the prior art, the present invention has at least the following beneficial effects:

[0140] (1) The micro field effect chip provided by the present invention is provided with a sensor assembly composed of a number of sensor elements arranged in an array on the surface of an insulating substrate layer. Among the sensor elements, the graphene channel layer serves as a semiconductor layer, which has the advantages of high electrical conductivity, zero bandgap, good mechanical properties, etc., and is an excellent material for the semiconductor channel of a field effect transistor; the metal layer can transmit and transfer electrical signals; the setting of the top encapsulation layer can prevent the internal structure of the chip from being eroded by external liquids, maximize the service life of the chip in a solution environment, and improve the working stability. More importantly, for the chip with a specific structure set by the present invention, the size of the exposed area in the graphene channel layer is set to the micron level, which can improve the spatial resolution of the chip, realize the detection of micro-area ions, and the graphene channel layer at the micron level can accommodate small-size ion-selective membranes, improving the high-precision of the chip.

[0141] (2) The ion-selective field effect chip provided by the present invention uses a micro field effect chip and multiple ion-selective membranes in cooperation, and can realize the detection of multiple target ions synchronously on a single chip, and is applicable to scenarios such as in vivo microenvironment monitoring, single cell analysis, microfluidic water quality detection, and rapid screening of food ingredients.

[0142] (3) The ion-selective field effect chip provided by the present invention uses a micro field effect chip and multiple ion-selective membranes in cooperation, and can realize the detection of multiple target ions synchronously on a single chip, and is applicable to scenarios such as in vivo microenvironment monitoring, single cell analysis, microfluidic water quality detection, and rapid screening of food ingredients.

[0143] (4) The preparation method of the ion-selective field effect chip provided by the present invention adopts the microchannel injection molding method. By assembling a PDMS chip and the micro field effect chip, a high-precision ion-selective membrane channel is designed, and combined with the injection molding process, through the precise fluid control of the microscale channel, the high-resolution patterning deposition of a multi-ion carrier solution can be realized. At the same time, cross-contamination is avoided through in-situ curing, so as to accurately realize the zone-specific modification of multiple ion-selective membranes on the micro field effect chip, and realize the preparation of a high-precision patterned ion-selective field effect chip. Description of the Drawings

[0144] Figure 1 is a top view structural schematic diagram of the micro field effect chip provided by the present invention.

[0145] Figure 2 is a partially enlarged top view structural schematic diagram of the micro field effect chip provided by the present invention.

[0146] Figure 3 is a top view structural schematic diagram of the flexible layer in the micro field effect chip provided by the present invention.

[0147] Figure 4 It is a front view structural schematic diagram of a sensor element provided on the surface of an insulating base layer.

[0148] Figure 5 It is a top view structural schematic diagram of a sensor unit provided by the present invention.

[0149] Figure 6 It is a top view structural schematic diagram of sensor units arranged in an array along the second direction ( Figure 2 an enlarged view of area A in

[0150] Figure 7 It is a top view structural schematic diagram of an ion-selective field effect chip provided by the present invention.

[0151] Figure 8 It is a partially enlarged top view structural schematic diagram of an ion-selective field effect chip provided by the present invention.

[0152] Figure 9 It is a bottom view structural schematic diagram of the bottom of a PDMS chip provided by the present invention.

[0153] Figure 10 It is a overall structural schematic diagram of a PDMS chip provided by the present invention.

[0154] Figure 11 It is a structural schematic diagram of the assembly of a PDMS chip and a micro field effect chip in the preparation process of an ion-selective field effect chip provided by the present invention.

[0155] Among them, 1, insulating base layer; 101, composite substrate layer; 102, flexible layer; 2, sensor element; 201, graphene channel layer; 201-1, exposed area of graphene channel; 202, metal contact layer; 202-1, source electrode; 202-2, drain electrode; 202-3, metal connection line; 203, top encapsulation layer; 3, bonding pad; 4, ion-selective film; 401, potassium ion-selective film; 402, sodium ion-selective film; 403, calcium ion-selective film; 5, PDMS chip; 501, potassium ion microchannel; 501-1, first potassium ion microchannel; 501-2, second potassium ion microchannel; 501-3, third potassium ion microchannel; 502, sodium ion microchannel; 502-1, first sodium ion microchannel; 502-2, second sodium ion microchannel; 502-3, third sodium ion microchannel; 503, calcium ion microchannel; 503-1, first calcium ion microchannel; 503-2, second calcium ion microchannel; 503-3, third calcium ion microchannel; 6, printed circuit board; 7, pressing sheet; 8, M3 screw block; 9, syringe; X, first direction; Y, second direction; Z, vertical direction. Detailed implementation manners

[0156] The technical solution of the present invention will be further described below in conjunction with the accompanying drawings and through specific embodiments. However, the following examples are merely simple examples of the present invention and do not represent or limit the scope of the claimed protection of the present invention. The scope of protection of the present invention shall be subject to the claims.

[0157] The single-layer graphene film deposited on the copper foil involved in the following examples is from the Beijing Institute of Graphene.

[0158] The SU8 negative photoresist involved in the following examples is SU8 2050 photoresist. The SU8 2050 photoresist, LOR 3A photoresist, and S1813 photoresist are all from Kayaku Advanced Materials Company, USA.

[0159] The ultraviolet lithography system involved in the following examples is the MA / BA6 Gen4 ultraviolet lithography system from SUSS, Germany; the thermal evaporator is the VZZ-400 thermal evaporator from Beijing Micro-Nano Vacuum Technology Co., Ltd.; the oxygen plasma cleaning is from Shenzhen Sanhe Boda Electromechanical Technology Co., Ltd.

[0160] The ZX-238 developer involved in the following examples is from Jiangyin Jianghua Microelectronics Materials Co., Ltd.; the PGMEA developer is from Xi'an Boyan Micro-Nano Information Technology Co., Ltd.; the PMMA is from Dow Corning, USA; the model of the Remover PG stripper is from Kayaku Advanced Materials Company, USA.

[0161] The potassium ionophore involved in the following examples is valinomycin, with the CAS number 2001-95-8, from Shanghai Macklin Biochemical Co., Ltd.; the sodium ionophore X is tetraethyl 4-tert-butylcalix[4]arene tetracarboxylate, with the CAS number 97600-39-0, from Sigma-Aldrich (Shanghai) Trading Co., Ltd.; the model of the calcium ionophore II is ETH129, with the CAS number 74267-27-9, from Sigma-Aldrich (Shanghai) Trading Co., Ltd.

[0162] Example 1

[0163] This example provides a micro field effect chip, and its top view structure schematic diagram is as Figure 1 shown, and the partially enlarged top view structure schematic diagram is as Figure 2 shown. It includes an insulating base layer 1 and a sensor assembly stacked on the surface of the insulating base layer 1.

[0164] Among them, the insulating base layer 1 includes a composite substrate layer 101 and a flexible layer 102 disposed on the surface of the composite substrate layer 101. The composite substrate layer 101 includes a silicon layer and a silicon oxide layer disposed in sequence from bottom to top. The silicon oxide layer is disposed close to the flexible layer 102. Taking the direction perpendicular to the surface of the insulating base layer 1 as the vertical direction Z, the thickness of the silicon layer in the vertical direction Z is 500 μm, and the thickness of the silicon oxide layer in the vertical direction Z is 15 μm; taking the direction parallel to the surface of the insulating base layer 1 as the horizontal direction, the structure of the flexible layer 102 in the horizontal direction is a symmetric butterfly shape, and its top view structure schematic diagram is as Figure 3 , the material of the flexible layer 102 is SU8 negative photoresist, and its thickness in the vertical direction Z is 0.3 μm.

[0165] The sensor assembly includes 100 sensor elements 2 arranged in an array on the surface of the flexible layer 102 in the insulating base layer 1. A single sensor element 2 includes a graphene channel layer 201 and a metal contact layer 202 disposed on the surface of the flexible layer 102, and a top encapsulation layer 203 covering the metal contact layer 202. The specific front view structure schematic diagram is as Figure 4 shown. The metal contact layer 202 includes a source electrode 202-1 and a drain electrode 202-2 disposed in parallel in the horizontal direction. The source electrode 202-1 and the drain electrode 202-2 are respectively disposed at both ends of the surface of the graphene channel layer 201. Taking the direction perpendicular to the parallel source electrode 202-1 and the drain electrode 202-2 as the first direction X, the sensor assembly is provided with 20 layers of sensor elements 2 along the first direction X, as Figure 2 shown. Two adjacent layers of sensor elements 2 along the first direction X share a common source electrode 202-1. Two sensor elements 2 in the upper and lower layers sharing a common source electrode 202-1 form a sensor unit, and its top view structure schematic diagram is as Figure 5 shown. The sensor assembly includes 10 layers of sensor units arranged along the first direction X. In each layer, 5 parallel sensor units are arranged along the second direction Y. The sensor units in the same layer along the first direction X are equally spaced along the second direction Y. The first direction X and the second direction Y are perpendicular to each other in the horizontal direction. In the horizontal direction, the common source electrodes 202-1 in the same layer of the sensor units arranged along the second direction Y are continuous. The specific structure schematic diagram is as Figure 6 shown. In the first direction X in the horizontal direction, the sensor units of each layer are correspondingly arranged.

[0166] The thickness of the graphene channel layer 201 in the vertical direction Z is 1.4 nm. The graphene in the graphene channel layer 201 is single-layer graphene. In each sensor element 2, the size of the area of the graphene channel layer 201 exposed by the source electrode 202-1, the drain electrode 202-2, and the top encapsulation layer 303 in the horizontal direction is at the micron level, as Figure 4and Figure 5 As shown in Figure 5 , the width of the exposed area 201-1 of the graphene channel in the graphene channel layer 201 along the first direction X is 2 μm, and the length along the second direction Y is 5 μm.

[0167] The metal contact layer 202 further includes 110 metal connection lines 202-3 arranged in an array for connecting the drain 202-2 in the sensor element 2 to the bonding pad 3 provided at the edge of the micro field effect chip, as Figure 1 shown in Figure 1 . The bonding pad 3 is square in shape with a side length of 150 μm in the horizontal direction, and is composed of a Cr metal layer with a thickness of 10 nm and an Au metal layer with a thickness of 100 nm stacked from bottom to top, and the Cr metal layer is close to the insulating substrate layer 1. Each component of the metal contact layer 202 includes a Cr metal layer with a thickness of 10 nm and an Au metal layer with a thickness of 100 nm stacked from bottom to top.

[0168] The top encapsulation layer 203 is used for the metal contact layer 202, and its material includes SU8 negative photoresist. In the vertical direction Z, the thickness of the top encapsulation layer 203 is 0.5 μm.

[0169] This embodiment also provides a preparation method for the above-mentioned micro field effect chip, including the following steps:

[0170] S1. Spin-coat LOR 3A photoresist (2000 rpm / 1 min) on the Si / SiO2 composite substrate layer 101, bake at 180 °C for 4 min, then spin-coat S1813 photoresist (4000 rpm / 1 min), bake at 115 °C for 2 min to obtain the photoresist-coated composite substrate layer 101. Cover it with a mask plate and expose the components using an ultraviolet lithography system. Then, after treating with ZX-238 developer for 1 min, fix it in pure water. Deposit a Cr / Au double-layer metal (Cr: 10 nm, Au: 50 nm) using a thermal evaporator, remove the excess metal in the unexposed area using Remover PG stripping solution, clean it with isopropyl alcohol and dry it with nitrogen to form a metal marking layer on the surface of the composite substrate layer 101, providing an alignment reference for subsequent lithography and graphene transfer.

[0171] S2. Spin-coat the SU8 negative photoresist on the composite substrate layer 101 at 400 rpm for 1 minute. Then, perform pre-soft baking at 65°C for 2 minutes first, and then at 95°C for 2 minutes. Use the metal marking layer obtained through step S1 with the first photomask plate to align and cover the composite substrate layer 101 coated with the SU8 negative photoresist. The first photomask plate includes a hollow area and a mask area. The shape of the hollow structure in the first photomask plate in the horizontal direction corresponds to the shape of the flexible layer 102 in the horizontal direction. Use an ultraviolet lithography system for exposure lithography to form a specifically patterned negative photoresist. Then, bake at 65°C for 2 minutes, and then at 95°C for 4 minutes. Then, develop with a PGMEA developer and fix with isopropyl alcohol. Finally, perform hard baking at 180°C for 15 minutes to form the flexible layer 102 on the surface of the composite substrate layer 101, obtaining the insulating substrate layer 1.

[0172] S3. Use a single-layer graphene film deposited on a copper foil. Spin-coat a PMMA layer on the surface of the single-layer graphene film. Use an etching solution formed by mixing ammonium persulfate and hydrochloric acid (the concentration of ammonium persulfate in the etching solution is 0.44 mol / L, and the concentration of hydrochloric acid is 0.12 mol / L) to remove the copper foil provided below the single-layer graphene film, obtaining a composite graphene layer composed of the graphene film and the PMMA layer. Wash the composite graphene layer with deionized water, and transfer the washed composite graphene layer to the surface of the flexible layer 102 in the insulating substrate layer 1. By heat-treating at 160°C for 5 minutes to soften the PMMA layer. Then, immerse the heat-treated component in acetone at 70°C for 1 hour to remove the PMMA layer, forming a graphene layer on the surface of the flexible layer 102.

[0173] Spin-coat the LOR 3A photoresist (2000 rpm / 1 minute) on the graphene layer provided on the surface of the flexible layer 102, bake at 180°C for 4 minutes, and then spin-coat the S1813 photoresist (4000 rpm / 1 minute), bake at 115°C for 2 minutes to form the first double-layer photoresist. Use the second photomask plate to cover the surface of the first double-layer photoresist. The second photomask plate includes a hollow area and a mask area. The shape of the mask area in the second photomask plate in the horizontal direction corresponds to the shape of the graphene channel layer 201 in the horizontal direction. Use an ultraviolet lithography system to perform exposure lithography on the component covered with the second photomask plate. After treating with the ZX-238 developer for 1 minute, fix in pure water, and then etch the graphene layer at 210W for 1 minute through an oxygen plasma cleaner to remove the graphene layer covering the exposed area outside the second photomask plate, and use the Remover PG stripper to strip the photoresist on the surface of the graphene that has not been removed, obtaining a specifically patterned graphene channel layer 201.

[0174] S4. The surface of the graphene channel layer 201 obtained in step S3 is treated with an ultraviolet ozone cleaner for 6 minutes to remove the residual first bilayer photoresist on the surface of the graphene channel layer 201.

[0175] Bonding pads 3 are arranged at the corresponding positions on the edge of the surface of the insulating substrate layer 1 provided with the treated graphene channel layer 201. Then, LOR 3A photoresist (2000 rpm / 1 min) is spin-coated on the top of the obtained component, baked at 180 °C for 4 minutes, and then S1813 photoresist (4000 rpm / 1 min) is spin-coated and baked at 115 °C for 2 minutes to form a second bilayer photoresist. A third photomask is covered on the surface of the second bilayer photoresist. The shape of the hollow structure of the third photomask in the horizontal direction corresponds to the shape of the metal contact layer 202 in the horizontal direction. The component covered with the third photomask is exposed through an ultraviolet lithography system, then developed in a ZX-238 developer for 1 minute and fixed in pure water. The thermal evaporation deposition method is carried out by a thermal evaporator. Chromium metal with a thickness of 10 nm and gold metal with a thickness of 100 nm are sequentially deposited on the top of the component covered with the third photomask. Then, the metal in the unexposed area (the area covered by the mask area of the third photomask) is stripped with Remover PG, and the component is cleaned with isopropanol to obtain the metal contact layer 202.

[0176] S5. SU8 negative photoresist is spin-coated on the surface and around the metal contact layer 202 of the component provided with the metal contact layer 202. The spin-coating time is 1 minute and the spin-coating speed is 400 rpm. Then, it is pre-soft baked at 65 °C for 2 minutes and then pre-soft baked at 95 °C for 2 minutes. The metal marking layer obtained through step S1 is aligned and covered on the spin-coated SU8 negative photoresist by using a fourth photomask. The shape of the hollow structure of the fourth photomask in the horizontal direction corresponds to the shape of the top encapsulation layer 203 in the horizontal direction. The component covered with the fourth photomask is exposed and lithographed through an ultraviolet lithography system to form a specific patterned negative photoresist. Then, it is baked at 65 °C for 2 minutes, baked at 95 °C for 4 minutes, developed with a PGMEA developer, and fixed with isopropanol. Finally, it is hard baked at 230 °C for 30 minutes to form the top encapsulation layer 203 covering each metal contact layer 202, and finally a micro field effect chip is prepared.

[0177] This embodiment also provides an ion-selective field effect chip, and its top view structural schematic diagram is as Figure 7As shown, it includes the above-mentioned micro field effect chip and three ion-selective membranes 4 covering the top of the micro field effect chip. The shape of each ion-selective membrane 4 in the horizontal direction is an S-shaped channel. One ion-selective membrane 4 continuously covers three layers of sensor units arranged in the first direction X in the micro field effect chip, and the ion-selective membrane 4 is not covered on the last layer of sensor units. The specific structural schematic diagram is as Figure 8 The partially enlarged top-view structural schematic diagram of the ion-selective field effect chip shown. The ion-selective membrane 4 covers the surfaces of the graphene channel layer 201, the top encapsulation layer 203, and the flexible layer 102 in the insulating substrate layer 1 in the micro field effect chip. In the first direction X, from top to bottom, the three ion-selective membranes 4 are a potassium ion-selective membrane 401, a sodium ion-selective membrane 402, and a calcium ion-selective membrane 403 in sequence. In the horizontal direction, the width of the ion-selective membrane 4 in the first direction X is 300 μm, the length in the second direction Y is greater than the sum of the sensor units arranged in the same layer, and the thickness of the ion-selective membrane 4 in the vertical direction Z is 50 μm. The composition of the potassium ion-selective membrane 401 is: 32 wt% of PVC (polyvinyl chloride), 64 wt% of DOS (dioctyl sebacate), 1 wt% of NaTPhB (sodium tetraphenylborate), and 3 wt% of valinomycin; the composition of the sodium ion-selective membrane 402 is: 32.1 wt% of PVC, 64.3 wt% of DOS, 0.6 wt% of NaTPhB (sodium tetraphenylborate), and 3 wt% of sodium ionophore X; the composition of the calcium ion-selective membrane 403 is 31 wt% of PVC, 62 wt% of DOS, 1 wt% of NaTPhB (sodium tetraphenylborate), and 6 wt% of calcium ionophore II.

[0178] This embodiment also provides a preparation method for the above ion-selective field effect chip, including the following steps:

[0179] (1) Design a negative photoresist mask according to the size and structure of the ion-selective membrane 4 in the ion-selective field effect chip. Spin-coat SU8 negative photoresist on the substrate, cover the surface of the spin-coated SU8 negative photoresist with a photoresist mask corresponding to the pattern of the ion-selective membrane 4, expose the component covered with the photoresist mask using an ultraviolet lithography system, then soft bake at 65 °C for 10 min, soft bake at 95 °C for 10 min, expose using the negative photoresist mask to form a negative resist pattern, then post-bake at 65 °C for 10 min, post-bake at 95 °C for 10 min. Then, develop using propylene glycol monomethyl ether acetate (PGMEA), fix using isopropyl alcohol, and then hard bake at 220 °C for 30 min to obtain an SU8 negative resist mold.

[0180] (2) Place the SU8 negative mold obtained in step (1) into a petri dish. Place the Dow Corning DC184 potting compound in a desiccator to defoam for 1 h. Then, pour the defoamed potting compound into the petri dish containing the negative mold. The height of the potting compound is 1 cm. Then, cure it at 50 °C for 6 h. After curing, remove the SU8 mold and the petri dish from the cured product, and cut out a PDMS chip 5 with the same size as the micro field-effect chip. Three first microchannels with an S-shaped horizontal shape are formed at the bottom of the PDMS chip 5. The shapes of the three first microchannels at the bottom of the PDMS chip 5 correspond to the shape of the ion-selective membrane 4. The schematic top view structure is as shown in Figure 9 . Use a punch to punch holes at the start and end of each first microchannel in the PDMS chip 5 to form a second microchannel and a third microchannel respectively. The second microchannel and the third microchannel are respectively connected to both ends of the first microchannel and extend to the top of the PDMS chip 5 and extend outwards, respectively for injecting and flowing out the ion-selective membrane precursor solution, thus obtaining the PDMS chip 5.

[0181] The schematic structural diagram of the PDMS chip 5 is as shown in Figure 10 . Among them, the PDMS chip 5 includes a potassium ion microchannel 501, a sodium ion microchannel 502, and a calcium ion microchannel 503. The potassium ion microchannel 501 includes a potassium ion first microchannel 501-1, a potassium ion second microchannel 501-2, and a potassium ion third microchannel 501-3. The sodium ion microchannel 502 includes a sodium ion first microchannel 502-1, a sodium ion second microchannel 502-2, and a sodium ion third microchannel 502-3. The calcium ion microchannel 503 includes a calcium ion first microchannel 503-1, a calcium ion second microchannel 503-2, and a calcium ion third microchannel 503-3.

[0182] (3) According to the formula amounts, dissolve the PVC, DOS, NaTPhB, and ion carriers in the potassium ion-selective membrane 401, sodium ion-selective membrane 402, and calcium ion-selective membrane 403 respectively into tetrahydrofuran with a volume 10 times the total volume of PVC, DOS, NaTPhB, and ion carriers. Rotate overnight to mix evenly and perform ultrasonic treatment at 120 KHz for 30 min to respectively prepare a potassium ion-selective membrane precursor solution, a sodium ion-selective membrane precursor solution, and a calcium ion-selective membrane precursor solution.

[0183] (4) Place the micro field effect chip on the printed circuit board 6. Under the guidance of a microscope, accurately align the PDMS chip 5 obtained in step (2) on the surface of the micro field effect chip away from the printed circuit board 6. The bottom surface of the PDMS chip 5 is attached to the upper surface of the micro field effect chip. Use a pressing piece 7 to fix the PDMS chip 5 above the micro field effect chip and align them. The shape and position of the first microchannel in the horizontal direction in each ion microchannel in the PDMS chip 5 correspond to the shape and position of the ion selective thin film 4 in the ion selective field effect chip. Connect and fix the printed circuit board 6 and the pressing piece 7 through the M3 screw block 8. The schematic diagram of its assembled structure is as shown in Figure 11 . Three ion selective thin film channels are formed between the PDMS chip 5 and the micro field effect chip. Inject the potassium ion selective membrane precursor solution, sodium ion selective membrane precursor solution, and calcium ion selective membrane precursor solution obtained in step (3) into the corresponding ion selective thin film channels using a syringe 9.

[0184] (5) After the injection in step (4) is completed, quickly remove the pressing piece 7 and the PDMS chip 5. Then, cure at 25 °C for 1 h to form three ion selective thin films 4 on the micro field effect chip, obtaining an ion selective field effect chip.

[0185] Performance test:

[0186] Using the separation solution method in the IUPAC guidelines, calculate the Nicholas selectivity coefficient K ij . Use gradient concentration sodium chloride (NaCl, pK is 6 - 2), potassium chloride (KCl, pK is 6 - 2), and calcium chloride (pK is 6 - 2) calibration solutions to flow through the potassium ion microchannel, sodium ion microchannel, and calcium ion microchannel in the ion selective field effect chip provided in Example 1 respectively. Thus, K-ISGFET, Na-ISGFET, and Ca-ISGFET can be obtained to detect the concentrations of K + , Na + , Ca 2+ in the calibration solution. When the test currents are equal, take the ion concentrations of each ion as a i , and the ion concentration of j is a j . According to the K ij calculation formula of the separation solution method, the corresponding ion in each ion microchannel is denoted as i, and the ion in the calibration solution used for detection is denoted as j. The K + , Na + , Ca 2+ of each ion microchannel (i-ISGFET) for K ij is calculated as follows:

[0187]

[0188] Among them, Z i , and Z j are the valence numbers of ions i and j, respectively.

[0189] The Nicholas selectivity coefficients (K ij ) for different ions in each channel can be obtained. The test results are shown in Table 1:

[0190] Table 1

[0191] <![CDATA[K + > <![CDATA[Sodium + > <![CDATA[Ca 2+ > Potassium ion microchannel (K-ISGFET) 1 <![CDATA[1.27×10 -2 > <![CDATA[4.80×10 -4 > Sodium ion microchannel (Na-ISGFET) <![CDATA[1.54×10 -2 > 1 <![CDATA[7.56×10 -4 > Calcium ion microchannel (Ca-ISGFET) <![CDATA[2.94×10 -3 > <![CDATA[2.64×10 -3 > 1

[0192] It can be seen from Table 1 that the potassium ion microchannel, sodium ion microchannel, and calcium ion microchannel have significantly stronger responses to their respective target ions, far greater than the responses to interfering ions. This consistency demonstrates the high selectivity of the ion-selective field-effect chip and verifies the detection reliability of the ion-selective field-effect chip for multi-ion detection.

[0193] In summary, the ion-selective field-effect chip provided by the present invention uses a micro field-effect chip and multiple ion-selective thin films in cooperation, and can realize the detection of multiple target ions synchronously on a single chip, and is applicable to scenarios such as in vivo microenvironment monitoring, single-cell analysis, microfluidic water quality detection, and rapid screening of food ingredients. Moreover, the preparation method of the ion-selective field-effect chip provided by the present invention uses a microchannel injection molding method. By assembling a PDMS chip and the micro field-effect chip, an ion-selective thin film channel with high precision is designed, and combined with the injection molding process, precise fluid control of the microscale channel can be used to achieve high-resolution patterning deposition of a multi-ion carrier solution. At the same time, cross-contamination is avoided through in-situ curing, so as to accurately realize the regional modification of multiple ion-selective thin films on the micro field-effect chip and achieve the preparation of an ion-selective field-effect chip with high-precision patterning.

[0194] The applicant declares that the above description is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention fall within the protection scope and the disclosure scope of the present invention.

Claims

1. A micro field effect chip, characterized in that, The micro field-effect chip includes an insulating base layer and a sensor assembly stacked on the surface of the insulating base layer. The sensor assembly includes a plurality of sensor elements arranged in an array on the surface of the insulating base layer. A single sensor element includes a graphene channel layer and a metal contact layer disposed on the surface of the insulating base layer, and a top encapsulation layer covering the metal contact layer. The metal contact layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively disposed at two end edges on the surface of the graphene channel layer. Taking the direction parallel to the surface of the insulating base layer as the horizontal direction, the size of the exposed area in the graphene channel layer in the horizontal direction is at the micron level.

2. The micro field effect chip according to claim 1, wherein The insulating base layer includes a composite substrate layer and a flexible layer disposed on the surface of the composite substrate layer. Preferably, the composite substrate layer includes a silicon layer and a silicon oxide layer disposed in sequence from bottom to top, and the silicon oxide layer is disposed close to the flexible layer. Preferably, taking the direction perpendicular to the surface of the insulating base layer as the vertical direction, the thickness of the silicon layer in the vertical direction is 300 - 600 μm. Preferably, taking the direction perpendicular to the surface of the insulating base layer as the vertical direction, the thickness of the silicon oxide layer in the vertical direction is 10 - 20 μm. Preferably, in the horizontal direction, the structure of the flexible layer is a symmetric butterfly shape. Preferably, the material of the flexible layer includes a negative photoresist. Preferably, the negative photoresist in the flexible layer includes SU8 negative photoresist. Preferably, taking the direction perpendicular to the surface of the insulating base layer as the vertical direction, the thickness of the flexible layer in the vertical direction is 0.1 - 0.5 μm.

3. The micro field effect chip according to claim 1 or 2, characterized in that, In any one of the sensor elements, the source electrode and the drain electrode are both arranged in parallel with each other, and the exposed area on the surface of the graphene channel layer is disposed between the source electrode and the drain electrode. Preferably, in the horizontal direction, the sensor assembly is provided with a plurality of layers of the sensor elements in a first direction, and the first direction is perpendicular to the direction in which the source electrode and the drain electrode are parallel to each other. Preferably, two adjacent layers of the sensor elements along the first direction share a common source electrode, and two sensor elements of two adjacent layers sharing a common source electrode form a sensor unit. Preferably, in the horizontal direction, each layer of the sensor assembly includes a plurality of the sensor units arranged in parallel with each other in a second direction, and the sensor units in the same layer are equally spaced in the second direction. Preferably, the first direction and the second direction are perpendicular to each other, and both the first direction and the second direction are parallel to the surface of the insulating base layer.

4. The micro field effect chip according to claim 3, characterized in that, Taking the direction perpendicular to the surface of the insulating base layer as the vertical direction, the thickness of the graphene channel layer in the vertical direction is 0.5 - 5 nm. Preferably, the width of the exposed area in the graphene channel layer in the horizontal direction along the first direction is 2 - 20 μm. Preferably, the length of the exposed area in the graphene channel layer in the horizontal direction along the second direction is 5 - 32 μm; Preferably, the metal contact layer further includes a plurality of metal connection lines arranged in an array for connecting the drain electrode to the bonding pads provided at the edge of the micro field effect chip; Preferably, the material of the metal contact layer includes chromium and gold; Preferably, the thickness of the metal contact layer is 10 - 150 nm; Preferably, the material of the top encapsulation layer includes negative photoresist; Preferably, the negative photoresist in the top encapsulation layer includes SU8 negative photoresist; Preferably, taking the direction perpendicular to the surface of the insulating base layer as the vertical direction, the thickness of the top encapsulation layer in the vertical direction is 0.3 - 1 μm.

5. A method for preparing a micro field effect chip according to any one of claims 1-4, characterized in that, The preparation method includes the following steps: Sequentially arranging a plurality of graphene channel layers and a plurality of metal contact layers arranged in an array on the surface of the insulating base layer, and arranging a top encapsulation layer covering each of the metal contact layers to form a plurality of sensor elements, and forming a sensor assembly on the surface of the insulating base layer to obtain the micro field effect chip; The metal contact layer includes a source electrode and a drain electrode provided at both edge portions on the surface of the graphene channel layer; Taking the direction parallel to the surface of the insulating base layer as the horizontal direction, the size of the exposed area in the graphene channel layer in the horizontal direction is at the micron level.

6. The preparation method according to claim 5, characterized in that, The insulating base layer includes a composite substrate layer and a flexible layer provided on the surface of the composite substrate layer; Preferably, the specific preparation process of the insulating base layer includes: spin-coating a negative photoresist on the composite substrate layer, performing pre-soft baking, covering the pre-soft baked negative photoresist with a first photomask, and then performing exposure, post-baking, development, and hard baking to form the flexible layer on the surface of the composite substrate layer to obtain the insulating base layer; Preferably, in the process of preparing the insulating base layer, the negative photoresist used includes SU8 negative photoresist; Preferably, the pre-soft baking includes first pre-soft baking and second pre-soft baking performed in sequence; Preferably, the temperature of the first pre-soft baking is 60 - 70 °C, and the time is 1 - 4 min; Preferably, the temperature of the second pre-soft baking is 80 - 100 °C, and the time is 1 - 4 min; Preferably, the first photomask includes a hollowed-out area and a masking area, and the shape of the hollowed-out area in the first photomask in the horizontal direction corresponds to the shape of the flexible layer in the horizontal direction; Preferably, the post-baking includes first post-baking and second post-baking performed in sequence; Preferably, the temperature of the first post-baking is 60 - 70 °C, and the time is 1 - 4 min; Preferably, the temperature of the second post-baking is 80 - 100 °C, and the time is 1 - 4 min; Preferably, fixing is further included after development; Preferably, the temperature of the hard baking is 170 - 190 °C, and the time is 10 - 60 min; Preferably, the specific preparation process of the graphene channel layer includes: disposing a graphene layer on the surface of the insulating substrate layer, coating a positive photoresist on the graphene layer, covering a second photomask on the surface of the graphene layer coated with the positive photoresist, performing exposure, development, and fixing, and then performing post-treatment to remove the graphene layer in the exposed area to obtain the patterned graphene channel layer; Preferably, the second photomask includes a hollowed-out area and a masking area, and the shape of the masking area in the second photomask in the horizontal direction corresponds to the shape of the graphene channel layer in the horizontal direction; Preferably, the power of the post-treatment is 100-240W; Preferably, the time of the post-treatment is 0.5-3 min; Preferably, after the post-treatment, the positive photoresist on the surface of the remaining graphene is also peeled off; Preferably, before disposing the metal contact layer, the surface of the graphene channel layer is also treated with an ultraviolet ozone cleaner to remove the remaining positive photoresist on the surface of the graphene channel layer; Preferably, the specific preparation process of the metal contact layer includes: coating a positive photoresist on the component provided with the graphene channel layer, covering a third photomask on the coated positive photoresist, performing exposure, development, and fixing, then depositing a metal by thermal evaporation deposition, and then using a stripper to strip the metal in the unexposed area; Preferably, the third photomask includes a hollowed-out area and a masking area, and the shape of the hollowed-out area in the third photomask in the horizontal direction corresponds to the shape of the metal contact layer in the horizontal direction; Preferably, the specific preparation process of the top encapsulation layer includes: spin-coating a negative photoresist on the top surface and the periphery of the component provided with the metal contact layer, performing pre-baking, covering a fourth photomask on the pre-baked negative photoresist on the metal contact layer, and then performing exposure, post-baking, development, and hard baking to form a top encapsulation layer covering each metal contact layer; Preferably, in the process of preparing the top encapsulation layer, the negative photoresist includes SU8 negative photoresist; Preferably, in the process of preparing the top encapsulation layer, the pre-baking includes a first pre-baking and a second pre-baking performed in sequence; Preferably, in the process of preparing the top encapsulation layer, the temperature of the first pre-baking is 60-70°C and the time is 1-4 min; Preferably, in the process of preparing the top encapsulation layer, the temperature of the second pre-baking is 80-100°C and the time is 1-4 min; Preferably, the fourth photomask includes a hollowed-out area and a masking area, and the shape of the hollowed-out area in the fourth photomask in the horizontal direction corresponds to the shape of the top encapsulation layer in the horizontal direction; Preferably, in the process of preparing the top encapsulation layer, the post-baking includes a first post-baking and a second post-baking performed in sequence; Preferably, during the preparation of the top encapsulation layer, the temperature of the first post-baking is 60-70 °C and the time is 1-4 min; Preferably, during the preparation of the top encapsulation layer, the temperature of the second post-baking is 80-100 °C and the time is 1-4 min; Preferably, during the preparation of the top encapsulation layer, fixing is further included after development; Preferably, during the preparation of the top encapsulation layer, the temperature of the hard baking is 200-230 °C and the time is 20-200 min.

7. An ion-selective field effect chip, characterized in that The ion-selective field-effect chip includes the micro field-effect chip according to any one of claims 1-4 and several ion-selective thin films; the ion-selective thin films include at least one ion-selective thin film.

8. The ion-selective field-effect chip according to claim 7, characterized in that, The ion-selective thin film covers the top of the micro field-effect chip, at least covering the surface of the exposed area of the graphene channel layer in the micro field-effect chip; Preferably, the shape of the ion-selective thin film in the horizontal direction is an S-shaped flow channel, continuously covering the sensor units in at least one layer of the ion-selective field-effect chips arranged in the first direction; Preferably, the ion-selective thin film includes polyvinyl chloride, dioctyl sebacate, sodium tetraphenylborate and an ionophore; Preferably, in the horizontal direction, the width of the ion-selective thin film in the first direction is 100-500 μm; Preferably, in the horizontal direction, the length of the ion-selective thin film in the second direction is greater than the sum of the sensor units arranged in the same layer; Preferably, the ion-selective thin film includes any one or a combination of at least two of a sodium ion-selective thin film, a potassium ion-selective thin film or a calcium ion-selective thin film.

9. A method for preparing an ion-selective field effect chip according to claim 7 or 8, characterized in that, The preparation method includes: Placing the micro field-effect chip on a printed circuit board, precisely placing the PDMS chip containing a first microchannel on the surface of the micro field-effect chip away from the printed circuit board, fixing the PDMS chip with a fixing component, forming several ion-selective thin film channels between the PDMS chip and the micro field-effect chip, injecting an ion-selective membrane precursor solution into the ion-selective thin film channels, and after curing, forming several ion-selective thin films on the micro field-effect chip to obtain the ion-selective field-effect chip; the shape and position of the first microchannel in the PDMS chip in the horizontal direction correspond to the shape and position of the ion-selective thin film in the ion-selective field-effect chip.

10. The preparation method according to claim 9, characterized in that, The ion-selective membrane precursor solution includes polyvinyl chloride, dioctyl sebacate, sodium tetraphenylborate, an ionophore and a solvent; Preferably, in the PDMS chip, the first microchannel of the PDMS chip is arranged at the bottom of the PDMS chip, and the bottom surface of the PDMS chip is attached to the upper surface of the micro field-effect chip to form several ion-selective thin film channels; Preferably, the shape of the first microchannel in the PDMS chip in the horizontal direction is S-shaped; Preferably, the PDMS chip further includes a second microchannel and a third microchannel; Preferably, the second microchannel and the third microchannel are respectively communicated with two ends of the first microchannel, extend to the top of the PDMS chip and extend outwards, and are used for injecting the ion-selective membrane precursor solution into the ion-selective thin film channel; Preferably, after the injection is completed, the fixing component and the PDMS chip are also removed; Preferably, the curing temperature is 20-30 °C; Preferably, the curing time is 0.5-3 h.

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