Equipment in-situ detection circuit and method

Abstract

The invention discloses an equipment in-place detection circuit and method, which are used for detecting the connection state of output stage circuits of lower-level equipment and upper-level equipment, and relates to the technical field of equipment in-place detection, and the equipment in-place detection circuit comprises a main circuit and a controller, the main circuit comprises a trigger circuit, a voltage circuit and a detection circuit; the trigger circuit is used for outputting multiple paths of trigger level signals according to an enable signal and a clock signal; the voltage circuit is used for outputting a reference voltage signal according to an enable signal and a current source; the detection circuit is connected with the trigger circuit and the differential output end of the output stage circuit, and the detection circuit is used for outputting an equipment in-place state level signal according to the two paths of trigger level signals, the differential voltage signal and the reference voltage signal; and the controller is connected with the detection circuit and is used for judging whether the equipment is in place or not according to the equipment in-place state level signal. According to the whole circuit, equipment in-place detection is completed through digital logic, the circuit structure is simple, and static power consumption is low.

Description

Technical Field

[0001] The present invention relates to the technical field of device presence detection, and in particular to a device presence detection circuit and method. Background Art

[0002] In the process of data transmission, the device presence detection circuit plays a vital role. It is mainly used to detect whether the lower-level device is correctly connected and ready to receive data. This detection mechanism is crucial to ensure the reliability and integrity of data transmission, especially in applications with hot-swap requirements such as PCIe bus, USB interface, and HDMI interface. For example, when it is detected that the device load on a certain interface is low, the resource allocation of other interfaces can be dynamically adjusted to optimize the overall performance, operate more efficiently, and reduce resource waste and unnecessary energy consumption. Under this premise, detecting whether the lower-level device is in place becomes a necessary indicator. If the lower-level device does not exist, the relevant circuits of the current-level device can be turned off to reduce unnecessary overhead. If the lower-level device is detected, the relevant circuits of the current-level device will start to work normally.

[0003] The existing device presence detection circuit uses a charge pump to inject current into the output stage circuit of the device at this stage to adjust the common-mode voltage, and compares the common-mode voltage with multiple reference voltages. The comparison result is used to control the current in the charge pump injection circuit and to determine whether the lower-level device is in place by detecting the adjustment rate of the common-mode voltage. However, the circuit current overhead of this solution is large and the static power consumption is high. In addition, since the charge pump directly injects current into the output stage circuit, it will have a greater adverse effect on the main signal path. Summary of the invention

[0004] The embodiments of the present invention provide a device presence detection circuit and method to solve the technical problems of large current overhead and high static power consumption in the existing device presence detection circuit in the related art.

[0005] In a first aspect, a device presence detection circuit is provided, which is used to detect the connection status of an output stage circuit of a lower-level device and an upper-level device, and includes: a main circuit and a controller;

[0006] The main circuit comprises:

[0007] A trigger circuit, used for outputting multiple trigger level signals according to an enable signal and a clock signal;

[0008] A voltage circuit, used for outputting a reference voltage signal according to an enable signal and a current source;

[0009] A detection circuit connected to the differential output terminal of the trigger circuit and the output stage circuit, and used for outputting a device in-position state level signal according to two-way trigger level signals, a differential voltage signal and a reference voltage signal;

[0010] The controller is connected to the detection circuit and is configured to determine whether the device is present based on the device presence status level signal.

[0011] In some embodiments, the controller is configured to determine whether the device is present based on the device presence status level signal, including:

[0012] When the device presence status level signal is at a low level, it is determined that the device is not present;

[0013] When the device presence status level signal is at a high level, it is determined that the device is present.

[0014] In some embodiments, the device presence detection circuit further includes:

[0015] When the device presence status level signal is at a high level, the trigger circuit changes the level state of the multi-channel trigger level signal.

[0016] In some embodiments, the trigger circuit includes a first delay unit, a second delay unit, a first monostable unit, a second monostable unit, and a combinational logic unit;

[0017] The input end of the first delay unit receives a clock signal, the output end of the first delay unit is connected to the input end of the first monostable unit, and the output end of the first monostable unit is connected to the first input end of the combinational logic unit;

[0018] The input end of the second monostable unit receives a clock signal, and the output end of the second monostable unit is connected to the second input end of the combinational logic unit;

[0019] The third input end of the combinational logic unit receives the device presence status level signal, the fourth input end of the combinational logic unit receives an enable signal, the first output end of the combinational logic unit outputs a first-channel trigger level signal, and the second output end of the combinational logic unit outputs a second-channel trigger level signal;

[0020] The input end of the second delay unit is connected to the second output end of the combinational logic unit, and the output end of the second delay unit outputs a third-channel trigger level signal.

[0021] In some embodiments, the combinational logic unit includes a first inverter, a first AND gate, a second AND gate, and a third AND gate;

[0022] The input end of the first inverter receives the device presence status level signal, and the output end of the first inverter is connected to the first input end of the first AND gate;

[0023] The second input terminal of the first AND gate receives an enable signal, and the output terminal of the first AND gate is connected to the first input terminal of the second AND gate and the first input terminal of the third AND gate;

[0024] The second input terminal of the second AND gate is connected to the output terminal of the second monostable unit, the second input terminal of the third AND gate is connected to the output terminal of the first monostable unit, the output terminal of the second AND gate outputs a first trigger level signal, and the output terminal of the third AND gate outputs a second trigger level signal respectively.

[0025] In some embodiments, the voltage circuit includes a second inverter, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a first resistor;

[0026] The input terminal of the second inverter receives an enable signal, and the output terminal of the second inverter is connected to the second terminal of the first MOS transistor;

[0027] The second terminals of the second MOS transistor and the third MOS transistor are connected, and the third terminals of the first MOS transistor, the second MOS transistor, and the third MOS transistor are grounded;

[0028] The first terminal of the first resistor is connected to a power supply, the second terminal of the first resistor is connected to the first terminal of the third MOS transistor and the second terminal of the fourth MOS transistor to output a reference voltage signal, and the first terminal and the third terminal of the fourth MOS transistor are grounded.

[0029] In some embodiments, the detection circuit includes a comparison unit and a detection unit. The comparison unit is connected to the trigger circuit, the voltage circuit, and the differential input terminals of the load, and the detection unit is connected to the trigger circuit and the comparison unit;

[0030] The detection circuit is configured to output a device presence status level signal according to two trigger level signals, a differential voltage signal, and a reference voltage signal, including:

[0031] The comparison unit is configured to output two comparison level signals according to one trigger level signal, a differential voltage signal, and a reference voltage signal;

[0032] The detection unit is configured to output a device presence status level signal according to an enable signal, one trigger level signal, and two comparison level signals.

[0033] In some embodiments, the comparison unit includes a first dynamic comparator, a second dynamic comparator, a fifth MOS transistor, and a sixth MOS transistor;

[0034] The non-inverting input terminal of the first dynamic comparator and the inverting input terminal of the second dynamic comparator are respectively connected to the differential output terminals of the output stage circuit. The inverting input terminal of the first dynamic comparator and the non-inverting input terminal of the second dynamic comparator receive a reference voltage signal. The enable terminals of the first dynamic comparator and the second dynamic comparator receive a trigger level signal;

[0035] The first ends of the fifth MOS transistor and the sixth MOS transistor are connected to a power supply. The second ends of the fifth MOS transistor and the sixth MOS transistor are connected to the enable terminals of the first dynamic comparator and the second dynamic comparator. The third end of the fifth MOS transistor is connected to the output terminal of the first dynamic comparator to output a first comparison level signal, and the third end of the sixth MOS transistor is connected to the output terminal of the second dynamic comparator to output a second comparison level signal.

[0036] In some embodiments, the detection unit includes a NOR gate, a flip-flop, and a second resistor. The two input terminals of the NOR gate are respectively connected to the output terminal of the first dynamic comparator and the output terminal of the second dynamic comparator. The output terminal of the NOR gate is connected to the input terminal of the flip-flop. The trigger terminal of the flip-flop receives a trigger level signal. The output terminal of the flip-flop is connected to the first end of the second resistor to output a device presence status level signal, and the second end of the second resistor is grounded.

[0037] In a second aspect, a method for detecting the presence of a load is provided. The method includes the following steps:

[0038] Output a plurality of trigger level signals according to an enable signal and a clock signal;

[0039] Output a reference voltage signal according to an enable signal and a current source;

[0040] Output a device presence status level signal according to two trigger level signals, a differential voltage signal, and a reference voltage signal;

[0041] Determine whether the device is present according to the device presence status level signal.

[0042] The beneficial effects brought by the technical solution provided by the present invention include:

[0043] An embodiment of the present invention provides a circuit and method for detecting the presence of a device. The device presence detection circuit is provided with a main circuit and a controller. The main circuit includes a trigger circuit, a voltage circuit, and a detection circuit. Among them, the trigger circuit outputs a trigger level signal under the control of an enable signal and a clock signal. The voltage circuit is controlled by the enable signal, and the detection circuit is controlled by the enable signal and the trigger level signal. In the device presence detection circuit of the embodiment of the present invention, the entire circuit completes the device presence detection by digital logic, without using circuits with large power consumption, area, etc. The structure is simple and the static power consumption is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0045] Figure 1 A schematic block diagram of a device presence detection circuit provided by an embodiment of the present invention;

[0046] Figure 2 A schematic diagram of the connection between a device presence detection circuit provided by an embodiment of the present invention and the output stage circuit of the upper-level device and the lower-level device;

[0047] Figure 3 A schematic block diagram of the trigger circuit provided by an embodiment of the present invention;

[0048] Figure 4 A circuit diagram of the combinational logic unit provided by an embodiment of the present invention;

[0049] Figure 5 A circuit diagram of the voltage circuit provided by an embodiment of the present invention;

[0050] Figure 6 A circuit diagram of the comparison unit provided by an embodiment of the present invention;

[0051] Figure 7 A circuit diagram of the detection unit provided by an embodiment of the present invention;

[0052] Figure 8 A schematic diagram of the signal waveforms of different nodes of a device presence detection circuit provided by an embodiment of the present invention under different working conditions. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0053] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are only a part rather than all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0054] The embodiment of the present invention provides a circuit for detecting the presence of a device, which can solve the technical problems of large current overhead and high static power consumption in the existing circuit for detecting the presence of a device.

[0055] See Figure 1 and Figure 2 As shown in

[0056] The main circuit includes a trigger circuit, a voltage circuit, and a detection circuit. The trigger circuit is configured to output multiple trigger level signals according to an enable signal and a clock signal. One of the trigger level signals is used to control the tail current source switch of the output stage circuit. Among them, the clock signal can be generated by a clock circuit, and the enable signal can be provided by a controller. The trigger circuit outputs a first trigger level signal idc_vc, a second trigger level signal cmp_vc, and a third trigger level signal dff_vc. When the normal detection starts, the first trigger level signal idc_vc is used to control the tail current source switch of the output stage circuit to be disconnected.

[0057] The voltage circuit is configured to output a reference voltage signal Vref according to the enable signal and a current source. The current source can be provided by the output stage circuit of the upper-level device, such as Figure 1 the tail current source IDC of the output stage circuit in

[0058] The detection circuit is connected to the trigger circuit and the differential output terminal of the output stage circuit. The detection circuit is configured to output a device presence status level signal according to two trigger level signals, a differential voltage signal, and the reference voltage signal. That is, the detection circuit outputs a device presence status level signal rxdet_st according to the second trigger level signal cmp_vc, the third trigger level signal dff_vc, the differential voltage signal VOP / N, and the reference voltage signal Vref.

[0059] The controller is connected to the detection circuit, and the controller is configured to determine whether the device is present according to the device presence status level signal.

[0060] Specifically, when the normal detection starts, the controller determines whether the device is present according to the device presence status level signal, including:

[0061] When the device presence status level signal is a low-level signal, it is determined that the device is not present;

[0062] When the device presence status level signal is a high-level signal, it is determined that the device is present.

[0063] The device presence detection circuit in the embodiment of the present invention is provided with a main circuit and a controller. The main circuit includes a trigger circuit, a voltage circuit, and a detection circuit. Among them, the trigger circuit is controlled by an enable signal and a clock signal to output a trigger level signal. The voltage circuit is controlled by the enable signal, and the detection circuit is controlled by the enable signal and the trigger level signal. That is, the device presence detection circuit is overall completed by digital logic, and circuits with large overheads such as power consumption and area are not used. The circuit structure is simple, and the static power consumption is low.

[0064] As an alternative embodiment, in an embodiment of the invention, refer to Figure 2 As shown, the device presence detection circuit in the embodiment of the present invention further includes: when the device presence status level signal rxdet_st is a high-level signal, the trigger circuit changes the level status of the multi-channel trigger level signals. That is, after detecting that the device is normally connected, the trigger circuit flips the level status of the first trigger level signal idc_vc, the second trigger level signal cmp_vc, and the third trigger level signal dff_vc, closes the current source in the output stage circuit, and at the same time the voltage circuit and the detection circuit stop working, automatically turning off the detection function of the main circuit, ending the detection, reducing the circuit power consumption, and having no impact on the main signal channel.

[0065] As an alternative embodiment, in an embodiment of the invention, refer to Figure 3 As shown, the trigger circuit includes a first delay unit, a second delay unit, a first monostable unit, a second monostable unit, and a combinational logic unit.

[0066] The input end of the first delay unit receives the clock signal, the output end of the first delay unit is connected to the input end of the first monostable unit, and the output end of the first monostable unit is connected to the first input end of the combinational logic unit.

[0067] The input end of the second monostable unit receives the clock signal, and the output end of the second monostable unit is connected to the second input end of the combinational logic unit.

[0068] The third input end of the combinational logic unit receives the device presence status level signal, the fourth input end of the combinational logic unit receives the enable signal, the first output end of the combinational logic unit outputs the first trigger level signal, and the second output end of the combinational logic unit outputs the second trigger level signal.

[0069] The input end of the second delay unit is connected to the second output end of the combinational logic unit, and the output end of the second delay unit outputs a third trigger level signal.

[0070] Within one clock cycle, the clock signal CLK passes through the first delay unit and the first monostable unit to generate a one-shot A signal, and the clock signal CLK passes through the second monostable unit to generate a one-shot B signal. That is, in terms of timing, the one-shot A signal lags behind the one-shot B signal. The one-shot A signal, the one-shot B signal, the device presence status level signal rxdet_st, and the enable signal are used as the four-terminal inputs of the combinational logic circuit, and output a first trigger level signal idc_vc and a second trigger level signal cmp_vc. The second trigger level signal cmp_vc passes through the second delay unit and then outputs a third trigger level signal dff_vc.

[0071] Further, referring to Figure 4 As shown, the combinational logic unit includes a second inverter INV2, a first AND gate AND1, a second AND gate AND2, and a third AND gate AND3. The input end of the second inverter INV2 receives the device presence status level signal. The output end of the second inverter INV2 is connected to the first input end of the first AND gate AND1. The second input end of the first AND gate AND1 receives the enable signal. The output end of the first AND gate AND1 is connected to the first input end of the second AND gate AND2 and the first input end of the third AND gate AND3. The second input end of the second AND gate AND2 is connected to the output end of the second monostable unit. The second input end of the third AND gate AND2 is connected to the output end of the first monostable unit. The output end of the second AND gate AND2 outputs a first trigger level signal, and the output end of the third AND gate AND3 outputs a second trigger level signal respectively.

[0072] The two inputs of the first AND gate AND1 are respectively the inverted signal of the device presence status level signal rxdet_st and the enable signal rxdet_en, and its output is the signal flag signal. The two input ends of the second AND gate AND2 are respectively connected to the flag signal and the One Shot B signal output by the second monostable unit, and output a first trigger level signal idc_vc. Similarly, the two input ends of the third AND gate AND3 are respectively connected to the flag signal and the One Shot A signal output by the first monostable unit, and output a second trigger level signal cmp_vc.

[0073] As an optional implementation manner, in an embodiment of the invention, referring to Figure 5As shown, the voltage circuit includes a first inverter INV1, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, and a first resistor R1. Among them, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 can be NMOS transistors.

[0074] The input end of the first inverter INV1 receives an enable signal. The output end of the first inverter INV1 is connected to the second end of the first MOS transistor M1. The second end of the second MOS transistor M2 is connected to the second end of the third MOS transistor M3. The third ends of the first MOS transistor M1, the second MOS transistor M2, and the third MOS transistor M3 are grounded. The first end of the first resistor R1 is connected to a power supply. The second end of the first resistor R1 is connected to the first end of the third MOS transistor M3 and the second end of the fourth MOS transistor M4 to output a reference voltage signal. The first end and the third end of the fourth MOS transistor M4 are grounded.

[0075] Among them, the current source IDC is the same as the tail current source of the output stage circuit. When the enable signal rxdet_en is at a high level, the second MOS transistor M2 and the third MOS transistor M3 form a basic current mirror. The current in the branch where the third MOS transistor M3 is located has a fixed proportional relationship with the current source IDC. Then the value of the reference voltage signal Vref is VDD - I d_M3 *R1, that is, VDD - β*I DC *R1, where β is the aspect ratio of the width to length of the third MOS transistor M3 and the second MOS transistor M2, that is, β ≈ (W M3 / L M3 ) / (W M2 / L M2 )). By selecting an appropriate R1, Vref can meet the comparison requirements with the differential voltage signal. In addition, the fourth MOS transistor M4 acts as a MOS capacitor to filter out the glitches in the reference voltage signal Vref. When the enable signal rxdet_en is at a low level, the first MOS transistor M1 conducts, pulling the gate voltages of the second MOS transistor M2 and the third MOS transistor M3 to a low level, and the current mirror fails, and Vref rises to VDD.

[0076] As an alternative implementation, in an invention embodiment, as shown in Figure 2 The detection circuit includes a comparison unit and a detection unit. The comparison unit is connected to the trigger circuit, the voltage circuit, and the differential input ends of the load. The detection unit is connected to the trigger circuit and the comparison unit.

[0077] The detection circuit is used to output a device presence status level signal according to two trigger level signals, a differential voltage signal, and a reference voltage signal, including:

[0078] The comparison unit is configured to output two comparison level signals according to a trigger level signal, a differential voltage signal, and a reference voltage signal;

[0079] The detection unit is configured to output a device presence status level signal according to an enable signal, a trigger level signal, and two comparison level signals.

[0080] Specifically, referring to Figure 6 As shown, the comparison unit includes a first dynamic comparator, a second dynamic comparator, a fifth MOS transistor M5, and a sixth MOS transistor M6. Among them, the fifth MOS transistor M5 and the sixth MOS transistor M6 can be PMOS transistors.

[0081] The non-inverting input terminal of the first dynamic comparator and the inverting input terminal of the second dynamic comparator are respectively connected to the differential input terminals of the load. The inverting input terminal of the first dynamic comparator and the non-inverting input terminal of the second dynamic comparator receive the reference voltage signal. The enable terminals of the first dynamic comparator and the second dynamic comparator receive a trigger level signal.

[0082] The first terminal of the fifth MOS transistor M5 and the first terminal of the sixth MOS transistor M6 are connected to the power supply. The second terminal of the fifth MOS transistor M5 and the second terminal of the sixth MOS transistor M6 are connected to the enable terminals of the first dynamic comparator and the second dynamic comparator. The third terminal of the fifth MOS transistor M5 is connected to the output terminal of the first dynamic comparator to output a first comparison level signal. The third terminal of the sixth MOS transistor M6 is connected to the output terminal of the second dynamic comparator to output a second comparison level signal.

[0083] The first dynamic comparator and the second dynamic comparator share the same reference voltage signal Vref and the same trigger level signal cmp_vc. When the trigger level signal cmp_vc is at a high level, the first dynamic comparator and the second dynamic comparator respectively compare VOP and VON with the reference voltage signal Vref. When cmp_vc is at a low level, the first dynamic comparator and the second dynamic comparator do not work, and the fifth MOS transistor M5 and the sixth MOS transistor M6 pull the output comparison level signals cmp_res_p and cmp_res_n to a high level.

[0084] Referring to Figure 7As shown, the detection unit includes a NOR gate, a D flip-flop, and a second resistor R2. The D flip-flop can be a D-type flip-flop. Two input terminals of the NOR gate are respectively connected to the output terminals of the first dynamic comparator and the second dynamic comparator. The output terminal of the NOR gate is connected to the input terminal of the D flip-flop. The trigger terminal of the D flip-flop receives a trigger level signal. The output terminal of the D flip-flop is connected to the second resistor R2 to output a device presence status level signal.

[0085] The second resistor R2 ensures that when the circuit starts up, the device presence status level signal rxdet_st is fixed at a low level. When and only when the comparison level signals cmp_res_p and cmp_res_n are both low, the NOR gate outputs a high-level res_raw signal; in other cases, it is low. When the trigger level signal dff_vc has a rising edge, the D flip-flop will output the current level of the res_raw signal, that is, the detection result. Additionally, when device presence detection is not performed, that is, when the enable signal rxdet_en is low, the D flip-flop maintains the reset state, and the device presence status level signal rxdet_st remains low, ensuring that there is no indeterminate state in all circuits. The clock signal of the D flip-flop is the trigger level signal dff_vc, the reset signal of the D flip-flop is the enable signal rxdet_en, and the output signal of the D flip-flop is the device presence status level signal rxdet_st.

[0086] See Figure 1 As shown, the working principle of the device presence detection circuit in the embodiment of the present invention is further described as follows:

[0087] Before preparing for detection, the input terminals inn and inp of the output stage circuit of the upper-level device remain high, ensuring that the input MOS transistors Minn and Minp of the output stage circuit are both turned on. Figure 1 In it, the tail current source switch S1 controls the closing or opening of the tail current source IDC.

[0088] When S1 is closed, the differential voltage signal is expressed as:

[0089] where i dc is the current of the tail current source IDC, and R TX is the termination resistor of the output stage circuit;

[0090] When S1 is open, since there is no current, the differential voltage signal is expressed as:

[0091] VOP = VON = VO2 = VDD;

[0092] Therefore, by opening and closing S1, the differential voltage signal can be switched back and forth between VO1 and VO2.

[0093] When the downstream device is not connected, that is, there is no termination resistor R at the far end RX , there is no need to charge the coupling capacitor C AC . The capacitor in the time constant RC is the parasitic capacitor Cpara, and the level switching process between VO1 and VO2 is very fast. When the downstream device is connected, that is, there is a termination resistor R at the far end RX , at this time, it is necessary to charge the coupling capacitor C AC . Since the magnitude of the coupling capacitor C AC is much larger than that of the parasitic capacitor, its time constant is also much larger than the case when there is no termination resistor at the far end, and the output common-mode level switching process is slow. Therefore, by detecting the magnitude relationship between the differential voltage signal and the reference voltage signal at a specific moment, it is possible to determine whether there is a termination resistor at the far end, that is, to determine whether the downstream device is connected to the output stage circuit.

[0094] Specifically, when the enable signal rxdet_en is at a low level, that is, when the device presence detection circuit is not enabled, there is no current in the branch where the output terminal of the voltage circuit belongs, and the reference voltage signal Vref is fixed to the power supply voltage VDD. The output of the first AND gate AND1 in the combinational logic unit flips the flag signal to a low level, fixing all the trigger level signals idc_vc, cmp_vc, and dff_vc to a low level, that is, closing the tail current source of the output stage circuit and not affecting the main channel signal transmission. In addition, the flip-flop DFF in the detection unit maintains the reset state, and the device presence status level signal rxdet_st is maintained at a low level through the second resistor R2.

[0095] When the enable signal rxdet_en is at a high level, that is, when the device presence detection circuit is working properly, as Figure 8 shown, the clock signal CLK outputs three trigger level signals through the signal circuit: idc_vc, cmp_vc, and dff_vc. Among them, the trigger level signal idc_vc is used to control the disconnection of the tail current source switch S1 of the output stage circuit, and the differential voltage signal VOP / N at the differential output terminal of the output stage circuit follows the switching of idc_vc. After the differential voltage signal VOP / N switches, cmp_vc controls the comparison unit to start working, comparing the differential voltage signal VOP / N with the reference voltage signal Vref output by the voltage circuit. When the termination resistor R RXWhen it does not exist, the switching speed is relatively fast. Both cmp_res_p and cmp_res_n output by the comparison unit are at high level. The NOR gate NOR in the detection unit outputs res_raw at low level. The flip-flop DFF in the detection unit outputs the device presence status level signal rxdet_st and remains at low level, indicating that the device is not detected to be present. When the termination resistor R RX exists, the termination resistor R RX is connected to the output stage circuit through the coupling capacitor C AC When the comparison unit starts to work, the differential voltage signal VOP / N is less than the reference voltage signal Vref output by the voltage circuit. Both the comparison level signals cmp_res_p and cmp_res_n output by the comparison unit switch to low level. The res_raw signal output by the NOR gate NOR in the detection unit then flips to high level. The device presence status level signal rxdet_st output by the flip-flop DFF in the detection unit also flips to high level, indicating that the device is detected to be present.

[0096] Meanwhile, since the presence status level signal rxdet_st is at high level, the flag signal output by the first AND gate AND1 in the combinational logic unit flips to low level, fixing all the trigger level signals idc_vc, cmp_vc, and dff_vc to low level. That is, the tail current source switch S1 of the output stage circuit is closed, and the comparison unit and the detection unit stop working, and the detection is completed, reducing the circuit power consumption.

[0097] Therefore, compared with the traditional device presence detection circuit, the device presence detection circuit in the embodiment of the present invention is composed of digital units, is more concise in structure, and the trigger level signals therein are all generated by the same clock signal, without complex timing control. All circuits or units only work during the detection process, with low static power consumption. After the detection is completed, the detection function can be automatically turned off without affecting the main signal channel.

[0098] The embodiment of the present invention provides a method for detecting the presence of a load. The method includes the following steps:

[0099] Step S10: Output multiple trigger level signals according to the enable signal and the clock signal.

[0100] Step S20: Output a reference voltage signal according to the enable signal and the current source.

[0101] Step S30: Output a device presence status level signal according to two trigger level signals, a differential voltage signal, and a reference voltage signal.

[0102] Step S40: Determine whether the device is present according to the device presence status level signal.

[0103] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by terms such as "upper" and "lower" is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention. Unless otherwise clearly specified and defined, the terms "mounted", "connected" and "coupled" shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0104] It should be noted that in the present invention, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variation thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0105] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An in-situ detection circuit for a device, which is used to detect the connection state between a lower-level device and the output-stage circuit of a higher-level device, is characterized in that Comprising: A main circuit and a controller; The main circuit includes: A trigger circuit for outputting multiple trigger level signals according to an enable signal and a clock signal; A voltage circuit for outputting a reference voltage signal according to an enable signal and a current source; A detection circuit connected to the differential output terminals of the trigger circuit and the output stage circuit, for outputting a device presence status level signal according to two trigger level signals, a differential voltage signal, and a reference voltage signal; The controller is connected to the detection circuit for determining whether the device is present according to the device presence status level signal.

2. The in-position detection circuit of the device according to claim 1, wherein The controller for determining whether the device is present according to the device presence status level signal includes: When the device presence status level signal is at a low level, it is determined that the device is not present; When the device presence status level signal is at a high level, it is determined that the device is present.

3. The in-position detection circuit of the device according to claim 2, characterized in that, It further includes: When the device presence status level signal is at a high level, the trigger circuit changes the level state of the multiple trigger level signals.

4. The device presence detection circuit according to claim 3, wherein: The trigger circuit includes a first delay unit, a second delay unit, a first monostable unit, a second monostable unit, and a combinational logic unit; The input end of the first delay unit receives the clock signal, the output end of the first delay unit is connected to the input end of the first monostable unit, and the output end of the first monostable unit is connected to the first input end of the combinational logic unit; The input end of the second monostable unit receives the clock signal, the output end of the second monostable unit is connected to the second input end of the combinational logic unit; The third input end of the combinational logic unit receives the device presence status level signal, the fourth input end of the combinational logic unit receives the enable signal, the first output end of the combinational logic unit outputs a first trigger level signal, and the second output end of the combinational logic unit outputs a second trigger level signal; The input end of the second delay unit is connected to the second output end of the combinational logic unit, and the output end of the second delay unit outputs a third trigger level signal.

5. The device presence detection circuit according to claim 4, wherein: The combinational logic unit includes a first inverter, a first AND gate, a second AND gate, and a third AND gate; The input end of the first inverter receives the device presence status level signal, and the output end of the first inverter is connected to the first input end of the first AND gate; The second input end of the first AND gate receives the enable signal, and the output end of the first AND gate is connected to the first input end of the second AND gate and the first input end of the third AND gate; The second input end of the second AND gate is connected to the output end of the second monostable unit, the second input end of the third AND gate is connected to the output end of the first monostable unit, the output end of the second AND gate outputs a first trigger level signal, and the output end of the third AND gate outputs a second trigger level signal respectively.

6. The device presence detection circuit according to claim 1, wherein: The voltage circuit includes a second inverter, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a first resistor; The input terminal of the second inverter receives an enable signal, and the output terminal of the second inverter is connected to the second terminal of the first MOS transistor; The second terminal of the second MOS transistor is connected to the second terminal of the third MOS transistor, and the third terminals of the first MOS transistor, the second MOS transistor, and the third MOS transistor are grounded; The first terminal of the first resistor is connected to a power supply, and the second terminal of the first resistor is connected to the first terminal of the third MOS transistor and the second terminal of the fourth MOS transistor to output a reference voltage signal, and the first terminal and the third terminal of the fourth MOS transistor are grounded.

7. The device in-position detection circuit according to claim 1, wherein: The detection circuit includes a comparison unit and a detection unit. The comparison unit is connected to the differential input terminals of the trigger circuit, the voltage circuit, and the load, and the detection unit is connected to the trigger circuit and the comparison unit; The detection circuit is configured to output a device in-position status level signal according to two trigger level signals, a differential voltage signal, and a reference voltage signal, including: The comparison unit is configured to output two comparison level signals according to one trigger level signal, a differential voltage signal, and a reference voltage signal; The detection unit is configured to output a device in-position status level signal according to an enable signal, one trigger level signal, and two comparison level signals.

8. The device in-position detection circuit according to claim 7, wherein: The comparison unit includes a first dynamic comparator, a second dynamic comparator, a fifth MOS transistor, and a sixth MOS transistor; The non-inverting input terminal of the first dynamic comparator and the inverting input terminal of the second dynamic comparator are respectively connected to the differential output terminals of the output stage circuit. The inverting input terminal of the first dynamic comparator and the non-inverting input terminal of the second dynamic comparator receive the reference voltage signal. The enable terminals of the first dynamic comparator and the second dynamic comparator receive one trigger level signal; The first terminal of the fifth MOS transistor and the first terminal of the sixth MOS transistor are connected to the power supply. The second terminals of the fifth MOS transistor and the sixth MOS transistor are connected to the enable terminals of the first dynamic comparator and the second dynamic comparator. The third terminal of the fifth MOS transistor is connected to the output terminal of the first dynamic comparator to output the first comparison level signal, and the third terminal of the sixth MOS transistor is connected to the output terminal of the second dynamic comparator to output the second comparison level signal.

9. The device in-position detection circuit according to claim 8, wherein: The detection unit includes a NOR gate, a flip-flop, and a second resistor. Two input terminals of the NOR gate are respectively connected to output terminals of the first dynamic comparator and the second dynamic comparator. An output terminal of the NOR gate is connected to an input terminal of the flip-flop. A trigger terminal of the flip-flop receives a path of trigger level signals. An output terminal of the flip-flop is connected to a first terminal of the second resistor to output an in-position state level signal of the device, and a second terminal of the second resistor is grounded.

10. A method for detecting the presence of a load, applied to the device presence detection circuit according to claim 1, characterized in that, The method includes the following steps: Outputting multiple paths of trigger level signals according to an enable signal and a clock signal; Outputting a reference voltage signal according to the enable signal and a current source; Outputting an in-position state level signal of the device according to two paths of trigger level signals, a differential voltage signal, and the reference voltage signal; Determining whether the device is in position according to the in-position state level signal of the device.

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