Voltage-to-current circuit

Abstract

The embodiment of the invention provides a voltage-to-current circuit, and relates to the technical field of power management circuits. The voltage-to-current circuit comprises a two-stage operational amplifier module and a current mirror module; the first-stage operational amplifier module is used for receiving an input voltage and transmitting the input voltage to the second-stage operational amplifier module after first-stage processing; the second-stage operational amplifier module is used for performing second-stage processing on the received voltage and then transmitting the processed voltage to the plug-in end of the voltage-to-current circuit; the output of the second-stage operational amplifier module is drain electrode output; the external end is used for connecting the external resistor and the external capacitor; the voltage of the plug-in end forms a first current through the plug-in resistor, and the current mirror module processes the first current into a second current and outputs the second current; a zero pole formed by the voltage-to-current circuit comprises a first pole; the first pole is determined according to the plug-in resistor and the plug-in capacitor, and the frequency of the first pole is the lowest in all zero poles. The voltage-to-current circuit can be adapted to plug-in resistors and plug-in capacitors in a relatively large range.

Description

Technical Field

[0001] This application relates to the technical field of power management circuits, and particularly to a voltage-to-current circuit. Background Art

[0002] In the application of power management chips, functions such as programmable high-precision clock frequencies and programmable output constant current sources are often required. These functions involve voltage-to-current circuits. Voltage-to-current, denoted as V-to-I, can be achieved by the voltage drop of a reference voltage across a resistor.

[0003] In the design of integrated circuits, the reference voltage has high precision and the technology is very mature. However, the drift of the resistor is 20% or more. In addition, due to the high precision and application flexibility of discrete resistors, external resistors are often required on the chip to implement the V-to-I circuit in order to obtain an accurate current source and thus achieve various required functions.

[0004] During the actual operation of the chip, there are often many noise interferences, resulting in unstable voltage on the external resistor. The external resistor of the V-to-I circuit needs to be shunted with an external capacitor to reduce interference.

[0005] However, the external resistor and capacitor introduce poles into the V-to-I loop, which may cause loop instability. The ranges of the external resistor and external capacitor need to be strictly restricted, which in turn limits the application of the V-to-I circuit.

[0006] How to broaden the ranges of the external resistor and external capacitor of V-to-I is the technical problem to be solved by this application. Summary of the Invention

[0007] The purpose of this application is to provide a voltage-to-current circuit that can adapt to a relatively wide range of external resistors and external capacitors.

[0008] The voltage-to-current circuit includes a first-stage operational amplifier module, a second-stage operational amplifier module, and a current mirror module;

[0009] The first-stage operational amplifier module is used to receive an input voltage, and after the first-stage processing of the input voltage, it is transmitted to the second-stage operational amplifier module;

[0010] The second-stage operational amplifier module is used to transmit the received voltage to the external terminal of the voltage-to-current circuit after the second-stage processing; the output of the second-stage operational amplifier module is a drain output;

[0011] The external terminal is used to connect an external resistor and an external capacitor;

[0012] The voltage at the external connection terminal forms a first current through the external resistor, and the current mirror module processes the first current into a second current and outputs the second current;

[0013] The zero-poles formed by the voltage-to-current circuit include a first pole; the first pole is determined according to the external resistor and the external capacitor, and the frequency of the first pole is the lowest among all zero-poles.

[0014] Optionally, the zero-poles formed by the voltage-to-current circuit further include a first zero, a second pole, a second zero, and a third pole; the frequencies of the first pole, the first zero, the second pole, the second zero, and the third pole increase in sequence.

[0015] Optionally, the voltage-to-current circuit further includes a zero-adjusting resistor;

[0016] The second-stage operational amplifier module is used to transmit the received voltage to the first end of the zero-adjusting resistor after second-stage processing, and the second end of the zero-adjusting resistor is connected to the external connection terminal of the voltage-to-current circuit;

[0017] The first zero is determined according to the equivalent resistance of the second-stage operational amplifier module and the equivalent capacitance of the current mirror module, and the second zero is determined according to the zero-adjusting resistor and the external capacitor, or:

[0018] The second zero is determined according to the equivalent resistance of the second-stage operational amplifier module and the equivalent capacitance of the current mirror module, and the first zero is determined according to the zero-adjusting resistor and the external capacitor.

[0019] Optionally, the second pole is determined according to at least a part of the equivalent resistance in the first-stage operational amplifier module, at least a part of the equivalent capacitance in the first-stage operational amplifier module, and the equivalent capacitance of the second-stage operational amplifier module;

[0020] The third pole is determined according to the equivalent capacitance of the current mirror module and at least a part of the equivalent transconductance in the current mirror module.

[0021] Optionally, the second-stage operational amplifier module includes a first MOS transistor. The gate of the first MOS transistor is used to receive the voltage after first-stage processing by the first-stage operational amplifier module. The first MOS transistor amplifies the voltage received by the gate and transmits it from the drain to the external connection terminal of the voltage-to-current circuit;

[0022] The voltage at the external connection terminal forms a first current through the external resistor. The current mirror module obtains the first current from the source of the first MOS transistor, processes the first current into a second current and outputs the second current.

[0023] Optionally, the voltage-to-current circuit further includes a zero-adjustment resistor;

[0024] The first MOS transistor amplifies the voltage received at its gate and transmits it from the drain to the first end of the zero-adjustment resistor, and the second end of the zero-adjustment resistor is connected to the external connection terminal of the voltage-to-current circuit.

[0025] Optionally, the resistance value of the zero-adjustment resistor is smaller than the resistance value of the external resistor.

[0026] Optionally, the first input terminal of the first-stage operational amplifier module is used to receive an input voltage;

[0027] The second input terminal of the first-stage operational amplifier module is connected to the drain of the first MOS transistor;

[0028] The output terminal of the first-stage operational amplifier module is connected to the gate of the first MOS transistor.

[0029] Optionally, the input stage of the first-stage operational amplifier module includes a current source, a first PMOS transistor, and a second PMOS transistor;

[0030] The output stage of the first-stage operational amplifier module includes a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor unit, and a second NMOS transistor unit;

[0031] The gate of the first PMOS transistor is connected to the drain of the first MOS transistor;

[0032] The source of the first PMOS transistor is connected to the current source; the drain of the first PMOS transistor is connected to the first NMOS transistor unit;

[0033] The gate of the second PMOS transistor is used to receive the input voltage;

[0034] The source of the second PMOS transistor is connected to the current source; the drain of the second PMOS transistor is connected to the second NMOS transistor unit;

[0035] The sources of the third PMOS transistor and the fourth PMOS transistor are both used to connect to a voltage source, and the gates of the third PMOS transistor, the drain of the third PMOS transistor, and the gate of the fourth PMOS transistor are connected together;

[0036] The drain of the third PMOS transistor is connected to the first NMOS transistor unit;

[0037] The drain of the fourth PMOS transistor is connected to the second NMOS transistor unit;

[0038] The gate of the first MOS transistor is used to receive the voltage at the drain of the fourth PMOS transistor.

[0039] Optionally, the first NMOS transistor unit includes a first NMOS transistor and a second NMOS transistor;

[0040] The drain of the second NMOS transistor is connected to the drain of the third PMOS transistor;

[0041] The source of the second NMOS transistor, the drain of the first NMOS transistor, and the drain of the first PMOS transistor are connected together;

[0042] The source of the first NMOS transistor is grounded;

[0043] The second NMOS transistor unit includes a third NMOS transistor and a fourth NMOS transistor;

[0044] The drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor;

[0045] The source of the fourth NMOS transistor, the drain of the third NMOS transistor, and the drain of the second PMOS transistor are connected together;

[0046] The source of the third NMOS transistor is grounded;

[0047] The gates of the first NMOS transistor and the third NMOS transistor are connected to the same first voltage;

[0048] The gates of the second NMOS transistor and the fourth NMOS transistor are connected to the same second voltage.

[0049] Optionally, the current mirror module includes a second MOS transistor, a third MOS transistor, and a fourth MOS transistor;

[0050] The source of the second MOS transistor, the source of the fourth MOS transistor, the source of the third MOS transistor, and the drain of the third MOS transistor are connected together and are used to connect to a voltage source;

[0051] The drain of the second MOS transistor, the gate of the second MOS transistor, the gate of the third MOS transistor, and the gate of the fourth MOS transistor are connected together and are connected to the source of the first MOS transistor;

[0052] The drain of the fourth MOS transistor is used to output the second current.

[0053] Compared with the prior art, the present application has the following beneficial effects:

[0054] In the voltage-to-current circuit provided by the embodiment of the present application, since the output of the second-stage operational amplifier module is a drain output, compared with the source-output scheme, the external resistor can adopt a smaller resistance, the external capacitor connected in parallel with the external resistor can adopt a larger capacitance, and there is no upper limit for the external capacitor, which broadens the range of the external resistor and the external capacitor. Moreover, the external resistor and the external capacitor determine the pole with the lowest frequency, and it is easy to set other poles to poles with higher frequencies. Therefore, it is also easy to implement inserting a zero point between the poles, which is convenient for realizing loop stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without creative efforts.

[0056] Figure 1 Schematic diagram of a V-to-I circuit where the value range of an external resistor R_ext and the capacitor connected in parallel with it is limited;

[0057] Figure 2 Schematic diagram of a voltage-to-current circuit adapted to a larger range of external resistors and external capacitors;

[0058] Figure 3 Schematic diagram of an implementation manner for zero-pole setting provided by the embodiment of the present application;

[0059] Figure 4 Schematic diagram of a voltage-to-current circuit provided by the embodiment of the present application with a zero-adjusting resistor;

[0060] Figure 5 Schematic diagram of a voltage-to-current circuit provided by the embodiment of the present application with a single MOS transistor as the second-stage operational amplifier module;

[0061] Figure 6 For Figure 5 Schematic diagram of adding a zero-adjusting resistor on the basis of;

[0062] Figure 7 For Figure 6 Equivalent schematic diagram of zero-point and pole calculation of. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0063] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application. The described embodiments are some, but not all, of the embodiments of this application. The components of the embodiments of this application usually described in the accompanying drawings here can be arranged and designed in various different configurations.

[0064] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of this application that is claimed, but merely represents selected embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts fall within the scope of protection of this application. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0065] In the description of this application, it should be noted that:

[0066] Relative terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations;

[0067] "Connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium.

[0068] A V-to-I circuit, such as Figure 1 , the voltage output by the MN6 transistor forms a current through R_ext, and this current is then subjected to proportional operation by the current mirror to obtain the current Iout.

[0069] Since the MN6 transistor is an NMOS transistor and the output terminal is the source electrode, the source electrode output of the NMOS transistor is a low resistance, and the external resistor R_ext at the output terminal needs to be very large (and the range of the capacitor connected in parallel with the external resistor R_ext also needs to vary according to the application) to introduce a low-frequency pole. At this time, if the main pole is to be designed in the front stage of the circuit, then the gate of the MN6 transistor needs to be connected to a capacitor, grounded through the capacitor, and may even need to be connected to a resistor to generate a zero point to compensate the phase of the pole. At this time, the external resistor R_ext and the capacitor connected in parallel with it are used as the secondary pole. To ensure sufficient phase margin, the capacitor connected in parallel with the external resistor R_ext needs to be very small, and the value range of the external resistor R_ext and the capacitor connected in parallel with it is limited.

[0070] To broaden the value range of the external resistor R_ext and the capacitor connected in parallel with it, such as Figure 2, an embodiment of the present application provides a voltage-to-current circuit, which includes a first-stage operational amplifier module 1, a second-stage operational amplifier module 2, and a current mirror module 3. The functions of each module are as follows:

[0071] The first-stage operational amplifier module 1 is used to receive the input voltage Vref, and transmit the input voltage Vref to the second-stage operational amplifier module 2 after the first-stage processing;

[0072] The second-stage operational amplifier module 2 is used to transmit the received voltage to the external connection terminal of the voltage-to-current circuit after the second-stage processing. The external connection terminal is used to connect the external resistor R_ext and the external capacitor C_ext. The voltage at the external connection terminal forms a first current I_1 through the external resistor R_ext;

[0073] The current mirror module 3 is used to process the first current I1 into a second current Iout and output the second current Iout.

[0074] The above voltage-to-current circuit can be packaged inside a chip, and the external resistor and the external capacitor are outside the chip. Different output currents can be obtained according to different external resistors.

[0075] Set the output of the second-stage operational amplifier module 2 to be a drain output, so that a smaller resistor can be used for the external resistor, and a smaller capacitor can also be used for the external capacitor connected in parallel with the external resistor, broadening the range of the external resistor and the external capacitor. Determine the pole with the lowest frequency for the external resistor and the external capacitor, that is, the poles and zeros formed by the voltage-to-current circuit include a first pole, and the first pole is determined according to the external resistor R_ext and the external capacitor C_ext, and the frequency of the first pole is the lowest among all poles and zeros. On this basis, it is easy to set other poles to be poles with higher frequencies, so it is also easy to insert zeros between the poles, which is convenient for realizing loop stability.

[0076] As Figure 3 , Figure 3 shows an implementation manner of pole-zero setting. The horizontal axis is frequency, and the vertical axis is gain. The poles and zeros formed by the voltage-to-current circuit can include a first pole Ps1, a first zero Pz1, a second pole Ps2, a second zero Pz2, and a third pole Ps3. The frequencies of the first pole Ps1, the first zero Pz1, the second pole Ps2, the second zero Pz2, and the third pole Ps3 increase in sequence. Since poles cause phase lag and zeros cause phase advance, inserting zeros between poles can compensate for the phase, and inserting zeros between every two poles is beneficial to loop stability.

[0077] The second pole Ps and the third pole Ps3 can be set in the following way:

[0078] The second pole Ps2 can be determined according to at least a part of the equivalent resistance in the first-stage operational amplifier module 1, at least a part of the equivalent capacitance in the first-stage operational amplifier module 1, and the equivalent capacitance of the second-stage operational amplifier module 2;

[0079] The third pole Ps3 can be determined according to the equivalent capacitance of the current mirror module 3 and at least a part of the equivalent transconductance in the current mirror module 3.

[0080] Regarding the position of introducing and adjusting the zero point, by setting the zero-adjusting resistor, such as Figure 4 , the voltage-to-current circuit may further include a zero-adjusting resistor R0. The second-stage operational amplifier module 2 is used to transmit the received voltage to the first end of the zero-adjusting resistor R0 after the second-stage processing. The second end of the zero-adjusting resistor R0 is connected to the external connection end of the voltage-to-current circuit, that is, the output end of the second-stage operational amplifier module 2 is connected to the external resistor and the external capacitor after passing through the zero-adjusting resistor R0. This zero-adjusting resistor R0 can affect the zero point of the loop, and adjusting the zero-adjusting resistor R0 can adjust Figure 3 the position of the zero point in

[0081] such that the zero point is located between the poles to stabilize the loop. Figure 3 By means of the zero-adjusting resistor R0, a second zero point Pz2 can be formed

[0082] between the second pole Ps2 and the third pole Ps3: The first zero point Pz1 is determined according to the equivalent resistance of the second-stage operational amplifier module 2 and the equivalent capacitance of the current mirror module 3, and the second zero point Pz2 is determined according to the zero-adjusting resistor R0 and the external capacitor C_ext. Figure 3 Or, by means of the zero-adjusting resistor R0, a first zero point Pz1 can be formed

[0083] between the first pole Ps1 and the second pole Ps2: The second zero point Pz2 is determined according to the equivalent resistance of the second-stage operational amplifier module 2 and the equivalent capacitance of the current mirror module 3, and the first zero point Pz1 is determined according to the zero-adjusting resistor R0 and the external capacitor C_ext. Figure 5 Regarding the implementation manner of the second-stage operational amplifier module 2, such as

[0084] The second-stage operational amplifier module 2 may include a first MOS transistor MP6. The gate of the first MOS transistor MP6 is used to receive the voltage after the first-stage processing of the first-stage operational amplifier module 1. The first MOS transistor MP6 amplifies the voltage received by the gate and transmits it from the drain to the external connection end IN of the voltage-to-current circuit.

[0085] Such as Figure 6In the illustrated embodiment, the voltage-to-current circuit may further include a zero-adjustment resistor R0. The first MOS transistor MP6 amplifies the voltage received at its gate and transmits it from the drain to the first end of the zero-adjustment resistor R0. The second end of the zero-adjustment resistor R0 is connected to the external connection terminal IN of the voltage-to-current circuit. The resistance value of the zero-adjustment resistor R0 may be much smaller than the resistance value of the external resistor R_ext. For example, the resistance value of the external resistor R_ext is at the kΩ level, and the resistance value of the zero-adjustment resistor R0 is dozens of Ω, which is beneficial to saving the area of the voltage-to-current circuit, thereby saving the area of the chip encapsulating the voltage-to-current circuit. In practical applications, the zero-adjustment resistor may be encapsulated outside the chip or inside the chip.

[0086] Regarding an embodiment of the above first-stage operational amplifier module 1, as Figure 6 , the input stage of the first-stage operational amplifier module 1 may include a current source, a first PMOS transistor MP2, and a second PMOS transistor MP3. The current source may be implemented by applying the Vb1 voltage through the MP1 transistor and its gate.

[0087] The output stage of the first-stage operational amplifier module 1 includes a third PMOS transistor MP4, a fourth PMOS transistor MP5, a first NMOS transistor unit, and a second NMOS transistor unit. In the output stage of the first-stage operational amplifier module 1, the PMOS transistors may be in a folded cascode structure. Compared with Figure 1 the cascode transistors of the PMOS are reduced ( Figure 1 MP5' and MP4' in

[0088] ), and the first-stage output impedance is reduced.

[0089] The gate of the first PMOS transistor MP2 is connected to the drain of the first MOS transistor MP6;

[0090] The source of the first PMOS transistor MP2 is connected to the current source; the drain of the first PMOS transistor MP2 is connected to the first NMOS transistor unit;

[0091] The gate of the second PMOS transistor MP3 is used to receive the input voltage Vref;

[0092] The source of the second PMOS transistor MP3 is connected to the current source; the drain of the second PMOS transistor MP3 is connected to the second NMOS transistor unit;

[0093] The sources of the third PMOS transistor MP4 and the fourth PMOS transistor MP5 are both used to connect to the voltage source VCC. The gate of the third PMOS transistor MP4, the drain of the third PMOS transistor MP4, and the gate of the fourth PMOS transistor MP5 are connected together;

[0094] The drain of the third PMOS transistor MP4 is connected to the first NMOS transistor unit;

[0095] The drain of the fourth PMOS transistor MP5 is connected to the second NMOS transistor unit;

[0096] The gate of the first MOS transistor MP6 is used to receive the voltage of the drain of the fourth PMOS transistor MP5.

[0097] Such as Figure 6 , the above-mentioned first NMOS transistor unit may include a first NMOS transistor MN1 and a second NMOS transistor MN2, and the above-mentioned second NMOS transistor unit may include a third NMOS transistor MN3 and a fourth NMOS transistor MN4, and there are the following connection relationships:

[0098] The drain of the second NMOS transistor MN2 is connected to the drain of the third PMOS transistor MP4;

[0099] The source of the second NMOS transistor MN2, the drain of the first NMOS transistor MN1, and the drain of the first PMOS transistor MP2 are connected together;

[0100] The source of the first NMOS transistor MN1 is grounded;

[0101] The drain of the fourth NMOS transistor MN4 is connected to the drain of the fourth PMOS transistor MP5;

[0102] The source of the fourth NMOS transistor MN4, the drain of the third NMOS transistor MN3, and the drain of the second PMOS transistor MP3 are connected together;

[0103] The source of the third NMOS transistor MN3 is grounded;

[0104] The gates of the first NMOS transistor MN1 and the third NMOS transistor MN3 are connected to the same first voltage Vb3;

[0105] The gates of the second NMOS transistor MN2 and the fourth NMOS transistor MN4 are connected to the same second voltage Vb2.

[0106] An implementation manner of the above current mirror module 3 is as Figure 6 , the current mirror module 3 includes a second MOS transistor MP7, a third MOS transistor MP8, and a fourth MOS transistor MP9, and there are the following connection relationships:

[0107] The source of the second MOS transistor MP7, the source of the fourth MOS transistor MP9, the source of the third MOS transistor MP8, and the drain of the third MOS transistor MP8 are connected together and are used to connect to the voltage source VCC;

[0108] The drain of the second MOS transistor MP7, the gate of the second MOS transistor MP7, the gate of the third MOS transistor MP8, and the gate of the fourth MOS transistor MP9 are connected together and are connected to the source of the first MOS transistor MP6;

[0109] The drain of the fourth MOS transistor MP9 is used to output the second current Iout.

[0110] The current of the fourth MOS transistor MP9 is I_1. In the case of having a zero-adjustment resistor, I_1 = Vref / (R_ext + R0). The second current Iout obtained through the current mirror module 3 is Iout = n * I_1 = n * Vref / (R_ext + R0), where n is the mirror ratio of the current mirror module 3. The order of magnitude of the zero-adjustment resistor R0 is smaller than that of the external resistor R_ext. For example, the resistance value of the external resistor R_ext is in the kΩ level, and the resistance value of the zero-adjustment resistor R0 is dozens of Ω. Therefore, the influence of R0 on the accuracy of Iout is very small and can be ignored, so that Iout is a high-precision current.

[0111] Figure 7 shows Figure 6 An equivalent diagram for zero and pole calculations. The first input terminal of the first-stage operational amplifier module 1 is used to receive the input voltage Vref. The second input terminal of the first-stage operational amplifier module 1 can be connected to the drain of the first MOS transistor MP6. According to the property of virtual short of the operational amplifier, the drain voltage of the first MOS transistor MP6 is also the input voltage Vref. The output terminal of the first-stage operational amplifier module 1 is connected to the gate of the first MOS transistor MP6.

[0112] From Figure 7 it can be known that the transfer function of the loop is:

[0113] Av = gmp2 × (ro_mp5 / / C1) × gmp6 × (1 / gmp7 / / C2 + ro_mp6) / / (Rext / / C ext)

[0114] In the formula, gmp2 is the equivalent transconductance of the input stage of the first-stage operational amplifier module 1, ro_mp5 is the output resistance of the fourth PMOS transistor MP5, gmp6 is the equivalent transconductance of the first MOS transistor MP6, gmp7 is the equivalent transconductance of the second MOS transistor, ro_mp6 is the output resistance of the first MOS transistor MP6, the capacitance value C_ext of the external capacitor is in the order of several hundred pF to nF, C1 and C2 are equivalent capacitors in the circuit, and C1 and C2 are relatively small compared to C_ext. C1 includes the gate-source capacitance of the first MOS transistor MP6 and the drain-source capacitance of the fourth PMOS transistor MP5, and its expression is as follows:

[0115] C1 = Cgs_mp6 + Cds_mp5

[0116] C2 includes the gate-source and drain-source parasitic capacitances of the second MOS transistor MP7, the gate-source parasitic capacitance of the third MOS transistor MP8, and the gate-drain and gate-source parasitic capacitances of the fourth MOS transistor MP9. Adding a decoupling capacitor, namely the fourth MOS transistor MP9, before the gates of the second MOS transistor MP7 and the third MOS transistor MP8 and the voltage source VCC can improve the current anti-interference ability of the current mirror module 3. Thus, the expression for C2 is obtained as follows:

[0117] C2 = Cgs_mp7 + Cds_mp7 + Cgs_mp8 + Cgs_mp9 + Cgd_mp9

[0118] According to the expressions of C1 and C2, smaller MOS transistors can be selected as the first MOS transistor MP6 and the fourth PMOS transistor MP5, thereby reducing C1 and relatively increasing C2. For example, C1 is in the order of fF and C2 is in the order of pF. Reducing C1 and increasing C2 can optimize the zero-pole distribution, and its principle will be discussed later.

[0119] At this time, the main zero-poles of the voltage-to-current circuit are as follows:

[0120] Ps1 = R_ext × C_ext

[0121] Ps3 = ro_mp5 × C1

[0122] Ps3 = 1 / gmp7 × C2

[0123] Pz1 = ro_mp6 × C2

[0124] Pz2 = R0 × C_ext

[0125] Regarding the poles: The external capacitor R_ext and the external capacitor C_ext are both relatively large, so Ps1 is the dominant pole; Ps2 is composed of ro_mp5 and C1 and is little affected by the external resistor and capacitor, with a fixed position; Ps3 is composed of 1 / gmp7 and C2, and 1 / gmp7 is affected by the external resistor R_ext and has a small value. Although C2 > C1, ro_mp5 is much larger than 1 / gmp7, so Ps2 is located in the intermediate frequency range and Ps3 is located in the high frequency range. Making the above zero-pole frequencies Figure 3 distributed as, that is, Ps1 > Ps2 > Ps3, so the minimum value of the product of the external resistor and capacitor can be determined according to Ps1 > Ps2 > Ps3.

[0126] Regarding the zeros: Pz1 is composed of ro_mp6 and C2, and Pz2 is composed of R0 and C_ext. The zero-pole distribution diagram of the conventional application situation can be obtained as Figure 3 distributed. If C_ext is several nF, then due to Pz1 > Ps2 > Pz2, the loop is stable.

[0127] Consider the case where the range of C_ext is wider. When C_ext is small, Pz1 > Pz2; when C_ext is large, Pz2 > Pz1. The positions of Pz1 and Pz2 change with the change of C_ext, but the two zeros of Pz1 and Pz2 are always between Ps1 and Ps3, that is, the middle zero-pole has a following characteristic, and the loop is always stable.

[0128] From the above zero-poles, when the external resistor R_ext is large, both Ps1 and Ps3 will move to the low-frequency region, and a larger C_ext is required. In the case of a determined external resistor, only the minimum value of the external capacitor C_ext is restricted. As C_ext increases, the phase margin approaches and maintains near 90°, and the loop stability is guaranteed. For the anti-interference ability of the chip, the larger the capacitance value of the external capacitor, the stronger its anti-interference ability, and there is no upper limit for the external capacitor, which is an advantage not possessed by the existing design structures.

[0129] Generally speaking, Figure 6 In the embodiment shown, the two-stage operational amplifier introduces two poles and one zero at a relatively high frequency, and the zero-adjusting resistor and the external resistor-capacitor introduce one zero and one pole. Taking the external resistor-capacitor as the main pole and the second-stage pole of the operational amplifier as the high-frequency pole, introducing the zero-adjusting resistor R0 to increase the zero is beneficial to the loop stability. The PMOS transistor series current mirror introduces a zero-pole pair with a following characteristic, broadening the range of the external resistor-capacitor, so that the voltage-to-current circuit proposed in this application can be applied in a wider field.

[0130] Based on the above embodiments, the embodiments of the present application further provide a voltage-to-current chip. The above voltage-to-current circuit can be encapsulated inside the voltage-to-current chip, and the external resistor and the external capacitor are outside the voltage-to-current chip. Different output currents can be obtained according to different external resistors.

[0131] Generally speaking, the present application proposes a voltage-to-current circuit. By using a two-stage operational amplifier and combining with a parasitic resistor-capacitor network, zero-pole following is realized for loop compensation, and the range of the external resistor and the external capacitor can be widened as much as possible. On the one hand, when the external resistor is determined, the external resistor can be continuously increased, the phase margin approaches 90° and is maintained, and the loop stability is guaranteed, which will greatly increase the anti-interference ability of the circuit. On the other hand, due to the reduction of the influence of the zero-pole on the external resistor and the range of the external resistor is widened as much as possible, the voltage-to-current circuit proposed in this application can also be applied in a wider field.

[0132] The device and system embodiments described above are only illustrative. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative work.

[0133] The above are only the preferred specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A voltage-to-current circuit, characterized in that, It includes a first-stage operational amplifier module, a second-stage operational amplifier module, and a current mirror module; The first-stage operational amplifier module is used to receive an input voltage, and after the first-stage processing of the input voltage, it is transmitted to the second-stage operational amplifier module; The second-stage operational amplifier module is used to transmit the received voltage to the external connection terminal of the voltage-to-current circuit after the second-stage processing; the output of the second-stage operational amplifier module is a drain output; The external connection terminal is used to connect an external resistor and an external capacitor; The voltage at the external connection terminal forms a first current through the external resistor, and the current mirror module processes the first current into a second current and outputs the second current; The zero-pole points formed by the voltage-to-current circuit include a first pole point; the first pole point is determined according to the external resistor and the external capacitor, and the frequency of the first pole point is the lowest among all the zero-pole points.

2. The voltage-to-current circuit according to claim 1, wherein The zero-pole points formed by the voltage-to-current circuit further include a first zero point, a second pole point, a second zero point, and a third pole point; the frequencies of the first pole point, the first zero point, the second pole point, the second zero point, and the third pole point increase in sequence.

3. The voltage-to-current circuit according to claim 2, wherein The voltage-to-current circuit further includes a zero-adjustment resistor; The second-stage operational amplifier module is used to transmit the received voltage to the first end of the zero-adjustment resistor after the second-stage processing, and the second end of the zero-adjustment resistor is connected to the external connection terminal of the voltage-to-current circuit; The first zero point is determined according to the equivalent resistance of the second-stage operational amplifier module and the equivalent capacitance of the current mirror module, and the second zero point is determined according to the zero-adjustment resistor and the external capacitor, or: The second zero point is determined according to the equivalent resistance of the second-stage operational amplifier module and the equivalent capacitance of the current mirror module, and the first zero point is determined according to the zero-adjustment resistor and the external capacitor.

4. The voltage-to-current circuit according to claim 2, wherein The second pole point is determined according to at least a part of the equivalent resistance in the first-stage operational amplifier module, at least a part of the equivalent capacitance in the first-stage operational amplifier module, and the equivalent capacitance of the second-stage operational amplifier module; The third pole point is determined according to the equivalent capacitance of the current mirror module and at least a part of the equivalent transconductance in the current mirror module.

5. The voltage-to-current circuit according to claim 1, wherein The second-stage operational amplifier module includes a first MOS transistor. The gate of the first MOS transistor is used to receive the voltage after the first-stage processing of the first-stage operational amplifier module. The first MOS transistor amplifies the voltage received at the gate and transmits it from the drain to the external connection terminal of the voltage-to-current circuit; The voltage at the external connection terminal forms a first current through the external resistor, and the current mirror module obtains the first current from the source of the first MOS transistor, processes the first current into a second current, and outputs the second current.

6. The voltage-to-current circuit according to claim 5, wherein The voltage-to-current circuit further includes a zero-adjustment resistor; The first MOS transistor amplifies the voltage received at the gate and transmits it from the drain to the first end of the zero-adjustment resistor, and the second end of the zero-adjustment resistor is connected to the external connection terminal of the voltage-to-current circuit.

7. The voltage-to-current circuit according to claim 6, wherein The resistance value of the zero-adjustment resistor is smaller than the resistance value of the external resistor.

8. The voltage-to-current circuit according to claim 5, wherein The first input terminal of the first-stage operational amplifier module is used to receive an input voltage; The second input terminal of the first-stage operational amplifier module is connected to the drain of the first MOS transistor; The output terminal of the first-stage operational amplifier module is connected to the gate of the first MOS transistor.

9. The voltage-to-current circuit according to claim 5, wherein The input stage of the first-stage operational amplifier module includes a current source, a first PMOS transistor, and a second PMOS transistor; The output stage of the first-stage operational amplifier module includes a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor unit, and a second NMOS transistor unit; The gate of the first PMOS transistor is connected to the drain of the first MOS transistor; The source of the first PMOS transistor is connected to the current source; the drain of the first PMOS transistor is connected to the first NMOS transistor unit; The gate of the second PMOS transistor is used to receive an input voltage; The source of the second PMOS transistor is connected to the current source; the drain of the second PMOS transistor is connected to the second NMOS transistor unit; The sources of the third PMOS transistor and the fourth PMOS transistor are both used to connect to a voltage source, and the gate of the third PMOS transistor, the drain of the third PMOS transistor, and the gate of the fourth PMOS transistor are connected together; The drain of the third PMOS transistor is connected to the first NMOS transistor unit; The drain of the fourth PMOS transistor is connected to the second NMOS transistor unit; The gate of the first MOS transistor is used to receive the voltage of the drain of the fourth PMOS transistor; The first NMOS transistor unit includes a first NMOS transistor and a second NMOS transistor; The drain of the second NMOS transistor is connected to the drain of the third PMOS transistor; The source of the second NMOS transistor, the drain of the first NMOS transistor, and the drain of the first PMOS transistor are connected together; The source of the first NMOS transistor is grounded; The second NMOS transistor unit includes a third NMOS transistor and a fourth NMOS transistor; The drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor; The source of the fourth NMOS transistor, the drain of the third NMOS transistor, and the drain of the second PMOS transistor are connected together; The source of the third NMOS transistor is grounded; The gates of the first NMOS transistor and the third NMOS transistor are connected to the same first voltage; The gates of the second NMOS transistor and the fourth NMOS transistor are connected to the same second voltage.

10. The voltage-to-current circuit according to claim 5, wherein The current mirror module includes a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; The sources of the second MOS transistor, the fourth MOS transistor, the source of the third MOS transistor, and the drain of the third MOS transistor are connected together and are used to connect to a voltage source; The drain of the second MOS transistor, the gate of the second MOS transistor, the gate of the third MOS transistor, and the gate of the fourth MOS transistor are connected together and are connected to the source of the first MOS transistor; The drain of the fourth MOS transistor is used to output the second current.

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