Linear voltage stabilizing circuit

Abstract

The invention discloses a linear voltage stabilizing circuit, which belongs to the technical field of integrated circuits and comprises an amplifying unit, a voltage regulating unit and a voltage dividing unit which are connected in sequence. The amplification unit, the voltage division unit and a fourth transistor of the voltage regulation unit form a voltage feedback slow loop; and the second capacitor, the third transistor and the second transistor of the voltage regulation unit form a quick response loop. The voltage drop signal is quickly coupled to the transistor by adopting the capacitor, the voltage is further regulated and controlled by regulating and controlling the current flowing through the transistor, the common-mode noise interference is reduced, faster transient response can be realized when the output voltage is quickly changed only by internally arranging the picofarad magnitude on-chip compensation capacitor, the common-mode noise is effectively counteracted by utilizing the characteristics of the circuit, and the output voltage is greatly improved. And the power supply rejection ratio is excellent in both low-frequency and high-frequency environments.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a linear voltage regulator circuit. Background Art

[0002] A digital isolator is an electronic device used to transmit digital signals under electrical isolation conditions. It transmits digital signals through an isolation barrier (such as optical, magnetic, or capacitive coupling) to achieve non-physical connection transmission between two circuit systems, blocking interference such as high voltage and noise, and is widely used in electrical isolation applications. Among them, capacitive coupling isolators are widely used due to their small size and strong anti-interference ability.

[0003] Common mode transient immunity (CMTI) is a key indicator of digital isolators. The change in the GND voltage at the receiving end of a digital isolator generates common mode noise inside the chip, which is transmitted to the sending end through the isolation capacitor, pulling down the voltage of the low dropout linear regulator (LDO) and affecting the operation of the internal circuits of the chip. Traditional low dropout linear regulator circuits have low self-gain and low power supply rejection ratio. If there is a disturbance on the power supply, the output voltage V OUT may shift, making it difficult to cope with high-frequency common mode noise and unable to ensure the normal transmission of high-frequency signals in digital isolators.

[0004] In the prior art, a PMOS power transistor is used to solve the problem of high-frequency common mode noise, but there are problems with the response speed. It is often necessary to increase the capacitance at the output voltage terminal to improve stability, resulting in the inability to implement an on-chip low dropout linear regulator circuit. Moreover, conventional low dropout linear regulator circuits use a five-transistor operational transconductance amplifier (OTA) structure, with low gain and power supply rejection ratio (PSRR). When there is a power supply disturbance, the output voltage is prone to shift, and a single feedback loop cannot cancel the common mode noise when the receiving end voltage changes rapidly, resulting in a decrease in the output voltage and making it unable to be used in digital isolators. Summary of the Invention

[0005] This application aims to provide a linear voltage regulator circuit that can cancel common mode noise and suppress output voltage shift when the output voltage changes rapidly.

[0006] To achieve the above objective, the technical solution of this application is: A linear voltage regulator circuit includes, an amplification unit, a voltage regulation unit, and a voltage division unit, which are connected in sequence; Among them, the voltage regulation unit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, and a first resistor; a first terminal of the first resistor is connected to a second terminal of the second transistor and a first terminal of the third transistor, a third terminal of the second transistor is connected to a second terminal of the fourth transistor, a first terminal of the second capacitor, and a second terminal of the first transistor, a first terminal of the fourth transistor is connected to a first terminal of the first capacitor, a third terminal of the fourth transistor is connected to a second terminal of the second capacitor and a third terminal of the third transistor, and a third terminal of the first transistor is connected to a second terminal of the first capacitor.

[0007] Optionally, the amplification unit includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; The first terminals of the fifth transistor and the sixth transistor, the seventh transistor and the eighth transistor, the ninth transistor and the tenth transistor, and the eleventh transistor and the twelfth transistor are respectively connected, a second terminal of the fifth transistor is connected to a second terminal of the sixth transistor, a third terminal of the fifth transistor is connected to a second terminal of the seventh transistor, a third terminal of the sixth transistor is connected to a second terminal of the eighth transistor, a third terminal of the seventh transistor is respectively connected to a third terminal of the ninth transistor, a first terminal of the eleventh transistor, and a first terminal of the twelfth transistor, a third terminal of the eighth transistor is connected to a third terminal of the tenth transistor, a second terminal of the ninth transistor is connected to a third terminal of the eleventh transistor, a second terminal of the tenth transistor is connected to a third terminal of the twelfth transistor, and a second terminal of the eleventh transistor is connected to a second terminal of the twelfth transistor; A first terminal of the fourteenth transistor is connected to a reference voltage, a second terminal of the thirteenth transistor is connected to a second terminal of the fourteenth transistor, a third terminal of the thirteenth transistor is connected to a series midpoint of a third terminal of the sixth transistor and a second terminal of the eighth transistor, a third terminal of the fourteenth transistor is connected to a series midpoint of a third terminal of the fifth transistor and a second terminal of the seventh transistor, a first terminal of the fifteenth transistor is connected to a first terminal of the eleventh transistor, a second terminal of the fifteenth transistor is connected to a second terminal of the eleventh transistor, and a third terminal of the fifteenth transistor is connected to a series midpoint of a second terminal of the thirteenth transistor and a second terminal of the fourteenth transistor.

[0008] Optionally, the second terminal of the first resistor is connected to the second terminal of the sixth transistor, the first terminal of the fourth transistor is connected to the series midpoint of the third terminal of the eighth transistor and the third terminal of the tenth transistor, the first terminal of the second transistor is connected to the first terminal of the tenth transistor, the first terminal of the first transistor is connected to the first terminal of the twelfth transistor, and the second terminal of the first capacitor is connected to the second terminal of the twelfth transistor.

[0009] Optionally, the voltage dividing unit includes: a second resistor, a third resistor, and a third capacitor; the first terminal of the second resistor is connected to the first terminal of the third capacitor, and the second terminal of the second resistor is connected to the first terminal of the third resistor and the second terminal of the third capacitor.

[0010] Optionally, the first terminal of the second resistor is connected to the second terminal of the second capacitor, the second terminal of the third resistor is connected to the second terminal of the first transistor, the first terminal of the third resistor is connected to the first terminal of the thirteenth transistor, and the first terminal of the third capacitor is connected to the output voltage.

[0011] Optionally, the third transistor and the fourth transistor are PMOS transistors, and the first transistor and the second transistor are NMOS transistors.

[0012] Optionally, the thirteenth transistor and the fourteenth transistor are NMOS transistors.

[0013] Optionally, the thirteenth transistor and the fourteenth transistor are PMOS transistors.

[0014] Optionally, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are PMOS transistors, and the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor are NMOS transistors.

[0015] Optionally, the order of magnitude of the first capacitor and the second capacitor includes picofarads.

[0016] In this application, by designing a fast response loop of a linear voltage regulator circuit under a conventional monolithic integration process technology, a capacitor is used to quickly couple the signal of the voltage drop to a transistor, and the voltage is further regulated by controlling the current flowing through the transistor, reducing the common-mode noise interference. Without relying on a large off-chip load capacitor, only a picofarad-level on-chip compensation capacitor is built in, and a faster transient response can be achieved when the output voltage V OUT changes rapidly due to a rapid change in the GND voltage, effectively canceling the common-mode noise; the linear voltage regulator circuit provided by this application has an excellent low-frequency power supply rejection ratio (about 130 dB), and the power supply rejection ratio still reaches 38 dB at a high frequency of 1 MHz, and can still effectively reduce the common-mode noise interference generated by the power supply voltage.

[0017] In order to make the above-described features and advantages of the application more obvious and understandable, specific embodiments are given below and detailed descriptions are provided in conjunction with the accompanying drawings as follows. Description of the Drawings

[0018] Figure 1 This is the structural diagram of the linear voltage regulator circuit provided by the present application.

[0019] Figure 2 This is the circuit diagram of the first specific embodiment of the linear voltage regulator circuit provided by the present application.

[0020] Figure 3 This is the transient response simulation waveform diagram when the load current of the traditional linear voltage regulator circuit is 0 - 10 mA.

[0021] Figure 4 This is the transient response simulation waveform diagram when the load current of the traditional linear voltage regulator circuit is 10 mA - 0.

[0022] Figure 5 This is the simulation waveform diagram of the fast loop of the linear voltage regulator circuit provided by the present application.

[0023] Figure 6 This is the simulation waveform diagram of the slow voltage feedback loop of the linear voltage regulator circuit provided by the present application.

[0024] Figure 7 This is the overall simulation waveform diagram of the linear voltage regulator circuit provided by the present application.

[0025] Figure 8 This is the simulation waveform diagram of the power supply rejection ratio of the linear voltage regulator circuit provided by the present application. Detailed Embodiments

[0026] To make the objectives and technical solutions of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0027] The present application provides a linear voltage regulator circuit. Please refer to Figure 1 , Figure 1 This is the structural diagram of the linear voltage regulator circuit provided by the present application. The linear voltage regulator circuit provided by the present application includes: An amplification unit 11, a voltage regulation unit 12, and a voltage division unit 13, which are connected in sequence.

[0028] As an example, please refer to Figure 2 ,Figure 2 This is the circuit diagram of the first specific embodiment of the linear voltage regulator circuit provided by this application. The amplifying unit 11 includes: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M 10 , an eleventh transistor M 11 , a twelfth transistor M 12 , a thirteenth transistor M 13 , a fourteenth transistor M 14 and a fifteenth transistor M 15 .

[0029] The first terminals of the fifth transistor M5 and the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8, the ninth transistor M9 and the tenth transistor M 10 , the eleventh transistor M 11 and the twelfth transistor M 12 are respectively connected. The second terminal of the fifth transistor M5 is connected to the second terminal of the sixth transistor M6. The third terminal of the fifth transistor M5 is connected to the second terminal of the seventh transistor M7. The third terminal of the sixth transistor M6 is connected to the second terminal of the eighth transistor M8. The third terminal of the seventh transistor M7 is connected to the third terminal of the ninth transistor M9, the first terminal of the eleventh transistor M 11 and the first terminal of the twelfth transistor M 12 are respectively connected. The third terminal of the eighth transistor M8 is connected to the third terminal of the tenth transistor M 10 . The second terminal of the ninth transistor M9 is connected to the third terminal of the eleventh transistor M 11 . The second terminal of the tenth transistor M 10 is connected to the third terminal of the twelfth transistor M 12 . The second terminal of the eleventh transistor M 11 is connected to the second terminal of the twelfth transistor M 12 .

[0030] The first terminal of the fourteenth transistor M 14 is connected to the reference voltage V REF . The second terminal of the thirteenth transistor M 13 is connected to the second terminal of the fourteenth transistor M 14 . The third terminal of the thirteenth transistor M 13 is connected to the series midpoint of the third terminal of the sixth transistor M6 and the second terminal of the eighth transistor M8. The third terminal of the fourteenth transistor M 14 is connected to the series midpoint of the third terminal of the fifth transistor M5 and the second terminal of the seventh transistor M7. The first terminal of the fifteenth transistor M 15 is connected to the eleventh transistor M 11The first terminal of the fifteenth transistor M is connected to 15 The second terminal of the eleventh transistor M is connected to 11 The second terminal of the fifteenth transistor M is connected to 15 The third terminal of the fifteenth transistor M is connected to the series midpoint of the second terminal of the thirteenth transistor M13 and the second terminal of the fourteenth transistor M 14 ; As an example, the voltage regulating unit 12 includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor C1, a second capacitor C2, and a first resistor R1; the first terminal of the first resistor R1 is connected to the third terminal of the second transistor M2 and the first terminal of the third transistor M3, the second terminal of the second transistor M2 is connected to the third terminal of the fourth transistor M4, the first terminal of the second capacitor C2, and the third terminal of the first transistor M1, the first terminal of the fourth transistor M4 is connected to the first terminal of the first capacitor C1, the third terminal of the fourth transistor M4 is connected to the second terminal of the second capacitor C2 and the third terminal of the third transistor M3, and the second terminal of the first transistor M1 is connected to the second terminal of the first capacitor C1.

[0031] The second terminal of the first resistor R1 is connected to the second terminal of the sixth transistor M6, the first terminal of the fourth transistor M4 is connected to the series midpoint of the third terminal of the eighth transistor M8 and the third terminal of the tenth transistor M 10 ; the first terminal of the second transistor M2 is connected to the first terminal of the tenth transistor M 10 ; the first terminal of the first transistor M1 is connected to the first terminal of the twelfth transistor M 12 ; the second terminal of the first capacitor C1 is connected to the second terminal of the twelfth transistor M 12 ;

[0032] As an example, the voltage dividing unit 13 includes: a second resistor R2, a third resistor R3, and a third capacitor C3; the first terminal of the second resistor R2 is connected to the first terminal of the third capacitor C3, the second terminal of the second resistor R2 is connected to the first terminal of the third resistor R3 and the second terminal of the third capacitor C3.

[0033] The first terminal of the second resistor R2 is connected to the second terminal of the second capacitor C2, the second terminal of the third resistor R3 is connected to the second terminal of the first transistor M1, and the first terminal of the third resistor R3 is connected to the first terminal of the thirteenth transistor M 13 ; the first terminal of the third capacitor C3 is connected to the output voltage V OUT ; the first terminal of the third capacitor C3 and the first terminal of the third resistor R3 are connected to the current source DC.

[0034] As an example, the first terminal of the first capacitor C1 is grounded.

[0035] As an example, the first transistor M1, the second transistor M2, the ninth transistor M9, and the tenth transistor M 10 , the eleventh transistor M 11 , the twelfth transistor M 12 , the thirteenth transistor M 13 , the fourteenth transistor M 14 and the fifteenth transistor M 15 are NMOS transistors.

[0036] As an example, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are PMOS transistors.

[0037] As an example, the first terminal of each transistor is its gate, the second terminal of each transistor is its source, and the third terminal of each transistor is its drain.

[0038] Next, continue to describe the working principle of this application in combination with Figure 2 to illustrate the working principle of this application.

[0039] As an example, in this application, the amplification unit 11, the voltage division unit 13, and the fourth transistor M4 form a voltage feedback slow loop. In the amplification unit 11, the thirteenth transistor M 13 and the fourteenth transistor M 14 serve as an input pair of transistors, converting the output voltage V OUT into a current. The current passes through the output load of the folded current mirror structure composed of the ninth transistor M9 to the fifteenth transistor M15 to amplify the output voltage V OUT . At the same time, the output load of the folded current mirror structure improves the DC gain and power supply rejection ratio, and has a larger DC gain and a larger power supply rejection ratio (PSRR) compared with the traditional operational amplifier. The PMOS source follower, that is, the fourth transistor M4, is used as the output stage of the amplification unit 11, and the second transistor M2, which is also a PMOS transistor, is used as the load of the output stage to buffer the pre-stage amplified signal and drive the post-stage transistor. In the voltage division unit 13, the output voltage V OUT is divided by the second resistor R2 and the third resistor R3 and compared with the reference voltage V REF at the input port, so that the output voltage V OUT is compared with the reference voltage V REFIt has a proportional relationship to achieve stable control of the voltage feedback slow loop. At the same time, in the voltage feedback slow loop, since the fourth transistor M4 is the output stage of the amplification unit 11, the gate of the fourth transistor M4 is a high-impedance point, and a relatively large main pole will be formed at the gate of the fourth transistor M4. The parasitic capacitance of the fourth transistor M4 is small. To meet the sufficient loop phase margin, a first capacitor C1 is added to the gate of the fourth transistor M4 to push the main pole to a lower frequency and maintain the stability of the linear voltage regulator circuit; further, the area of the input pair transistors and the current mirror structure is increased to ensure that the linear voltage regulator circuit has a low offset and maintain a low offset voltage.

[0040] As an example, the second capacitor C2, the third transistor M3 and the second transistor M2 form a fast response loop. The function of the voltage feedback slow loop is to maintain normal circuit feedback and ensure that the output voltage has normal offset adjustment ability. However, the response speed of the voltage feedback slow loop is slow and cannot cancel the interference brought by high-frequency noise in the linear voltage regulator circuit. Therefore, a fast response loop is added to cancel high-frequency common-mode noise. The second capacitor C2 quickly couples the signal of voltage change to the transistors in the fast response loop for feedback. By regulating the current flowing through the third transistor M3 and the second transistor M2, different voltage drops are formed at the first resistor R1, and further regulate the gate-source voltage V of the third transistor M3 GS3 , using the characteristics of the circuit itself to achieve a faster transient response when the output voltage V OUT changes rapidly due to the rapid change of the GND voltage, and reduce the common-mode noise interference.

[0041] When the output voltage V OUT rises rapidly, the voltages of the second resistor R2 and the third resistor R3 of the voltage dividing unit 13 increase, the gate voltage of the input pair transistors in the amplification unit 11 increases, the drain voltage decreases, the gate voltage of the fourth transistor M4 decreases, and the gate-source voltage V GS4 increases, and the current I1 flowing through the fourth transistor M4 increases; since the current copied by the folded current mirror structure is constant, the current I3 flowing through the first transistor M1 is constant, that is, the sum I3 of the current I1 flowing through the fourth transistor M4 and the current I2 flowing through the second transistor M2 is fixed. When I1 increases, the current I2 flowing through the second transistor M2 decreases. Therefore, the current I4 on the first resistor R1 decreases, and the gate-source voltage V of the third transistor M3 GS3 also decreases, and the channel opened by the third transistor M3 becomes smaller, resulting in a decrease in the output voltage V OUT . When the output voltage V OUT rises rapidly, the fast response loop can use the characteristics of the circuit itself to regulate the current and then regulate the voltage, effectively canceling the influence of the rapid rise of the output voltage V OUT , reducing the common-mode noise. Similarly, when the output voltage VOUT During a rapid drop, the output voltage V can also be effectively canceled through the fast response loop. OUT the impact of the rapid drop.

[0042] As an example, the first capacitor C1 and the second capacitor C2 include on-chip compensation capacitors in the picofarad (pF) range.

[0043] Specifically, the current flowing through each transistor is expressed as follows: (1) where I represents the current flowing through the transistor; μ represents the electron mobility, with the unit of cm² / V·s, reflecting the movement ability of carriers in the channel; Cox represents the gate oxide capacitance per unit area, with the unit of F / cm²; W represents the width of the transistor; L represents the length of the transistor; V GS represents the gate-source voltage of the transistor, that is, the voltage difference between the gate and the source of the transistor; V th represents the threshold voltage of the transistor itself.

[0044] The output voltage is expressed as follows: (2) The operational amplifier gain of the linear voltage regulator circuit is expressed as follows: (3) where AV represents the operational amplifier gain, gmN represents the transconductance parameter of the input pair transistors, ron represents the on-resistance of the NMOS transistor in the current mirror, rop represents the on-resistance of the PMOS transistor in the current mirror.

[0045] In an embodiment of the present application, the gain bandwidth of the voltage feedback slow loop is approximately 160KHz to maintain the stability of the output DC voltage value, and the gain bandwidth product of the fast response loop is approximately 250MHz to achieve the fast response of the linear voltage regulator circuit and avoid the interference of common-mode noise.

[0046] Please refer to Figure 3 , Figure 3 represents the load current I of the traditional linear voltage regulator circuit DC when switching between 0 - 10mA, the transient response curve is obtained by switching the current source DC between 0 - 10mA and detecting the load current I DC to test the stability of the linear voltage regulator circuit. From Figure 3 it can be obtained that in the traditional linear voltage regulator circuit, when the load current I DC rises from 0 to 10mA within 1us, the output voltage V OUTAn undershoot of approximately 70 mV occurred and the voltage recovered to a stable voltage of 1.8 V after 0.6 μs.

[0047] Please refer to Figure 4 , Figure 4 which represents the load current I of the traditional linear voltage regulator circuit DC for the transient response curve during the switching from 10 mA to 0. When the load current I DC decreases from 10 mA to 0 within 1 μs, the output voltage V OUT generated an overcharge voltage of approximately 160 mV and recovered to a stable voltage of 1.8 V after 0.7 μs.

[0048] Furthermore, please refer to Figure 5 , Figure 5 which represents the frequency characteristics of the fast response loop of the linear voltage regulator circuit provided by this application. When simulating a circuit with multiple loops, in order to accurately analyze the frequency characteristics of the loops, different loop ports need to be opened and their frequency characteristics analyzed separately. For the linear voltage regulator circuit provided by this application, during the simulation of the fast loop, the first end of the fourth transistor M4 needs to be set to an AC open circuit, and then an excitation signal is applied to the first end of the second transistor M2. The obtained simulation results represent the frequency characteristics of the fast response loop.

[0049] Please refer to Figure 6 , Figure 6 which represents the frequency characteristics of the voltage feedback slow loop of the linear voltage regulator circuit provided by this application. When simulating the voltage feedback slow loop, the first end of the second transistor M2 needs to be set to an AC open circuit, and then an excitation signal is applied to the first end of the fourth transistor M4. The obtained simulation results represent the frequency characteristics of the voltage feedback slow loop.

[0050] Please refer to Figure 7 , Figure 7 which represents the overall frequency characteristics of the linear voltage regulator circuit provided by this application. When simulating the frequency characteristics of the overall linear voltage regulator circuit, the first end of the fourth transistor M4 is disconnected and an excitation signal is applied. The obtained simulation results represent the overall frequency characteristics of the linear voltage regulator circuit.

[0051] Please continue to refer to Figures 5 - 7 , and it is obtained that the bandwidth of the fast response loop of the linear voltage regulator circuit provided by this application is 250 MHz, the phase margin is 57°, the bandwidth of the voltage feedback slow loop is 160 kHz, the phase margin is 80°, the bandwidth of the overall linear voltage regulator circuit is 460 kHz and the phase margin is 82°. During the fast jump of the output voltage V OUT the fast response loop can respond more effectively to voltage disturbances.

[0052] Please refer toFigure 8 , Figure 8 represents the power supply rejection ratio (PSRR) characteristic of the linear voltage regulator circuit provided by the present application. The linear voltage regulator circuit provided by the present application has a PSRR of 130 dB at low frequencies and also has a PSRR of 38 dB at a high frequency of 1 MHz. It has a good suppression effect on the noise of the power supply voltage at both low and high frequencies.

[0053] As an example, for the topological deformation of the operational amplifier in the amplification unit 11 of the linear voltage regulator circuit provided by the present application, such as using PMOS as the input pair transistors, but still without departing from the principle of achieving the stability of the circuit through a fast response loop and a slow voltage feedback loop, it also belongs to the protection scope of the present application.

[0054] As an example, the fast response loop and the slow voltage feedback loop of the linear voltage regulator circuit provided by the present application are applicable to various topological structures, such as digital isolators, high-frequency drive circuits, high-frequency DC-DC circuits, etc., not limited to the situations proposed in the present application.

[0055] In the present application, under the conventional monolithic integration process technology, a fast response loop of the linear voltage regulator circuit is designed. A capacitor is used to quickly couple the signal with a voltage drop to a transistor, and the voltage is further regulated by controlling the current flowing through the transistor, reducing the common-mode noise interference. Without relying on a large off-chip load capacitor, only a picoFarad-level on-chip compensation capacitor is built-in, and faster transient response can be achieved when the output voltage V OUT changes rapidly due to a rapid change in the GND voltage. The current is regulated by using the characteristics of the circuit itself to further regulate the voltage, effectively canceling the common-mode noise. The linear voltage regulator circuit provided by the present application has an excellent low-frequency power supply rejection ratio (about 130 dB), and the power supply rejection ratio is still up to 38 dB at a high frequency of 1 MHz, still being able to effectively reduce the common-mode noise interference generated by the power supply voltage.

[0056] Although the present application has been disclosed as above by way of embodiments, it is not intended to limit the present application. Any person with ordinary knowledge in the technical field to which the present application pertains, without departing from the spirit and scope of the present application, may make some modifications and refinements. Therefore, the protection scope of the present application shall be subject to that defined by the appended patent application scope.

Claims

1. A linear voltage regulator circuit, characterized in that including an amplifying unit, a voltage regulating unit and a voltage dividing unit, which are connected in sequence; wherein, the voltage regulating unit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor and a first resistor; a first terminal of the first resistor is connected to a second terminal of the second transistor and a first terminal of the third transistor, a third terminal of the second transistor is connected to a second terminal of the fourth transistor, a first terminal of the second capacitor and a second terminal of the first transistor, a first terminal of the fourth transistor is connected to a first terminal of the first capacitor, a third terminal of the fourth transistor is connected to a second terminal of the second capacitor and a third terminal of the third transistor, and a third terminal of the first transistor is connected to a second terminal of the first capacitor.

2. The linear voltage regulator circuit according to claim 1, wherein The amplifying unit includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a fifteenth transistor; The first terminals of the fifth transistor and the sixth transistor, the seventh transistor and the eighth transistor, the ninth transistor and the tenth transistor, and the eleventh transistor and the twelfth transistor are respectively connected, a second terminal of the fifth transistor is connected to a second terminal of the sixth transistor, a third terminal of the fifth transistor is connected to a second terminal of the seventh transistor, a third terminal of the sixth transistor is connected to a second terminal of the eighth transistor, a third terminal of the seventh transistor is respectively connected to a third terminal of the ninth transistor, a first terminal of the eleventh transistor and a first terminal of the twelfth transistor, a third terminal of the eighth transistor is connected to a third terminal of the tenth transistor, a second terminal of the ninth transistor is connected to a third terminal of the eleventh transistor, a second terminal of the tenth transistor is connected to a third terminal of the twelfth transistor, and a second terminal of the eleventh transistor is connected to a second terminal of the twelfth transistor; a first terminal of the fourteenth transistor is connected to a reference voltage, a second terminal of the thirteenth transistor is connected to a second terminal of the fourteenth transistor, a third terminal of the thirteenth transistor is connected to a series midpoint of a third terminal of the sixth transistor and a second terminal of the eighth transistor, a third terminal of the fourteenth transistor is connected to a series midpoint of a third terminal of the fifth transistor and a second terminal of the seventh transistor, a first terminal of the fifteenth transistor is connected to a first terminal of the eleventh transistor, a second terminal of the fifteenth transistor is connected to a second terminal of the eleventh transistor, and a third terminal of the fifteenth transistor is connected to a series midpoint of a second terminal of the thirteenth transistor and a second terminal of the fourteenth transistor.

3. The linear voltage regulator circuit according to claim 2, characterized in that, A second terminal of the first resistor is connected to a second terminal of the sixth transistor, a first terminal of the fourth transistor is connected to a series midpoint of a third terminal of the eighth transistor and a third terminal of the tenth transistor, a first terminal of the second transistor is connected to a first terminal of the tenth transistor, a first terminal of the first transistor is connected to a first terminal of the twelfth transistor, and a second terminal of the first capacitor is connected to a second terminal of the twelfth transistor.

4. The linear voltage regulator circuit according to claim 3, characterized in that, The voltage dividing unit includes: a second resistor, a third resistor, and a third capacitor; a first terminal of the second resistor is connected to a first terminal of the third capacitor, and a second terminal of the second resistor is connected to a first terminal of the third resistor and a second terminal of the third capacitor.

5. The linear voltage regulator circuit as claimed in claim 4, wherein, A first terminal of the second resistor is connected to a second terminal of the second capacitor, a second terminal of the third resistor is connected to a second terminal of the first transistor, a first terminal of the third resistor is connected to a first terminal of the thirteenth transistor, and a first terminal of the third capacitor is connected to an output voltage.

6. The linear voltage regulator circuit according to claim 1, wherein The third transistor and the fourth transistor are PMOS transistors, and the first transistor and the second transistor are NMOS transistors.

7. The linear voltage regulator circuit according to claim 2, wherein The thirteenth transistor and the fourteenth transistor are NMOS transistors.

8. The linear voltage regulator circuit according to claim 2, characterized in that, The thirteenth transistor and the fourteenth transistor are PMOS transistors.

9. The linear voltage regulator circuit according to claim 2, characterized in that, The fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are PMOS transistors, and the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor are NMOS transistors.

10. The linear voltage regulator circuit according to claim 1, characterized in that, The orders of magnitude of the first capacitor and the second capacitor include picofarads.

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