Data bit width conversion method and first-in first-out buffer

Abstract

The invention provides a data bit width conversion method and a first-in first-out buffer, and belongs to the technical field of data processing. According to the method, when the write enable frequency is matched with the protocol type of the first bit width data to be transmitted, the read enable is triggered (namely, the start of reading the data is triggered), and the target frequency (namely the number of the read data) of the read enable is determined based on the write enable frequency, the first bit width and the second bit width, so that the written data can be accurately read; the area of the first-in first-out buffer can be reduced, the problem that bubbles exist between output data is solved, and certain universality is achieved.

Description

Technical Field

[0001] This application relates to the technical field of data processing, and in particular, to a data bit-width conversion method and a first-in-first-out buffer. Background Art

[0002] According to the UCIE (Universal Chiplet Interconnect Express) Spec (Specification) protocol, the CTRL (Controller Layer) and PHY (Physical Layer) of UCIE mainly consist of a mainband channel and a sideband channel. Among them, the mainband mainly conducts data information interaction between the local die and the remote die, and the sideband mainly conducts interaction such as link training information, remote die register access, and link management information between dies.

[0003] Due to limitations such as the area of a single die, the frequency between the CTRL and PHY, and the mismatch of the data bit-width of the sideband channel between the CTRL and PHY, according to actual needs, corresponding asynchronous / synchronous fifos (first-in-first-out buffers) need to be added to the sideband channel between dies. However, traditional fifos can only implement the first-in-first-out function. When there is a certain difference in the read and write bandwidths, there will be a bubble problem between the output data. Moreover, since the fifo needs to generate status signals such as "empty" and "full", it also has the problem of large area. That is, the existing fifo design cannot meet the actual use of the UCIE sideband channel. Summary of the Invention

[0004] The main purpose of the embodiments of this application is to propose a data bit-width conversion method and a first-in-first-out buffer, aiming to trigger the read enable (i.e., trigger the start of reading data) when the number of write enable times matches the protocol type of the first bit-width data to be transmitted, and determine the target number of read enables (i.e., the number of read data) based on the number of write enable times, the first bit-width, and the second bit-width, which can reduce the area of the first-in-first-out buffer, solve the problem of bubbles between the output data after the fifo performs bit-width conversion, and has a certain generality and can be applicable to data transmission between DS die (downstream chiplet) and US die (upstream chiplet).

[0005] To achieve the above object, the first aspect of the embodiments of this application proposes a data bit-width conversion method, which is applied to data transmission in the sideband channel of a universal chiplet interconnect technology system, including:

[0006] Write the first-bit-width data to be transmitted and record the write enable count;

[0007] When the write enable count matches the protocol type corresponding to the first-bit-width data to be transmitted, trigger a read enable to read out data according to a preset second-bit-width, where different protocol types include a continuous corresponding number of first-bit-width data, and one write enable can write one first-bit-width data;

[0008] Determine the target count of the read enable according to the write enable count, the first-bit-width, and the second-bit-width, where one read enable can read out one second-bit-width data;

[0009] Record the read enable count, and when the read enable count reaches the target count, control the read enable to close to stop reading out data.

[0010] In an embodiment of the present application, before writing the first-bit-width data to be transmitted, the method further includes:

[0011] Receive a transmission request and parse the transmission request to determine the protocol type of the first-bit-width data to be transmitted.

[0012] In an embodiment of the present application, the determining the target count of the read enable according to the write enable count, the first-bit-width, and the second-bit-width includes:

[0013] Multiply the write enable count by the first-bit-width and then divide by the second-bit-width to obtain the target count of the read enable.

[0014] In an embodiment of the present application, after controlling the read enable to close to stop reading out data, the method further includes:

[0015] Reset the write enable count and the read enable count to zero.

[0016] In an embodiment of the present application, after controlling the read enable to close to stop reading out data, the method further includes:

[0017] Concatenate all the read second-bit-width data.

[0018] In an embodiment of the present application, the first-bit-width is greater than or equal to 1 bit and less than or equal to 64 bits, and the second-bit-width is greater than or equal to 1 bit and less than or equal to 64 bits.

[0019] In an embodiment of the present application, when the write enable count matches the protocol type corresponding to the first-bit-width data to be transmitted, the method further includes:

[0020] Control the write enable to close to stop writing data.

[0021] To achieve the above object, a second aspect of the embodiments of the present application proposes a first-in first-out buffer, which is applied to data transmission of a sideband channel in a general chiplet interconnection technology system, and includes a buffer unit, a protocol parsing unit, a read / write enable logic unit, a write counting unit, a read counting unit, a write data unit, and a read data unit. Among them, the buffer unit, the protocol parsing unit, the write counting unit, the read counting unit, the write data unit, and the read data unit are all connected to the read / write enable logic unit;

[0022] The write data unit is used to write the first bit-width data to be transmitted into the buffer unit;

[0023] The buffer unit is used to cache the written first bit-width data;

[0024] The protocol parsing unit is used to parse the transmission request to determine the protocol type of the first bit-width data to be transmitted;

[0025] The write counting unit is used to record the number of write enables;

[0026] The read counting unit is used to record the number of read enables;

[0027] The read data unit is used to read data from the buffer unit according to a preset second bit-width;

[0028] The read / write enable logic unit is used to perform the following steps:

[0029] Obtain the number of write enables recorded by the write counting unit, and when the number of write enables matches the protocol type corresponding to the first bit-width data to be transmitted, trigger a read enable, so that the read data unit reads data from the buffer unit according to a preset second bit-width. Among them, different protocol types contain a continuous corresponding number of first bit-width data, and one write enable can write one first bit-width data;

[0030] Determine the target number of read enables according to the number of write enables, the first bit-width, and the second bit-width, where one read enable can read one second bit-width data;

[0031] Obtain the number of read enables recorded by the read counting unit, and when the number of read enables reaches the target number, control the read enable to close, so that the read data unit stops reading data from the buffer unit.

[0032] In an embodiment of the present application, the read / write enable logic unit is further used for:

[0033] When the number of write enables matches the protocol type corresponding to the first bit-width data to be transmitted, control the write enable to close so that the write data unit stops writing data to the buffer unit.

[0034] In one embodiment of the present application, the read / write enable logic unit is further configured to:

[0035] After controlling the read enable to be turned off to stop reading data, control the write count unit to reset the write enable count to zero, and control the read count unit to reset the read enable count to zero.

[0036] The present application provides a data bit-width conversion method, which is applied to the data transmission of the sideband channel in the general chiplet interconnection technology system. The method first writes the first bit-width data to be transmitted and records the number of write enables. When the number of write enables matches the protocol type corresponding to the first bit-width data to be transmitted, the read enable is triggered to read the data according to the preset second bit-width. According to the number of write enables, the first bit-width, and the second bit-width, the target number of read enables can be determined. Here, one write enable can write one first bit-width data, and one read enable can read one second bit-width data. Thus, when the number of read enables reaches the target number, it can be determined that the reading is completed, and the data reading is stopped. By triggering the read enable (i.e., triggering the start of reading data) when the number of write enables matches the protocol type, and determining the target number of read enables (i.e., the number of read data) based on the number of write enables, the first bit-width, and the second bit-width, it can be ensured that the written data is accurately read, the area of the first-in-first-out buffer can be reduced, the problem of bubbles existing between the output data can be solved, it has a certain generality, and it can be applied to the data transmission between the DS die (downstream chiplet) and the US die (upstream chiplet). Description of the Drawings

[0037] Figure 1 is a schematic diagram of data transmission in the UCIE system.

[0038] Figure 2 is a schematic diagram of the first-in-first-out buffer provided by the embodiment of the present application.

[0039] Figure 3 is a flowchart of the steps executed by the read / write enable logic unit provided by the embodiment of the present application.

[0040] Figure 4 is a flowchart of the steps of the data bit-width conversion method provided by an embodiment of the present application. Detailed Embodiments

[0041] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0042] It should be noted that although the functional modules are divided in the device schematic diagram and the logical sequence is shown in the flowchart, in some cases, the steps shown or described can be executed in a different module division in the device or a different sequence in the flowchart. Terms such as "first", "second", etc. in the specification, claims, and the above-mentioned drawings are used to distinguish similar objects and do not necessarily describe a specific order or sequence.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0044] Refer to Figure 1 , according to the UCIE (Universal Chiplet Interconnect Express) Spec (specification) protocol, the CTRL (controller layer) of UCIE and the PHY (physical layer) of UCIE are mainly composed of a mainband channel and a sideband channel. Among them, the mainband mainly performs data information interaction between the local die and the remote die, and the sideband mainly performs interactions such as link training information, remote die register access, and link management information between die and die.

[0045] Due to limitations such as the area of a single die, the frequency between the CTRL and the PHY, and the data bit width mismatch of the sideband channel between the CTRL and the PHY, according to actual needs, corresponding asynchronous / synchronous fifos (first-in-first-out buffers) need to be added to the sideband channel between die and die, as Figure 1 shown, a 32-bit to 8-bit fifo and an 8-bit to 32-bit fifo are respectively added to each die. However, traditional fifos can only implement the first-in-first-out function. When there is a certain difference in the read and write bandwidths, there will be a bubble problem between the output data, and due to the need for the fifo to generate status signals such as "empty" and "full", it also has the problem of large area. That is, the existing fifo design cannot meet the actual use of the UCIE sideband channel.

[0046] Based on this, an embodiment of the present application proposes a data bit-width conversion method, aiming to trigger a read enable (i.e., trigger the start of reading data) when the number of write enables matches the protocol type of the first bit-width data to be transmitted, and determine the target number of read enables (i.e., the number of data read out) based on the number of write enables, the first bit-width, and the second bit-width, which can reduce the area of the first-in first-out buffer, solve the problem that there are (bubbles) between the data output after the fifo bit-width conversion, and has a certain generality.

[0047] Refer to Figure 2 and Figure 3 , Figure 2 is a schematic diagram of the first-in first-out buffer provided by an embodiment of the present application. Figure 3 is a flowchart of steps executed by the read / write enable logic unit provided by an embodiment of the present application. An embodiment of the present application provides an improved first-in first-out buffer, which is applied to the data transmission of the sideband channel in the general die interconnect technology system. That is, it is set in the sideband channel of the general die interconnect technology system. The first-in first-out buffer includes a buffer unit 210, a protocol parsing unit 220, a read / write enable logic unit 230, a write counting unit 240, a read counting unit 250, a write data unit 260, and a read data unit 270. Among them, the buffer unit 210, the protocol parsing unit 220, the write counting unit 240, the read counting unit 250, the write data unit 260, and the read data unit 270 are all connected to the read / write enable logic unit 230. Among them:

[0048] The write data unit 260 is used to write the first bit-width data to be transmitted into the buffer unit 210.

[0049] The buffer unit 210 is used to cache the written first bit-width data.

[0050] The protocol parsing unit 220 is used to parse the transmission request to determine the protocol type of the first bit-width data to be transmitted.

[0051] The write counting unit 240 is used to record the number of write enables, that is, to record the number of data written into the buffer unit 210. Among them, one write enable can write one first bit-width data. Taking the first bit-width as 8bit, the second bit-width as 32bit, and the first bit-width data to be transmitted as 16 consecutive 8bit data of the register access type as an example, one write enable can write 1 8bit data. When the number of write enables is 16, it means that the number of data written into the buffer unit 210 is 16. At this time, the data writing is completed. That is, the number of write enables is equal to the number of data written into the buffer unit 210.

[0052] The read count unit 250 is used to record the number of read enable times, that is, to record the number of data read from the cache unit 210. Among them, one read enable can read out one data with the second bit width. Taking the first bit width as 8 bits, the second bit width as 32 bits, and the first-bit-width data to be transmitted as 16 consecutive 8-bit data of the register access type as an example, one read enable can read out 1 32-bit data. When the number of read enable times is 4, it means that the number of data read from the cache unit 210 is 4. At this time, the data reading is completed. That is, the number of read enable times is equal to the number of data read from the cache unit 210.

[0053] The read data unit 270 is used to read data from the cache unit 210 according to the preset second bit width.

[0054] Refer to Figure 3 , the read-write enable logic unit 230 is used to execute the following steps S310 to S330:

[0055] Step S310, obtain the number of write enable times recorded by the write count unit, and when the number of write enable times matches the protocol type corresponding to the first-bit-width data to be transmitted, trigger a read enable so that the read data unit reads data from the cache unit according to the preset second bit width, where different protocol types include consecutive corresponding numbers of first-bit-width data.

[0056] In the embodiment of the present application, the read / write enable logic unit 230 is connected to the write count unit 240, so that the read / write enable logic unit 230 can obtain the number of write enable times recorded by the write count unit 240 to obtain the number of data written into the cache unit 210. And when the number of write enable times matches the protocol type corresponding to the first bit width data to be transmitted, the read enable is triggered, so that the read data unit reads out data from the cache unit according to the preset second bit width. Taking the first bit width data to be transmitted as 4 consecutive 32-bit data in the register access request format as an example, since one write enable can write 1 32-bit data, when the number of write enable times is 4, it means that the number of write enable times matches the protocol type corresponding to the first bit width data to be transmitted. At this time, it means that the data writing is completed, and the read enable can be triggered to read out data from the cache unit according to the preset second bit width. Taking the first bit width data to be transmitted as 2 consecutive 32-bit data in the message format without data as an example, since one write enable can write 1 32-bit data, when the number of write enable times is 2, it means that the number of write enable times matches the protocol type corresponding to the first bit width data to be transmitted. At this time, it means that the data writing is completed, and the read enable can be triggered to read out data from the cache unit according to the preset second bit width. Taking the first bit width data to be transmitted as 16 consecutive 8-bit data in the register access type as an example, since one write enable can write 1 8-bit data, when the number of write enable times is 16, it means that the number of write enable times matches the protocol type corresponding to the first bit width data to be transmitted. At this time, it means that the data writing is completed, and the read enable can be triggered to read out data from the cache unit according to the preset second bit width.

[0057] Step S320, determine the target number of read enables according to the number of write enables, the first bit width, and the second bit width, where one read enable reads out one second bit width data.

[0058] In this step, the read / write enable logic unit 230 can also determine the target number of read enables according to the number of write enables, the first bit width, and the second bit width. Here, one read enable reads out one data with the second bit width, and the product of the number of write enables and the first bit width is equal to the product of the number of read enables and the second bit width. The number of write enables represents the number of data written into the cache unit 210, and the number of read enables represents the number of data read out from the cache unit 210. That is, multiplying the number of write enables by the first bit width and then dividing by the second bit width can obtain the target number of read enables. Taking the first bit width of 32 bit, the second bit width of 8 bit, and the continuous 4 32-bit data in the register access request format of the first bit width data to be transmitted as an example, when the number of 32-bit data written is 4, it indicates that the number of write enables matches the protocol type corresponding to the first bit width data to be transmitted. At this time, it indicates that the data writing is completed, and the read enable can be triggered to read out the data from the cache unit 210 according to the preset second bit width. Since the second bit width is 8 bit, the target number of read enables can be calculated as 4×32÷8 = 16. That is, one read enable can read out 1 8-bit data, and 16 read enables are required to read out the continuous 4 32-bit data written in the form of 8 bit.

[0059] Step S330: Obtain the number of read enables recorded by the read count unit, and when the number of read enables reaches the target number, control the read enable to turn off to control the read data unit to stop reading data from the cache unit.

[0060] In this step, the read / write enable logic unit 230 is connected to the read count unit 250. Thus, after the read / write enable logic unit 230 calculates the target number of read enables, it can obtain the number of read enables recorded by the read count unit 250. When the number of read enables reaches the target number, it indicates that all the data written into the cache unit 210 has been read out. At this time, it is necessary to control the read enable to turn off to control the read data unit 270 to stop reading data from the cache unit 210.

[0061] In the embodiments of the present application, the full state (i.e., full write) is characterized by matching the write enable count with the protocol type corresponding to the first bit-width data to be transmitted. There is no need to additionally set up a state circuit to generate a full state signal, which can reduce the area of the first-in first-out buffer. The empty state (i.e., the data cached in the cache unit 210 is empty) is characterized by the read enable count reaching the target count. There is no need to additionally set up a state circuit to generate an empty state signal, which can reduce the area of the first-in first-out buffer. By triggering the read enable (i.e., triggering the start of reading data) when the write enable count matches the protocol type of the first bit-width data to be transmitted, and determining the target count of the read enable (i.e., the number of data read out) based on the write enable count, the first bit-width, and the second bit-width, the area of the first-in first-out buffer can be reduced, the problem of (bubbles) between the output data after the FIFO bit-width conversion can be solved, and it has a certain generality and can be applied to data transmission between DS die (downstream die) and US die (upstream die).

[0062] In some embodiments, the read / write enable logic unit 230 can also be used to control the write enable to turn off when the number of data written into the cache unit 210 (i.e., the write enable count) matches the protocol type corresponding to the first bit-width data to be transmitted, so as to control the write data unit 260 to stop writing data into the cache unit 210. That is, when the write enable count matches the protocol type corresponding to the first bit-width data to be transmitted, it indicates that the data writing is completed. At this time, controlling the write enable to turn off can control the write data unit 260 to stop writing data into the cache unit 210.

[0063] In some embodiments, the read / write enable logic unit 230 can also be used to control the write count unit 240 to reset the write enable count to zero and control the read count unit 250 to reset the read enable count to zero after controlling the read enable to turn off to stop reading data, that is, after the read enable count reaches the target count. This is convenient for subsequent data transmission and bit-width conversion.

[0064] Refer to Figure 4 , Figure 4 is a flowchart of the steps of a data bit-width conversion method provided by an embodiment of the present application. This method is applied to data transmission in the sideband channel of a general die interconnection technology system and is executed based on a first-in first-out buffer provided in the sideband channel of the general die interconnection technology system. This method includes but is not limited to steps S410 to S440.

[0065] Step S410, write the first bit-width data to be transmitted and record the write enable count.

[0066] In the embodiments of the present application, according to the protocol type transmitted by the sideband channel, in accordance with the UCIE Spec protocol, the information types transmitted by the sideband channel include two types: register access related and Message related. When data is transmitted, it may involve transmitting data from the CTRL (controller layer) of UCIE to the PHY (physical layer) of UCIE, or transmitting data from the PHY (physical layer) of UCIE to the CTRL (controller layer) of UCIE. Taking the transmission of data from the CTRL (controller layer) of UCIE to the PHY (physical layer) of UCIE as an example, when the CTRL (controller layer) of UCIE transmits data to the PHY (physical layer) of UCIE, it will first send a transmission request to the PHY (physical layer) through the sideband channel. At this time, the protocol parsing unit 220 in the first-in first-out buffer added to the sideband channel can first parse the transmission request to determine the protocol type corresponding to the first bit-width data to be transmitted. Among them, different protocol types contain consecutive corresponding numbers of the first bit-width data. Taking the first bit-width data to be transmitted as 32-bit data as an example, its corresponding protocol types include the first type (4 consecutive 32-bit data in the register access request format), the second type (4 consecutive 32-bit data in the register access completion format), the third type (2 consecutive 32-bit data in the message format without data), and the fourth type (4 consecutive 32-bit data in the message format with data payload). Taking the first bit-width data to be transmitted as 8-bit data as an example, its corresponding protocol types include the first type (16 consecutive 8-bit data in the register access type) and the second type (8 consecutive 8-bit data in the register access type). Then, the write data unit 260 writes the first bit-width data to be transmitted into the buffer unit 210 of the first-in first-out buffer, and records the write enable times through the write counting unit 240, that is, records the number of data written into the buffer unit 210. Taking the 4 consecutive 32-bit data in the register access request format as the first bit-width data to be transmitted as an example, first write the 4 consecutive 32-bit data in the register access request format into the buffer unit 210 for caching, and at the same time record the number of 32-bit data written into the buffer unit 210. It should be noted that during the data transmission process, a transmission request sent by the CTRL (controller layer) of UCIE to the PHY (physical layer) of UCIE can only correspond to transmitting one type of data. For example, based on the current transmission request, the CTRL (controller layer) of UCIE transmits data of the first type (4 consecutive 32-bit data in the register access request format) to the PHY (physical layer) of UCIE through the sideband channel. After the transmission is completed, a transmission request needs to be sent again to then transmit the next protocol type (such as transmitting 4 consecutive 32-bit data in the register access completion format).

[0067] Step S420: When the write enable count matches the protocol type corresponding to the first-width data to be transmitted, trigger a read enable to read out data according to a preset second width. Different protocol types include a continuous corresponding number of first-width data, and one write enable can write one first-width data.

[0068] In the embodiment of the present application, when the write enable count matches the protocol type corresponding to the first-width data to be transmitted, the read / write enable logic unit 230 triggers a read enable to read out data from the buffer unit 210 according to a preset second width. At the same time, when the write enable count matches the protocol type corresponding to the first-width data to be transmitted, the read / write enable logic unit 230 controls the write enable to be turned off to control the write data unit 260 to stop writing data into the buffer unit 210. Taking the continuous 4 32-bit data in the register access request format as the first-width data to be transmitted as an example, when the number of 32-bit data written is 4 (i.e., the write enable count is 4), it indicates that the write enable count matches the protocol type corresponding to the first-width data to be transmitted. At this time, it indicates that the data writing is completed, and the read enable can be triggered to enable the read data unit 260 to read out data from the buffer unit according to a preset second width. At the same time, control the write enable to be turned off to make the write data unit 260 stop writing data into the buffer unit 210. Taking the continuous 2 32-bit data in the message format without data as the first-width data to be transmitted as an example, when the number of 32-bit data written is 2 (i.e., the write enable count is 2), it indicates that the write enable count matches the protocol type corresponding to the first-width data to be transmitted. At this time, it indicates that the data writing is completed, and the read enable can be triggered to read out data from the buffer unit according to a preset second width. At the same time, control the write enable to be turned off to make the write data unit 260 stop writing data into the buffer unit 210. Taking the continuous 16 8-bit data in the register access type as the first-width data to be transmitted as an example, when the number of 8-bit data written is 16 (i.e., the write enable count is 16), it indicates that the write enable count matches the protocol type corresponding to the first-width data to be transmitted. At this time, it indicates that the data writing is completed, and the read enable can be triggered to read out data from the buffer unit according to a preset second width. At the same time, control the write enable to be turned off to make the write data unit 260 stop writing data into the buffer unit 210. In the embodiment of the present application, the full state (i.e., full write) is characterized by the write enable count matching the protocol type corresponding to the first-width data to be transmitted, without the need to additionally set a state circuit to generate a full state signal, which can reduce the area of the buffer unit.

[0069] Step S430: Determine the target count of the read enable according to the write enable count, the first width, and the second width, where one read enable can read out one second-width data.

[0070] In the embodiment of the present application, after the read / write enable logic unit 230 triggers a read enable to cause the read data unit 270 to read data from the buffer unit 210 according to a preset second bit width, it can further determine the target number of read enables according to the number of write enables, the first bit width, and the second bit width. One read enable can read one second-bit-width data. The number of read enables represents the number of data read from the buffer unit 210, and the product of the number of write enables and the first bit width is equal to the product of the number of read enables and the second bit width. That is, multiplying the number of write enables by the first bit width and then dividing by the second bit width can obtain the target number of read enables. Taking the first bit width as 32 bit, the second bit width as 8 bit, and the first-bit-width data to be transmitted as 4 consecutive 32-bit data in the register access request format as an example, when the number of 32-bit data written is 4 (i.e., the number of write enables is 4), it indicates that the number of write enables matches the protocol type corresponding to the first-bit-width data to be transmitted. At this time, it indicates that the data writing is completed, and the read / write enable logic unit 230 triggers a read enable to cause the read data unit 270 to read data from the buffer unit 210 according to the preset second bit width. Since the second bit width is 8 bit, the target number of read enables can be calculated as 4×32÷8 = 16, that is, one read enable can read 1 8-bit data, and it needs to be read enabled 16 times to read the 4 consecutive 32-bit data written in the form of 8 bit. Similarly, taking the first bit width as 8 bit, the second bit width as 32 bit, and the first-bit-width data to be transmitted as 16 consecutive 8-bit data of the register access type as an example, when the number of 8-bit data written is 16 (i.e., the number of write enables is 16), it indicates that the number of write enables matches the protocol type corresponding to the first-bit-width data to be transmitted. At this time, it indicates that the data writing is completed, and the read / write enable logic unit 230 triggers a read enable to cause the read data unit 270 to read data from the buffer unit 210 according to the preset second bit width. Since the second bit width is 32 bit, the target number of read enables can be calculated as 16×8÷32 = 4, that is, one read enable can read 1 32-bit data, and it needs to be read enabled 4 times to read the 16 consecutive 8-bit data written in the form of 32 bit.

[0071] Step S440, record the number of read enables, and when the number of read enables reaches the target number, control the read enable to be turned off to stop reading data.

[0072] In the embodiment of the present application, after determining the target number of read enables according to the number of write enables, the first bit width, and the second bit width, when the number of read enables reaches the target number, it indicates that all the data written into the cache unit 210 has been read out. At this time, the read enable is controlled to be in the off state, so that the read data unit 270 stops reading data from the cache unit 210. Exemplarily, taking the first bit width as 32 bits, the second bit width as 8 bits, and the first-bit-width data to be transmitted being 4 consecutive 32-bit data in the register access request format as an example, when the number of 32-bit data written is 4 (i.e., the number of write enables is 4), it indicates that the number of write enables matches the protocol type corresponding to the first-bit-width data to be transmitted. At this time, it indicates that the data writing is completed, and the read / write enable logic unit 230 triggers the read enable, so that the read data unit 270 reads data from the cache unit 210 according to the preset second bit width. Since the second bit width is 8 bits, the target number of read enables can be calculated as 4×32÷8 = 16, that is, one read enable can read 1 8-bit data, and 16 read enables are required to read the 4 consecutive 32-bit data written in the form of 8 bits. That is, when the cumulative number of read enables reaches 16 times, it indicates that all the 4 32-bit data cached in the cache unit 210 has been read out. At this time, the read enable signal needs to be controlled to be in the off state to control the stop of reading data from the cache unit 210. Similarly, taking the first bit width as 8 bits, the second bit width as 32 bits, and the first-bit-width data to be transmitted being 16 consecutive 8-bit data of the register access type as an example, when the number of 8-bit data written is 16 (i.e., the number of write enables is 16), it indicates that the number of write enables matches the protocol type corresponding to the first-bit-width data to be transmitted. At this time, it indicates that the data writing is completed, and the read enable can be triggered to read data from the cache unit 210 according to the preset second bit width. Since the second bit width is 32 bits, the target number of read enables can be calculated as 16×8÷32 = 4, that is, one read enable can read 1 32-bit data, and 4 read enables are required to read the 16 consecutive 8-bit data written in the form of 32 bits. That is, when the cumulative number of read enables reaches 4 times, it indicates that all the 16 8-bit data cached in the cache unit 210 has been read out. At this time, the read enable signal needs to be controlled to be in the off state to control the stop of reading data from the cache unit 210.

[0073] In the embodiment of the present application, the empty state is characterized by the number of read enables reaching the target number (i.e., the data cached in the cache unit 210 is empty). There is no need to additionally set a status circuit to generate an empty state signal, which can reduce the area of the first-in first-out buffer.

[0074] In some embodiments, since only one type of data can be transmitted in response to one transmission request, after the read enable count reaches the target count and the control stops reading data from the cache unit 210, it is necessary to control the write count unit 240 to reset the write enable count to zero and control the read count unit 250 to reset the read enable count to zero, so as to facilitate the next data transmission and bit width conversion.

[0075] In some embodiments, after the read enable count reaches the target count and it is controlled to stop reading data from the cache unit 210, that is, after all the data cached in the cache unit 210 has been read out, at this time, all the read second-width data needs to be concatenated. Exemplarily, taking the first width as 32 bits, the second width as 8 bits, and the first-width data to be transmitted being 4 consecutive 32-bit data in the register access request format as an example, when the number of 32-bit data written is 4 (i.e., the write enable count is 4), it indicates that the write enable count matches the protocol type corresponding to the first-width data to be transmitted. At this time, it indicates that the data writing is completed, and the read enable can be triggered to read data from the cache unit 210 according to the preset second width. Since the second width is 8 bits, the target read enable count can be calculated as 4×32÷8 = 16, that is, one read enable can read out 1 8-bit data, and it is necessary to perform 16 read enables to read out the 4 consecutive 32-bit data written in the form of 8 bits. That is, when the accumulated read enable count reaches 16 times, it indicates that all the 4 32-bit data cached in the cache unit 210 has been read out. At this time, it is necessary to control the read enable signal to the off state to control the stop of reading data from the cache unit 210. At this time, through 16 read enables, each read enable reads out 1 8-bit data, so a total of 16 consecutive 8-bit data are read out, and the 16 consecutive 8-bit data read out need to be concatenated to obtain the data corresponding to the 4 32-bit data written. Similarly, taking the first width as 8 bits, the second width as 32 bits, and the first-width data to be transmitted being 16 consecutive 8-bit data of the register access type as an example, when the number of 8-bit data written is 16 (i.e., the write enable count is 16), it indicates that the write enable count matches the protocol type corresponding to the first-width data to be transmitted. At this time, it indicates that the data writing is completed, and the read enable can be triggered to read data from the cache unit 210 according to the preset second width. Since the second width is 32 bits, the target read enable count can be calculated as 16×8÷32 = 4, that is, one read enable can read out 1 32-bit data, and it is necessary to perform 4 read enables to read out the 16 consecutive 8-bit data written in the form of 32 bits. That is, when the accumulated read enable count reaches 4 times, it indicates that all the 16 8-bit data cached in the cache unit 210 has been read out. At this time, it is necessary to control the read enable signal to the off state to control the stop of reading data from the cache unit 210. At this time, through 4 read enables, each read enable can read out 1 32-bit data, so a total of 4 consecutive 32-bit data are read out, and the 4 consecutive 32-bit data read out need to be concatenated to obtain the data corresponding to the 16 8-bit data written.

[0076] In some embodiments, according to the UCIE Spec protocol, the width of the first bit is greater than or equal to 1 bit and less than or equal to 64 bits, and the width of the second bit is greater than or equal to 1 bit and less than or equal to 64 bits. The data bit-width conversion method proposed in the embodiments of the present application is applicable to the mutual conversion between 1 bit and 64 bits.

[0077] The preferred embodiments of the embodiments of the present application have been described above with reference to the accompanying drawings, and thus do not limit the scope of the rights of the embodiments of the present application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall be within the scope of the rights of the embodiments of the present application.

Claims

1. A data bit-width conversion method is applied to data transmission in the sideband channel of a general chiplet interconnection technology system, characterized in that Including: Write the first-width data to be transmitted and record the write enable count; When the write enable count matches the protocol type corresponding to the first-width data to be transmitted, trigger a read enable to read out data according to a preset second width, where different protocol types include a continuous corresponding number of first-width data, and one write enable can write one first-width data; Determine the target count of the read enable according to the write enable count, the first width, and the second width, where one read enable can read out one second-width data; Record the read enable count, and when the read enable count reaches the target count, control the read enable to close to stop reading out data.

2. The method according to claim 1, characterized in that, Before writing the first-width data to be transmitted, the method further includes: Receive a transmission request and parse the transmission request to determine the protocol type of the first-width data to be transmitted.

3. The method according to claim 1, characterized in that The determining the target count of the read enable according to the write enable count, the first width, and the second width includes: Multiply the write enable count by the first width and then divide by the second width to obtain the target count of the read enable.

4. The method according to claim 1, wherein After controlling the read enable to close to stop reading out data, the method further includes: Reset the write enable count and the read enable count to zero.

5. The method according to claim 1 or 4, characterized in that, After controlling the read enable to close to stop reading out data, the method further includes: Concatenate all the read second-width data.

6. The method according to claim 1, wherein The first width is greater than or equal to 1 bit and less than or equal to 64 bits, and the second width is greater than or equal to 1 bit and less than or equal to 64 bits.

7. The method according to claim 1, characterized in that, When the write enable count matches the protocol type corresponding to the first-width data to be transmitted, the method further includes: Control the write enable to close to stop writing data.

8. A first-in-first-out buffer is applied to the data transmission of the sideband channel in a general chiplet interconnection technology system, and is characterized in that, Including a cache unit, a protocol parsing unit, a read / write enable logic unit, a write count unit, a read count unit, a write data unit, and a read data unit, where the cache unit, the protocol parsing unit, the write count unit, the read count unit, the write data unit, and the read data unit are all connected to the read / write enable logic unit; The write data unit is used to write the first-width data to be transmitted into the cache unit; The cache unit is used to cache the written first-width data; The protocol parsing unit is used to parse the transmission request to determine the protocol type of the first-width data to be transmitted; The write count unit is used to record the write enable count; The read count unit is used to record the read enable count; The read data unit is used to read out data from the cache unit according to a preset second width; The read / write enable logic unit is used to perform the following steps: Obtain the write enable count recorded by the write count unit, and when the write enable count matches the protocol type corresponding to the first-width data to be transmitted, trigger a read enable to enable the read data unit to read out data from the cache unit according to a preset second width, where different protocol types include a continuous corresponding number of first-width data, and one write enable can write one first-width data; Determine the target number of read enables according to the write enable count, the first bit width, and the second bit width, where one read enable can read out one data with the second bit width; Obtain the number of read enables recorded by the read count unit, and when the number of read enables reaches the target number, control the read enable to be turned off so that the read data unit stops reading data from the cache unit.

9. The first-in-first-out buffer according to claim 8, wherein, The read / write enable logic unit is further configured to: When the write enable count matches the protocol type corresponding to the first bit width data to be transmitted, control the write enable to be turned off so that the write data unit stops writing data to the cache unit.

10. The first-in first-out buffer according to claim 8, characterized in that, The read / write enable logic unit is further configured to: After controlling the read enable to be turned off to stop reading data, control the write count unit to reset the write enable count to zero and control the read count unit to reset the read enable count to zero.

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