An optimization method and an optimizer applied to X86 vector instruction translation

Abstract

The application provides an optimization method applied to X86 vector instruction translation, which is used for eliminating redundant instructions generated in the X86 vector instruction translation process, and the method comprises the following steps: obtaining the to-be-optimized code containing multiple instructions after translation processing, and performing the following steps: a mask optimization step: deleting redundant mask register setting instructions in the to-be-optimized code according to preset mask optimization rules to obtain mask optimization code; a vsetvli optimization step: deleting all csrr instructions and redundant vsetvli instructions in the mask optimization code according to preset instruction optimization rules to obtain target optimization code. The technical scheme of the application solves the problem of redundant instructions generated in the X86 vector instruction translation process through mask optimization and vsetvli optimization.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of binary translation, in particular to instruction optimization technology in the field of binary translation, and more particularly to an optimization method and an optimizer applied to X86 vector instruction translation. BACKGROUND

[0002] With the development of computer architecture, there are some different instruction set architectures. The vitality of an instruction set architecture lies in whether the ecosystem is perfect. Currently, the two major ecosystems are the Wintel ecosystem led by Windows and Intel, and the AA ecosystem led by Android and Arm. It is worth noting that neither the X86 nor the Arm instruction set architecture is an open source instruction set architecture, which brings technical barriers to the independent research and development of domestic processors. Under this background, the RISC-V instruction set architecture, which is flexible, open and simple, has become the best choice for the research and development of domestic processors. However, the key challenge faced by the RISC-V architecture is the immaturity of its ecosystem, which needs to be broken through by binary translation technology.

[0003] Vector instructions generally refer to instructions that can simultaneously perform the same operation on multiple data elements in computer architecture, thereby significantly improving the performance of the processor, reducing the number of instructions, and utilizing the parallelism of data. In the X86 architecture, vector instructions are mainly implemented through the SIMD (Single Instruction Multiple Data) technology. SIMD instructions perform the same operation on multiple data in turn, and these data are usually organized in a vector or array. X86 vector instructions have undergone four major stages of MMX, SSE, AVX, and AVX512 over time. Today, the X86 vector architecture has 32 512-bit vector registers. The X86 vector instructions and vector architecture provide powerful data parallel processing capabilities. In contrast, the RISC-V architecture adopts a modular vector extension scheme, supporting 128 / 256 / 512-bit configurable vector lengths, and its element bit width is dynamically set through the sew field of the vtype register, which is significantly different from the design of X86, which fixes the element bit width in the instruction opcode.

[0004] In order to break through the short board of RISC-V ecology, the dynamic binary translation technology can be used to convert X86 vector instructions into RISC-V instructions to realize the compatible running of existing X86 software on RISC-V hardware. In the field of binary translation, the translation strategy of vector instructions has a significant impact on the execution efficiency of the translated code. At present, there are two main vector instruction translation methods. One is to translate the vector instructions of the source architecture into scalar instructions of the target architecture. This method is simple to implement, does not need to deeply understand the vector instruction set of the target architecture, and can run on the target architecture that does not support vector instructions. However, this will reduce the execution efficiency of the translated code. The other method is to translate the vector instructions of the source architecture into the vector instructions of the target architecture. This method needs to have a deep understanding of the vector instruction sets of the two architectures. This method is not suitable for the target architecture that does not support vector instructions, but can fully utilize the resources of the target architecture and significantly improve the execution efficiency of the translated code.

[0005] Although the existing two translation methods can realize the translation from the X86 architecture to the RISC-V architecture, considering the execution efficiency of the translated code, the open source dynamic binary translator is usually used to translate the source X86 vector instructions into RISC-V vector instructions. However, the open source dynamic binary translator will generate some redundant setting instructions in the process of translating the source X86 vector instructions into RISC-V vector instructions, which will affect the execution efficiency of the translated code.

[0006] It should be noted that the background technology is only used to introduce the related information of the present application, so as to help understand the technical scheme of the present application, but does not mean that the related information must be prior art. In the absence of evidence that the related information has been disclosed before the filing date of the present application, the related information should not be regarded as prior art. SUMMARY

[0007] Therefore, the purpose of the present application is to overcome the defects of the prior art, and to provide an optimization method applied to X86 vector instruction translation and an optimizer.

[0008] The purpose of the present application is achieved by the following technical solutions.

[0009] According to a first aspect of the present application, an optimization method applied to X86 vector instruction translation is provided for eliminating redundant instructions generated in the X86 vector instruction translation process, the method comprising obtaining translated code containing a plurality of instructions to be optimized, and performing the following steps: a mask optimization step of deleting redundant mask register setting instructions in the code to be optimized according to a preset mask optimization rule to obtain mask optimized code; a vsetvli optimization step of deleting all csrr instructions and redundant vsetvli instructions in the mask optimized code according to a preset instruction optimization rule to obtain target optimized code.

[0010] In some embodiments of the present application, the preset mask optimization rule is to replace all mask register setting instructions in the code to be optimized with pseudo-instructions according to a known instruction manual, and to set a high-bit identifier and a low-bit identifier in the pseudo-instructions to mark the usage state of the mask register when the corresponding pseudo-instruction is executed; wherein the code to be optimized includes a plurality of sequentially arranged code blocks, and some code blocks contain instructions with labels, which represent that the instructions are jump execution instructions corresponding to other instructions; the low-bit variable identifier and the high-bit variable identifier are set to mark the immediate usage state of the mask register, and each instruction in the code to be optimized is analyzed one by one based on the immediate usage state of the mask register according to the preset pseudo-instruction elimination rule to delete redundant pseudo-instructions; the instruction sequence corresponding to the pseudo-instruction is selected from a preset instruction sequence table to replace each remaining pseudo-instruction in the code to be optimized to obtain the mask optimized code.

[0011] In some embodiments of the present application, the preset pseudo-instruction elimination rule is to analyze each instruction in the code to be optimized one by one in the following manner: judging whether the current instruction is a pseudo-instruction, if it is a pseudo-instruction, analyzing whether the low-bit variable identifier and the high-bit variable identifier of the immediate usage state of the mask register are the same as the high-bit identifier and the low-bit identifier of the pseudo-instruction, if they are the same, deleting the pseudo-instruction, if they are not the same, updating the low-bit variable identifier and the high-bit variable identifier of the immediate usage state of the mask register to be consistent with the high-bit identifier and the low-bit identifier of the pseudo-instruction, and ending the analysis of the current instruction; if the current instruction is not a pseudo-instruction, analyzing whether the current instruction is provided with a label, if the current instruction is provided with a label, analyzing whether the usage states of the mask registers corresponding to other instructions that can jump to the current instruction are the same, if they are the same, updating the low-bit variable identifier and the high-bit variable identifier of the immediate usage state of the mask register to be consistent with the usage states of the mask registers corresponding to other instructions, if they are not the same, initializing the low-bit variable identifier and the high-bit variable identifier and ending the analysis of the current instruction; if the current instruction is not provided with a label, ending the analysis of the current instruction; wherein the initialization of the low-bit variable identifier and the high-bit variable identifier indicates that the immediate usage state of the mask register is set to not used.

[0012] In some embodiments of the present application, the preset instruction optimization rule is: deleting all csrr instructions and redundant vsetvl instructions in the mask optimization code according to a preset conversion rule, and replacing the remaining vsetvl instructions in the mask optimization code with vsetvli instructions to obtain intermediate optimization code; deleting invalid vsetvli instructions in the intermediate optimization code according to a preset one-stage elimination rule to obtain one-stage optimization code; performing instruction scheduling on the one-stage optimization code according to a preset instruction scheduling rule to adjust the arrangement order of each code block in the one-stage optimization code; and deleting duplicate vsetvli instructions in the one-stage optimization code after scheduling according to a preset two-stage elimination rule to obtain target optimization code.

[0013] In some embodiments of the present application, the preset conversion rule is: determining each vsetvl instruction in the mask optimization code, and the corresponding crss instruction of each vsetvl; analyzing each vsetvl instruction in the mask optimization code; wherein the analysis process of each vsetvl instruction is: taking the current vsetvl instruction as the starting point, traversing downward until the next vsetvl instruction or vsetvli instruction of the current vsetvl instruction is found, and analyzing whether the other instructions between the current vsetvl instruction and the next vsetvl instruction or vsetvli instruction use a specific field in the vector configuration register; if not, deleting the current vsetvl instruction and the corresponding csrr instruction, and ending the analysis of the current vsetvl instruction; if yes, taking the csrr instruction corresponding to the current vsetvl instruction as the starting point and traversing upward until the previous vsetvli instruction of the csrr instruction is found, and replacing the current vsetvl instruction with the previous vsetvli instruction, while deleting the csrr instruction corresponding to the current vsetvl instruction and ending the analysis of the current vsetvl instruction; wherein the vector configuration register is a vtype register, and the specific field in the vector configuration register is the sew field in the vtype register.

[0014] In some embodiments of the present application, the preset one-stage elimination rule is that each vsetvli instruction in the intermediate code is processed by one-stage elimination to delete invalid vsetvli instructions; wherein the one-stage elimination process of each vsetvli instruction is that the current vsetvli instruction is taken as a starting point, and then the following vsetvli instruction of the current vsetvli instruction is found by traversing downwards, and it is analyzed whether the specific field in the vector configuration register is used by other instructions between the current vsetvli instruction and the following vsetvli instruction; if the specific field in the vector configuration register is not used by other instructions between the current vsetvli instruction and the following vsetvli instruction, the current vsetvli instruction is deleted and the processing of the current vsetvli instruction is ended; otherwise, the current vsetvli instruction is not deleted and the processing of the current vsetvli instruction is ended.

[0015] In some embodiments of the present application, the preset instruction scheduling rule is that data flow analysis is performed on each code block in the one-stage optimization code to determine whether there is a data flow dependency relationship between the code blocks; wherein the data flow dependency relationship means that the execution of a certain instruction in the code block needs to depend on the execution result of other instructions in other code blocks in the order of sequence; and instruction scheduling is performed on any two code blocks in the one-stage optimization code without data flow dependency relationship until the instruction scheduling of each code block is completed, wherein the instruction scheduling of any two code blocks is performed in the following manner: the use state of the specific field in the vector configuration register indicated by the last vsetvli instruction in the code block in the order of sequence and the use state of the specific field in the vector configuration register indicated by the first vsetvli instruction in the code block in the order of sequence are determined, and it is analyzed whether the use states of the specific fields in the vector configuration registers indicated by the two instructions are the same, if the same, the code block in the order of sequence is scheduled after the code block in the order of sequence without affecting the execution result of other code blocks.

[0016] In some embodiments of the present application, the preset two-stage elimination rule is: a variable parameter identifier is set to mark the immediate use state of a specific field in a vector configuration register, and based on the immediate use state of the specific field in the vector configuration register marked by the variable parameter identifier, each instruction in the one-stage optimized code after instruction scheduling is processed one by one for two-stage elimination; wherein the two-stage elimination process of each instruction is: judging whether the current instruction is a vsetvli instruction, if it is a vsetvli instruction, analyzing whether the immediate use state of the specific field in the vector configuration register marked by the variable parameter identifier is consistent with the use state of the specific field in the vector configuration register corresponding to the current instruction, if it is consistent, deleting the current instruction and ending the processing of the current instruction; if it is not consistent, updating the variable parameter identifier to be consistent with the use state of the specific field in the vector configuration register corresponding to the current instruction, and ending the processing of the current instruction; if the current instruction is not a vsetvli instruction, analyzing whether the current instruction is set with a label; if the current instruction is set with a label, analyzing whether the use states of the specific fields in the vector configuration registers corresponding to all other instructions that can jump to the current instruction are consistent, if they are consistent, updating the variable parameter identifier to be consistent with the use states of the specific fields in the vector configuration registers corresponding to the other instructions and ending the processing of the current instruction, if they are not consistent, initializing the variable parameter identifier and ending the processing of the current instruction; if the current instruction is not set with a label, ending the processing of the current instruction; wherein the initialization of the variable parameter identifier means setting the immediate use state of the specific field in the vector configuration register to be unused.

[0017] According to the second aspect of the present application, an optimizer is provided for eliminating redundant instructions generated in the process of translating X86 vector instructions, the optimizer comprising: a data acquisition module for acquiring the optimized code containing multiple instructions obtained after translation processing; a mask optimization module for deleting redundant mask register setting instructions in the optimized code according to a preset mask optimization rule to obtain mask optimized code; a vsetvli optimization module for deleting all csrr instructions and redundant vsetvli instructions in the mask optimized code according to a preset instruction optimization rule to obtain target optimized code.

[0018] Compared with the prior art, the present application has the advantages that: redundant mask register setting instructions and vtype register setting instructions generated in the process of translating X86 vector instructions into RISC-V vector instructions are deleted, and the execution efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] The embodiments of the present application will be further described below with reference to the accompanying drawings, in which:

[0020] Figure 1A flowchart of an optimization method according to an embodiment of the present application;

[0021] Figure 2 A flowchart of a preset pseudo-instruction elimination rule according to an embodiment of the present application;

[0022] Figure 3 A flowchart of a preset conversion rule according to an embodiment of the present application;

[0023] Figure 4 A flowchart of a two-stage elimination rule according to an embodiment of the present application;

[0024] Figure 5 A schematic diagram of an optimizer composition according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0026] As mentioned in the background section, open source dynamic binary translators generate some redundant set instructions in the process of translating source X86 vector instructions into RISC-V vector instructions, which affect the execution efficiency of the translated code.

[0027] To solve the above problems, the inventors analyzed the translation process of X86 vector instructions and found that when translating a single X86 instruction, the vtype register and the mask register are set separately for each instruction due to the lack of context information between instructions, resulting in a large number of redundant set instructions. Based on this, the inventors propose an instruction optimization method for eliminating redundant instructions generated in the translation process of X86 vector instructions, which includes a mask optimization step and a vsetvli optimization step. In the mask optimization step, redundant mask register setting instructions are deleted according to a preset mask optimization rule; in the vsetvli optimization step, redundant vtype register setting instructions are deleted according to a preset instruction optimization rule.

[0028] In summary, as Figure 1As shown, an optimization method applied to X86 vector instruction translation is used to eliminate redundant instructions generated in the X86 vector instruction translation process, and the method comprises the following steps: obtaining the to-be-optimized code containing multiple instructions after translation processing, and performing the following steps: a mask optimization step: deleting the redundant mask register setting instructions in the to-be-optimized code according to a preset mask optimization rule to obtain mask optimization code; a vsetvli optimization step: deleting all csrr instructions and redundant vsetvli instructions in the mask optimization code according to a preset instruction optimization rule to obtain target optimization code.

[0029] In order to better understand the present application, the mask optimization step and the vsetvli optimization step will be described in detail below in combination with specific embodiments.

[0030] I. Mask optimization step

[0031] In the mask optimization step, the redundant mask register setting instructions in the to-be-optimized code are deleted according to a preset mask optimization rule to obtain mask optimization code.

[0032] According to an embodiment of the present application, the preset mask optimization rule is: according to the known instruction manual, all mask register setting instructions in the to-be-optimized code are replaced with pseudo-instructions, and high-bit and low-bit identifiers are set in the pseudo-instructions to mark the usage state of the mask register when the corresponding pseudo-instruction is executed; wherein the to-be-optimized code comprises multiple sequentially arranged code blocks, and some code blocks contain instructions with labels, which represent that the instructions are jump execution instructions corresponding to other instructions; the low-bit and high-bit variable identifiers are set to mark the immediate usage state of the mask register, and based on the immediate usage state of the mask register, each instruction in the to-be-optimized code is analyzed one by one according to the preset pseudo-instruction elimination rule to delete redundant pseudo-instructions; the instruction sequence corresponding to the pseudo-instruction is selected from the preset instruction sequence table to replace each remaining pseudo-instruction in the to-be-optimized code to obtain the mask optimization code.

[0033] It should be noted that the pseudo-instruction is set to replace the mask register setting instruction because the mask register setting instruction involves multiple instructions, and the specific value of the mask register cannot be inferred from the multiple instructions. If the pseudo-instruction is not introduced to replace the mask register setting instruction, it is difficult to effectively analyze the redundant mask register setting instruction when analyzing.

[0034] According to one embodiment of the present application, the preset pseudo-instruction elimination rule analyzes each instruction in the optimized code one by one in the following manner: it is determined whether the current instruction is a pseudo-instruction, if it is a pseudo-instruction, it is determined whether the low variable identifier and the high variable identifier of the immediate use state of the mask register are the same as the high identifier and the low identifier of the pseudo-instruction, if they are the same, the pseudo-instruction is deleted, if they are not the same, the low variable identifier and the high variable identifier of the immediate use state of the mask register are updated to be consistent with the high identifier and the low identifier of the pseudo-instruction, and the analysis of the current instruction is ended; if the current instruction is not a pseudo-instruction, it is determined whether the current instruction is provided with a label, if the current instruction is provided with a label, it is determined whether the use states of the mask registers corresponding to all other instructions that can jump to the current instruction are the same, if they are the same, the low variable identifier and the high variable identifier of the immediate use state of the mask register are updated to be consistent with the use states of the mask registers corresponding to the other instructions, if they are not the same, the low variable identifier and the high variable identifier are initialized, and the analysis of the current instruction is ended; if the current instruction is not provided with a label, the analysis of the current instruction is ended; wherein the initialization of the low variable identifier and the high variable identifier indicates that the immediate use state of the mask register is set to be unused.

[0035] In order to better understand the mask optimization step, the following will be described in detail in combination with the code example shown in Table 1 (the code example shown in Table 1 contains 9 instructions, and the instructions are not provided with labels) and the preset pseudo-instruction elimination rule flow diagram shown in Figure 1. Figure 2 In the preset pseudo-instruction elimination rule flow diagram shown in Figure 1, set_mask lo, hi represents a pseudo-instruction, lo represents the low 64 bits (low identifier) of the mask register, lo = 1 indicates that the low 64 bits of the mask register are used, lo = 0 indicates that the low 64 bits of the mask register are not used; hi represents the high 64 bits of the mask register, hi = 1 indicates that the high 64 bits of the mask register are used, hi = 0 indicates that the high 64 bits of the mask register are not used. For example, the pseudo-instruction set_mask 0x0, 0x1 indicates that the low 64 bits of the mask register are not used, and the high 64 bits of the mask register are used; pre_lo represents the low variable identifier, and pre_hi represents the high variable identifier.

[0036] According to the preset pseudo-instruction elimination rule, the following steps are performed on the code example shown in Table 1. Figure 2It can be known that before starting the mask optimization, the low bit variable identifier and the high bit variable identifier are initialized, i.e. pre_lo=-1 and pre_hi=-1 are set, which indicates that the immediate use state of the mask register is that the low 64 bits and the high 64 bits of the mask register are not used, and cur_ins=hd is initialized, wherein cur_ins represents the current pointed instruction, and cur_ins=hd indicates that the current pointed instruction is the first instruction in the code example shown in Table 1; then, according to the preset pseudo-instruction elimination rule, each instruction is analyzed one by one from the first instruction in the code example, and the code example after the elimination processing shown in Table 2 is obtained (Table 2 contains 7 instructions); finally, the instruction sequence corresponding to the pseudo-instruction is selected from the preset instruction sequence table to replace each remaining pseudo-instruction in Table 2 to obtain the mask optimization code.

[0037] Wherein, when analyzing the first instruction set_mask 0x0,0x1, cur_ins= set_mask 0x0,0x1, pre_lo=-1, pre_hi=-1. The specific analysis process is: first, it is judged whether the current pointed instruction is not empty (cur_ins! = null), at this time, cur_ins points to the first instruction set_mask 0x0,0x1, which satisfies cur_ins! = null; then, it is judged whether cur_ins points to the pseudo-instruction, at this time, cur_ins points to the pseudo-instruction set_mask 0x0,0x1, and it is judged whether the low bit variable identifier and the high bit variable identifier are consistent with the low bit identifier and the high bit identifier in the pseudo-instruction, since pre_lo=-1, pre_hi=-1, and the pseudo-instruction represented by the first instruction lo=0, hi=1, therefore pre_lo≠lo, pre_hi≠hi; the low bit variable identifier and the high bit variable identifier are modified to be consistent with the low bit identifier and the high bit identifier in the pseudo-instruction pointed by the current instruction, i.e. pre_lo=0, pre_hi=1, and the analysis of the first instruction is ended, so that cur_ins points to the next instruction.

[0038] When the first instruction vsetvli x0, x0, e64 is analyzed, cur_ins = vsetvli x0, x0, e64, pre_lo = 0, and pre_hi = 1. The specific analysis process is as follows: first, it is judged whether the currently pointed instruction is not empty (cur_ins!= null), at this time cur_ins points to the first instruction vsetvli x0, x0, e64, which satisfies cur_ins!= null; then, it is judged whether cur_ins points to a pseudo instruction, at this time cur_ins points to the non-pseudo instruction vsetvli x0, x0, e64, when cur_ins points to the non-pseudo instruction, it is analyzed whether the instruction pointed by cur_ins has a label, since the instruction pointed by cur_ins vsetvli x0, x0, e64 has no label, the analysis of the first instruction is ended, and cur_ins points to the next instruction.

[0039] When the third instruction vfadd.vv v6, v6, v8, v0 is analyzed, cur_ins = vfadd.vv v6, v6, v8, v0, pre_lo = 0, and pre_hi = 1. The specific analysis process is as follows: first, it is judged whether the currently pointed instruction is not empty (cur_ins!= null), at this time cur_ins points to the third instruction vfadd.vv v6, v6, v8, v0, which satisfies cur_ins!= null; then, it is judged whether cur_ins points to a pseudo instruction, at this time cur_ins points to the non-pseudo instruction vfadd.vv v6, v6, v8, v0, when cur_ins points to the non-pseudo instruction, it is analyzed whether the instruction pointed by cur_ins has a label, since the instruction pointed by cur_ins vfadd.vv v6, v6, v8, v0 has no label, the analysis of the third instruction is ended, and cur_ins points to the next instruction.

[0040] When analyzing the 4th instruction set_mask 0x0,0x1, cur_ins = set_mask 0x0,0x1, pre_lo = 0, and pre_hi = 1. The specific analysis process is as follows: first, it is judged whether the current instruction is empty (cur_ins!= null), at this time, cur_ins points to the 4th instruction set_mask 0x0,0x1, which satisfies cur_ins!= null; then it is judged whether cur_ins points to a pseudo instruction, at this time, cur_ins points to the pseudo instruction set_mask 0x0,0x1, and it is judged whether the low bit variable identifier and the high bit variable identifier are consistent with the low bit identifier and the high bit identifier in the pseudo instruction, since pre_lo = 0, pre_hi = 1, and the pseudo instruction represented by the 4th instruction set_mask 0x0,0x1 has lo = 0 and hi = 1, therefore, pre_lo = lo, and pre_hi = hi, the 4th instruction set_mask 0x0,0x1 can be deleted, and the analysis of the 4th instruction is ended, and cur_ins points to the next instruction.

[0041] The analysis processes of the subsequent 5th instruction to the 9th instruction are consistent with the analysis processes of the foregoing instructions, which will not be described one by one here.

[0042] It can be known from Table 1 and Table 2 that, after the code example shown in Table 1 is analyzed and processed according to the preset pseudo instruction elimination rule, the pseudo instructions corresponding to the 4th and 7th instructions in the code example can be deleted.

[0043] Table 1

[0044]

[0045]

[0046] Based on the foregoing embodiment, it can be known that, in the mask optimization step, a pseudo instruction is introduced to identify the use state of the mask register, and a low bit variable identifier and a high bit variable identifier are set to mark the immediate use state of the mask register, and whether the use state of the mask register of each instruction and the immediate use state of the mask register are the same is analyzed to delete the redundant pseudo instruction, and the remaining pseudo instruction is replaced by a normal instruction sequence, the optimization of the mask register setting instruction is realized, and the code execution efficiency is improved.

[0047] II. Vsetvli optimization step

[0048] In the vsetvli optimization step, all csrr instructions and redundant vsetvli instructions in the mask optimization code are deleted according to a preset instruction optimization rule to obtain target optimization code.

[0049] According to one embodiment of the present application, the preset instruction optimization rule is: deleting all csrr instructions and redundant vsetvl instructions in the mask optimization code according to a preset conversion rule, and replacing the remaining vsetvl instructions in the mask optimization code with vsetvli instructions to obtain intermediate optimization code; deleting invalid vsetvli instructions in the intermediate optimization code according to a preset one-stage elimination rule to obtain one-stage optimization code; performing instruction scheduling on the one-stage optimization code according to a preset instruction scheduling rule to adjust the arrangement order of each code block in the one-stage optimization code; and deleting repeated vsetvli instructions in the one-stage optimization code after scheduling according to a preset two-stage elimination rule to obtain target optimization code.

[0050] According to one embodiment of the present application, the preset conversion rule is: determining each vsetvl instruction in the mask optimization code, and the corresponding crss instruction of each vsetvl; analyzing each vsetvl instruction in the mask optimization code; wherein the analysis process of each vsetvl instruction is: taking the current vsetvl instruction as the starting point, traversing downward until the next vsetvl instruction or vsetvli instruction of the current vsetvl instruction is found, and analyzing whether the other instructions between the current vsetvl instruction and the next vsetvl instruction or vsetvli instruction use a specific field in the vector configuration register; if not, deleting the current vsetvl instruction and the corresponding csrr instruction, and ending the analysis of the current vsetvl instruction; if yes, taking the csrr instruction corresponding to the current vsetvl instruction as the starting point to traverse upward until the previous vsetvli instruction of the csrr instruction is found, and replacing the current vsetvl instruction with the previous vsetvli instruction, while deleting the csrr instruction corresponding to the current vsetvl instruction and ending the analysis of the current vsetvl instruction; wherein the vector configuration register is a vtype register, and the specific field in the vector configuration register is the sew field in the vtype register.

[0051] It should be noted that if an instruction related to the sew field in the vtype register is found between the current vsetvl instruction or vsetvli instruction and the next vsetvl instruction or vsetvli instruction, the sew field in the vtype register is considered to be used; if no instruction related to the sew field in the vtype register is found between the current vsetvl instruction and the next vsetvl instruction or vsetvli instruction, the sew field in the vtype register is considered not to be used. Whether an instruction is an instruction related to the sew field can be determined according to whether the value of the sew field affects the execution result of the instruction. If the value of the sew field affects the execution result of the instruction, the instruction is an instruction related to the sew field. If the value of the sew field does not affect the execution result of the instruction, the instruction is an instruction unrelated to the sew field. For example, the scalar instruction, the bit operation vector instruction and the move vector instruction in the RISC-V instruction are all instructions unrelated to the sew field; and the vector operation instruction is an instruction related to the sew field.

[0052] In order to better understand the preset conversion rule, the code shown in Table 3 (Table 3 contains 13 instructions, and the instructions without labels are not set) is taken as an example, and the preset conversion rule flow diagram shown in Table 5 is used for description. Figure 3

[0053] For the code example given in Table 3: first determine each vsetvl instruction in the example and each vsetvl instruction corresponding csrr instruction, only the 6th instruction in the example is a vsetvl instruction, and the 6th instruction corresponds to the 4th csrr instruction (vsetvl instruction and csrr instruction appear in pairs, csrr instruction is used to save the state of the vtype register, vsetvl is used to restore the state of the vtype register, and the next saved is the next restored); take the 6th vsetvl instruction as the starting point, traverse the mask optimization code downward until the 8th vsetvli instruction is found, at this time the 7th instruction vfadd.vvv6, v6, v8, v0 is an instruction related to the sew field, which indicates that the 7th instruction between the 6th instruction and the 8th instruction uses the sew field in the vector configuration register; take the 4th csrr instruction corresponding to the 6th vsetvl instruction as the starting point and traverse upward until the vsetvli instruction (vsetvli x0, x0, e32) before the csrr instruction is found, and replace the 6th vsetvl instruction with the vsetvli x0, x0, e32 instruction, and delete the 4th csrr instruction corresponding to the 6th instruction, to obtain the code example after conversion processing as shown in Table 4 (Table 4 contains 12 instructions).

[0054] Table 3​

[0055]

[0056]

[0057] According to one embodiment of the present application, the preset one-stage elimination rule is that each vsetvli instruction in the intermediate code is processed by one-stage elimination to delete invalid vsetvli instructions; wherein the one-stage elimination process of each vsetvli instruction is that the current vsetvli instruction is taken as a starting point, and then it is traversed downwards until the next vsetvli instruction of the current vsetvli instruction is found, and it is analyzed whether the specific field in the vector configuration register is used by other instructions between the current vsetvli instruction and the next vsetvli instruction; if the specific field in the vector configuration register is not used by other instructions between the current vsetvli instruction and the next vsetvli instruction, the current vsetvli instruction is deleted and the processing of the current vsetvli instruction is ended; otherwise, the current vsetvli instruction is not deleted and the processing of the current vsetvli instruction is ended.

[0058] In order to better understand the preset one-stage elimination rule, the following takes the code example given in Table 4 as an example for illustration.

[0059] For the code example shown in Table 4, the one-stage elimination process is performed from the first vsetvli instruction.

[0060] For the first vsetvli instruction: vsetvli x0, x0, e32, there is no other instruction between the first vsetvli instruction and the next vsetvli instruction (the second instruction), so the current vsetvli instruction is not deleted.

[0061] For the second vsetvli instruction: vsetvli x0, x0, e64, since the other instructions between the second vsetvli instruction and the next vsetvli instruction (the fifth instruction) are all instructions irrelevant to the sew field, the second vsetvli instruction can be deleted.

[0062] For the third vsetvli instruction: vsetvli x0, x0, e32, since the other instructions between the third vsetvli instruction and the next vsetvli instruction (the seventh instruction) are instructions relevant to the sew field, the third vsetvli instruction cannot be deleted; by analogy, the code example after one-stage elimination processing is shown in Table 5 (Table 5 contains 10 instructions).

[0063]

[0064] According to one embodiment of the present application, the preset instruction scheduling rule is: performing data flow analysis on each code block in the one-stage optimized code to determine whether there is a data flow dependency relationship between the code blocks; wherein the data flow dependency relationship indicates that the execution of an instruction in a code block needs to depend on the execution result of other instructions in other code blocks in sequence; performing instruction scheduling on any two code blocks in the one-stage optimized code until the instruction scheduling on each code block is completed, wherein the instruction scheduling on any two code blocks is performed in the following manner: determining the use state of a specific field in a vector configuration register indicated by the last vsetvli instruction in the code block in sequence, and the use state of the specific field in the vector configuration register indicated by the first vsetvli instruction in the code block in sequence, and analyzing whether the use states of the specific fields in the vector configuration registers indicated by the two instructions are the same, and if so, scheduling the code block in sequence to after the code block in sequence without affecting the execution result of other code blocks.

[0065] It should be noted that the instruction scheduling processing is needed because in this way, the vsetvli instructions repeatedly set in the code can be deleted to the maximum extent without affecting the execution result of each instruction in the code block.

[0066] According to one embodiment of the present invention, the preset two-stage elimination rule is: setting a variable parameter identifier to mark the immediate usage status of a specific field in the vector configuration register, and based on the immediate usage status of the specific field in the vector configuration register marked by the variable parameter identifier, performing two-stage elimination processing on each instruction in the one-stage optimization code after instruction scheduling; wherein, the two-stage elimination processing process of each instruction is: judging whether the current instruction is a vsetvli instruction, if it is a vsetvli instruction, analyzing whether the immediate usage status of the specific field in the vector configuration register marked by the variable parameter identifier is consistent with the usage status of the specific field in the vector configuration register corresponding to the current instruction, if they are consistent, deleting the current instruction and ending the processing of the current instruction; if they are inconsistent, changing the variable parameter identifier to a new one. The new usage status is consistent with the usage status of the specific field in the vector configuration register corresponding to the current instruction, and the processing of the current instruction is terminated; if the current instruction is not the vsetvli instruction, analyze whether the current instruction is set with a label; if the current instruction is set with a label, analyze whether the usage status of the specific field in the vector configuration register corresponding to all other instructions that can jump to the current instruction is consistent, if it is consistent, update the variable parameter identifier to be consistent with the usage status of the specific field in the vector configuration register corresponding to other instructions and terminate the processing of the current instruction, if it is inconsistent, initialize the variable parameter identifier and terminate the processing of the current instruction; if the current instruction is not set with a label, terminate the processing of the current instruction; wherein, the variable parameter identifier initialization means setting the immediate usage status of the specific field in the vector configuration register to unused.

[0067] In order to better understand the preset two-stage elimination rules, the following code example is shown in Table 5, combined with Figure 4 The two-stage elimination rule flow diagram is shown for explanation. In which cur_sew represents a variable parameter identifier.

[0068] Depend on Figure 4 It can be seen that before the two-stage elimination process, the variable parameter flag is initialized first, that is, cur_sew=-1 is set to indicate that the sew field in the vtype register is not used, and cur_ins=hd is initialized, where cur_ins represents the currently pointed instruction, and cur_ins=hd indicates that the currently pointed instruction is the first instruction in the code shown in Table 5; then, each instruction is processed one by one starting from the first instruction in the code example according to the preset two-stage elimination rule, and the code example after the two-stage elimination process is obtained as shown in Table 6 (Table 6 contains 8 instructions).

[0069] When the first instruction vsetvli x0, x0, e64 is processed, cur_sew = -1, and cur_ins = vsetvli x0, x0, e64. It is determined whether the first instruction is a vsetvli instruction. In this case, the first instruction is a vsetvli instruction. Then, it is analyzed whether the value of cur_sew is consistent with the value of the sew field in the first instruction. In this case, cur_sew = -1, and the sew in the first instruction is e64, cur_sew ≠ sew. Since cur_sew ≠ sew, the value of cur_sew is updated to e64, and the processing of the first instruction is ended.

[0070] When the second instruction li s6, 1 is processed, cur_sew = e64, and cur_ins = li s6, 1. Since the second instruction is not a vsetvli instruction and has no tag, the processing of the second instruction is ended.

[0071] When the third instruction vmv.sx v0, s6 is processed, cur_sew = e64, and cur_ins = vmv.sx v0, s6. Since the third instruction is not a vsetvli instruction and has no tag, the processing of the third instruction is ended.

[0072] When the fourth instruction vsetvli x0, x0, e32 is processed, cur_sew = e64, and cur_ins = vsetvli x0, x0, e32. It is determined whether the fourth instruction is a vsetvli instruction. In this case, the fourth instruction is a vsetvli instruction. Then, it is analyzed whether the value of cur_sew is consistent with the value of the sew in the fourth instruction. In this case, cur_sew = e64, and the sew in the fourth instruction is e32, cur_sew ≠ sew. Since cur_sew ≠ sew, the value of cur_sew is updated to e32, and the processing of the fourth instruction is ended.

[0073] When the fifth instruction vfadd.vv v6, v6, v8, v0 is processed, cur_sew = e32, and cur_ins = vfadd.vv v6, v6, v8, v0. Since the fifth instruction is not a vsetvli instruction and has no tag, the processing of the fifth instruction is ended.

[0074] When the sixth instruction vor.vv v10, v10, v12 is processed, cur_sew = e32, and cur_ins = vor.vv v10, v10, v12. Since the sixth instruction is not a vsetvli instruction and has no tag, the processing of the sixth instruction is ended.

[0075] When the seventh instruction vsetvli x0, x0, e32 is processed, cur_sew = e32, cur_ins = vsetvli x0, x0, e32, it is judged whether the seventh instruction is a vsetvli instruction, and the seventh instruction is a vsetvli instruction at this time; then, it is analyzed whether the value of cur_sew is consistent with the value of sew in the seventh instruction, cur_sew = e32, sew = e32 in the seventh instruction, and cur_sew = sew; since cur_sew = sew, the seventh instruction is deleted.

[0076] The processing processes of the eighth instruction to the tenth instruction are consistent with the processing processes of the foregoing instructions, and will not be described one by one here.

[0077]

[0078] It should be noted that the optimization method proposed in the present application is applicable to the code obtained by processing any open source dynamic binary translator. Among them, some dynamic binary translators only support the translation of vector instructions of the source X86 architecture into scalar instructions of the target RISC-V architecture, at this time, only after the scalar instructions are converted into vector instructions can the optimization method proposed in the present application be applied for optimization processing.

[0079] Based on the optimization method described in the foregoing embodiments, as shown in Figure 5 The present application also proposes an optimizer for eliminating redundant instructions generated in the translation process of X86 vector instructions, the optimizer comprising: a data acquisition module for acquiring the to-be-optimized code containing multiple instructions obtained after translation processing; a mask optimization module for deleting redundant mask register setting instructions in the to-be-optimized code according to a preset mask optimization rule to obtain mask optimized code; and a vsetvli optimization module for deleting all csrr instructions and redundant vsetvli instructions in the mask optimized code according to a preset instruction optimization rule to obtain target optimized code.

[0080] The present application has the beneficial effect that the redundant mask register setting instructions and vtype register setting instructions generated in the process of translating X86 vector instructions into RISC-V vector instructions are deleted, and the execution efficiency is improved.

[0081] It should be noted that although the above describes each step in a specific order, it does not mean that each step must be executed in the above specific order, in fact, some of these steps can be executed concurrently, or even the order is changed, as long as the required function can be realized.

[0082] The present application can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present application.

[0083] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium can also include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se.

[0084] Having described above several embodiments of the present application, any modifications and variations that fall within the scope of the described embodiments are also to be considered as falling within the scope of the present application. The above description is that of current embodiments of the application, and is not to be construed as limiting the scope of the application, which is to be determined by the appended claims. The language used in this specification should not be used to argue, by implication, limitation or exclusion, that any particular hardware recited is a requirement of the application. The language used is merely an aid in learning the inventive function of the devices and / or methods with which the present application is concerned, and should not be construed to limit the range of acceptable hardware or acceptable methods, that maintain the spirit and essential qualities of the application.

Claims

1. An optimization method for X86 vector instruction translation, for eliminating redundant instructions generated during the X86 vector instruction translation process, characterized in that: The method includes obtaining a code to be optimized containing multiple instructions obtained after translation processing, and performing the following steps: Mask optimization step: Deleting redundant mask register setting instructions in the code to be optimized according to a preset mask optimization rule to obtain a mask optimized code, wherein the preset mask optimization rule is: According to a known instruction manual, all mask register setting instructions in the code to be optimized are replaced with pseudo-instructions, and a high-order flag and a low-order flag are set in the pseudo-instructions to mark the usage status of the mask register when the corresponding pseudo-instructions are executed; wherein the code to be optimized includes a plurality of sequentially arranged code blocks, and some of the code blocks include instructions with labels, and the instructions with labels indicate that the instructions are jump execution instructions corresponding to other instructions; Setting a low-order variable flag and a high-order variable flag to mark the immediate use status of the mask register, and analyzing each instruction in the optimized code one by one according to a preset pseudo-instruction elimination rule based on the immediate use status of the mask register to delete redundant pseudo-instructions; Selecting an instruction sequence corresponding to a pseudo-instruction from a preset instruction sequence table to replace each remaining pseudo-instruction in the code to be optimized to obtain a masked optimized code; vsetvli optimization step: Delete all csrr instructions and redundant vsetvli instructions in the mask optimization code according to the preset instruction optimization rules to obtain the target optimized code, wherein the preset instruction optimization rules are: According to the preset conversion rules, all csrr instructions and redundant vsetvl instructions in the mask optimization code are deleted, and the remaining vsetvl instructions in the mask optimization code are replaced with vsetvli instructions to obtain the intermediate optimized code; Delete invalid vsetvli instructions in the intermediate optimized code according to the preset one-stage elimination rule to obtain the one-stage optimized code; Performing instruction scheduling on the first-stage optimized code according to a preset instruction scheduling rule to adjust the arrangement order of each code block in the first-stage optimized code; And according to the preset two-stage elimination rule, the repeated vsetvli instructions in the scheduled one-stage optimization code are deleted to obtain the target optimized code.

2. The method according to claim 1, characterized in that The preset pseudo-instruction elimination rule is to analyze each instruction in the optimized code one by one in the following manner: Determine whether the current instruction is a pseudo-instruction. If it is a pseudo-instruction, analyze whether the low-order variable flag and the high-order variable flag of the instant use state of the mask register are the same as the high-order flag and the low-order flag of the pseudo-instruction. If they are the same, delete the pseudo-instruction. If they are not the same, update the low-order variable flag and the high-order variable flag of the instant use state of the mask register to be consistent with the high-order flag and the low-order flag of the pseudo-instruction, and end the analysis of the current instruction. If the current instruction is not a pseudo-instruction, analyze whether the current instruction is set with a label. If the current instruction is set with a label, analyze whether the usage status of the mask registers corresponding to all other instructions that can jump to the current instruction is the same. If they are the same, update the low-order variable flag and the high-order variable flag of the immediate usage status of the mask register to be consistent with the usage status of the mask register corresponding to other instructions. If they are not the same, initialize the low-order variable flag and the high-order variable flag and end the analysis of the current instruction; if the current instruction is not set with a label, end the analysis of the current instruction; wherein, initializing the low-order variable flag and the high-order variable flag means setting the immediate usage status of the mask register to unused.

3. The method according to claim 2, characterized in that The preset conversion rules are: Determine each vsetvl instruction in the mask optimization code, and the crss instruction corresponding to each vsetvl; Analyze each vsetvl instruction in the mask optimization code; the analysis process of each vsetvl instruction is as follows: Starting from the current vsetvl instruction, traverse downward until the next vsetvl instruction or vsetvli instruction after the current vsetvl instruction is found, and analyze whether other instructions between the current vsetvl instruction and the next vsetvl instruction or vsetvli instruction use a specific field in the vector configuration register; If not used, delete the current vsetvl instruction and the corresponding csrr instruction, and end the analysis of the current vsetvl instruction; If it has been used, start from the csrr instruction corresponding to the current vsetvl instruction and traverse upward until the previous vsetvli instruction of the csrr instruction is found, and replace the current vsetvl instruction with the previous vsetvli instruction. At the same time, delete the csrr instruction corresponding to the current vsetvl instruction and end the analysis of the current vsetvl instruction. The vector configuration register is a vtype register, and the specific field in the vector configuration register is a sew field in the vtype register.

4. The method according to claim 3, characterized in that The preset one-stage elimination rule is: Perform a one-stage elimination process on each vsetvli instruction in the intermediate code to delete invalid vsetvli instructions; wherein, the one-stage elimination process of each vsetvli instruction is as follows: Starting from the current vsetvli instruction, traverse downward until the next vsetvli instruction is found, and analyze whether other instructions between the current vsetvli instruction and the next vsetvli instruction use a specific field in the vector configuration register; If other instructions between the current vsetvli instruction and the next vsetvli instruction do not use the specific field in the vector configuration register, the current vsetvli instruction is deleted and the processing of the current vsetvli instruction ends; otherwise, the current vsetvli instruction is not deleted and the processing of the current vsetvli instruction ends.

5. The method according to claim 4, characterized in that The preset instruction scheduling rules are: Perform data flow analysis on each code block in the first-stage optimized code to determine whether there are data flow dependencies between the code blocks. A data flow dependency indicates that the execution of a certain instruction in a code block depends on the execution results of other instructions in other code blocks that are ordered earlier. Instruction scheduling is performed on any two code blocks that do not have data flow dependencies in the first-stage optimized code until instruction scheduling of each code block is completed. Instruction scheduling is performed on any two code blocks in the following manner: Determine the usage status of a specific field in the vector configuration register indicated by the last vsetvli instruction in the code block that is sorted first, and the usage status of a specific field in the vector configuration register indicated by the first vsetvli instruction in the code block that is sorted later, and analyze whether the usage status of the specific fields in the vector configuration register indicated by these two instructions are the same. If they are the same, schedule the code block that is sorted later to after the code block that is sorted earlier without affecting the execution results of other code blocks.

6. The method according to claim 5, characterized in that The preset two-stage elimination rule is: A variable parameter flag is set to mark the immediate use status of a specific field in the vector configuration register, and based on the immediate use status of the specific field in the vector configuration register marked by the variable parameter flag, a two-stage elimination process is performed on each instruction in the first-stage optimized code after instruction scheduling. The two-stage elimination process of each instruction is as follows: Determine whether the current instruction is a vsetvli instruction. If it is a vsetvli instruction, analyze whether the immediate usage status of the specific field in the vector configuration register marked by the variable parameter identifier is consistent with the usage status of the specific field in the vector configuration register corresponding to the current instruction. If they are consistent, delete the current instruction and end the processing of the current instruction; if they are inconsistent, update the variable parameter identifier to be consistent with the usage status of the specific field in the vector configuration register corresponding to the current instruction, and end the processing of the current instruction. If the current instruction is not a vsetvli instruction, analyze whether the current instruction is set with a label; if the current instruction is set with a label, analyze whether the usage status of specific fields in the vector configuration registers corresponding to all other instructions that can jump to the current instruction is consistent; if they are consistent, update the variable parameter identifier to be consistent with the usage status of the specific fields in the vector configuration registers corresponding to other instructions and end the processing of the current instruction; if they are inconsistent, initialize the variable parameter identifier and end the processing of the current instruction; if the current instruction is not set with a label, end the processing of the current instruction; The variable parameter flag initialization indicates setting the immediate use state of a specific field in the vector configuration register to unused.

7. An optimizer based on the method according to any one of claims 1 to 6, for eliminating redundant instructions generated during the translation of X86 vector instructions, characterized in that: The optimizer includes: A data acquisition module is used to acquire the code to be optimized containing multiple instructions obtained after translation processing; A mask optimization module, configured to delete redundant mask register setting instructions in the code to be optimized according to preset mask optimization rules to obtain mask optimized code; The vsetvli optimization module is used to delete all csrr instructions and redundant vsetvli instructions in the mask optimization code according to preset instruction optimization rules to obtain target optimized code.

8. A computer-readable storage medium, characterized in that A computer program is stored thereon, and the computer program can be executed by a processor to implement the steps of any one of the methods of claims 1-6.

9. An electronic device, characterized in that: include: One or more processors, and memory, wherein the memory is configured to store executable instructions; The one or more processors are configured to implement the steps of the method according to any one of claims 1 to 6 by executing the executable instructions.

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