Server voltage monitoring system and method, electronic equipment and storage medium

Abstract

The invention provides a server voltage monitoring system and method, electronic equipment and a storage medium, and relates to the technical field of computers, the system comprises a complex programmable logic device CPLD, and an initial timing module, a voltage acquisition module, an abnormal data storage module, a CPU processor and a baseboard management controller BMC module which are respectively in communication connection with the CPLD. The initial timing module activates the monitoring function of the CPLD through a startup signal; the voltage acquisition module acquires voltage data under the control of the CPLD so as to read the voltage data of the server mainboard; the CPLD obtains voltage data, compares the voltage data with a reference voltage range of the abnormal data storage module, triggers an interrupt signal after identifying abnormal fluctuation voltage, and feeds back the interrupt signal to the CPU and the BMC, so that the CPU and the BMC quickly output an alarm. The system covers full-cycle monitoring from startup to BMC startup, supports efficient acquisition, dynamic detection and low-delay response of multi-path voltage, relieves the voltage pressure of a BMC monitoring mainboard, and provides reliable guarantee for power supply safety of a server.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a server voltage monitoring system, method, electronic device, and storage medium. Background Art

[0002] With the continuous improvement of the functions and performance of servers, the design complexity thereof also increases accordingly, which makes the monitoring of server hardware and the human-machine status interaction particularly important. Currently, in the initial stage of power-on of the server, the monitoring of the server status is relatively weak. In the BIOS SETUP interface and the BMC (Board Management Controller) Web interface, the voltage fluctuation of the main board power supply can be monitored when the BMC is not activated in the initial stage of power-on. This monitoring ability is crucial for users to timely understand the abnormal status of the server in the initial stage of power-on and discover the power supply characteristics at the customer site.

[0003] However, the existing technical solutions have obvious deficiencies in voltage monitoring in the initial stage of server startup. For example, servers using mature technologies such as X86 usually rely on the BMC management module or the SuperIO chip to monitor the main board voltage, but these solutions cannot effectively monitor the voltage before the BMC starts (about 90 seconds), resulting in a monitoring blind spot within the first 90 seconds of server startup. In addition, as an important part of server supervision, the BMC is responsible for heavy supervision tasks, and the designed main board voltage monitoring resources are limited and cannot effectively cope with the various types of server power supply voltages. Summary of the Invention

[0004] The present disclosure provides a server voltage monitoring system, method, electronic device, and storage medium to at least solve the above technical problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, a server voltage monitoring system is provided. The system includes a Complex Programmable Logic Device (CPLD), an initial timing module, a voltage acquisition module, an abnormal data storage module, a CPU processor, and a Baseboard Management Controller (BMC) module that are respectively communicatively connected to the CPLD, wherein:

[0006] The initial timing module is configured to monitor the time window from the power-on of the server to the completion of the startup of the Baseboard Management Controller (BMC) module, and activate the monitoring function of the CPLD within the time window;

[0007] The voltage acquisition module is configured to acquire multiplexed voltage data of the server main board power supply and transmit the data to the CPLD;

[0008] The CPLD is used to control the voltage acquisition operation of the voltage acquisition module, cache the voltage data into a register, compare the voltage data with a reference voltage range, identify the fluctuating voltage exceeding the reference voltage range, and trigger an interrupt signal.

[0009] The abnormal data storage module is used to store the reference voltage range in a non-volatile random access memory (NVRAM), and alternately store the fluctuating voltage obtained from the CPLD through two of the NVRAMs.

[0010] The CPU processor and the BMC module are used to read the voltage data from the register of the CPLD, trigger an interrupt in response to the interrupt signal, and feedback the fluctuating voltage.

[0011] In an implementable embodiment, the voltage acquisition module includes multiple analog-to-digital converters (ADCs). Each ADC is assigned an independent address and connected to the CPLD through an I2C bus for parallel acquisition of voltage data of multiple power supply paths on the server motherboard.

[0012] In an implementable embodiment, the CPLD communicates with the CPU processor and the BMC module through the I2C protocol, and performs verification processing on the transmitted data based on a multi-byte data group transmission protocol and a cyclic redundancy check code.

[0013] In an implementable embodiment, the CPLD includes:

[0014] A first register for storing the voltage data read by the CPU processor;

[0015] A second register for storing the voltage data read by the BMC module;

[0016] The first register and the second register respectively reserve storage spaces for multiple acquisitions of voltage data. The CPLD calculates the voltage data based on the percentage deviation counting method and stores them in the first register and the second register respectively.

[0017] In an implementable embodiment, the CPLD generates a first interrupt signal to trigger the CPU processor to read the fluctuating voltage and the corresponding time information from the abnormal data storage module and display them in the BIOS interface;

[0018] The CPLD generates a second interrupt signal to trigger the BMC module to read the fluctuating voltage from the second register and display it in the Web interface.

[0019] In one possible implementation, the BMC module is further used to dynamically adjust the reference voltage range in the abnormal data storage module according to the ambient temperature, including: the BMC module reads temperature sensor data and dynamically adjusts the reference voltage range according to the ambient temperature.

[0020] In one possible implementation manner, the system further includes: a power status monitoring module, which is used to collect the enable signal and the power normal signal of the voltage acquisition module, and transmit the signal status to the CPLD.

[0021] In one possible implementation, the system further comprises: an LED status indication module, the LED status indication module comprising a multi-segment digital tube;

[0022] When the power status monitoring module detects a power abnormality signal, the CPLD controls the LED status indication module to display an abnormal channel number;

[0023] When the CPLD detects a fluctuating voltage, the LED status indication module is controlled to flash and display the abnormal channel number at a frequency corresponding to the number of fluctuations.

[0024] In one possible implementation manner, the CPU processor and the BMC module respectively control the channel enable state of the voltage acquisition module through register enable control ports respectively.

[0025] In one possible implementation, the initial timing module determines the time window by monitoring a server power-on signal and a server reset signal, a BMC start signal and a BMC reset signal, and an I2C clock signal.

[0026] According to a second aspect of the present disclosure, a server voltage monitoring method is provided, the method comprising:

[0027] The monitoring server is powered on to the time window when the baseboard management controller BMC module is started, and the monitoring function of the complex programmable logic device CPLD is activated within the time window;

[0028] The CPLD controls multiple analog-to-digital converters ADC to collect multi-channel voltage data of the server mainboard power supply, caches the voltage data in a register, and compares the voltage data with a reference voltage range stored in a non-volatile random access memory NVRAM, identifies a fluctuating voltage that exceeds the range, and triggers an interrupt signal;

[0029] The fluctuating voltage is alternately stored by two NVRAMs;

[0030] The voltage data is read from the register of the CPLD through the CPU processor and the BMC module, and an interrupt is triggered in response to the interrupt signal and the fluctuating voltage is fed back.

[0031] In one implementable embodiment, the multiple-channel voltage data of the acquisition server motherboard power supply includes:

[0032] Multiple-channel voltage data of the acquisition server motherboard power supply is acquired in parallel through multiple ADCs. Each of the ADCs is assigned an independent address and connected to the CPLD through the I2C bus.

[0033] In one implementable embodiment, the CPLD communicates with the CPU processor and the BMC module through the I2C protocol, and performs verification processing on the transmitted data based on the multi-byte data group transmission protocol and the cyclic redundancy check code.

[0034] In one implementable embodiment, the CPLD caches the voltage data into registers, including:

[0035] Storing the voltage data read by the CPU processor into the first register of the CPLD;

[0036] Storing the voltage data read by the BMC module into the second register of the CPLD;

[0037] The first register and the second register respectively reserve storage spaces for collecting voltage data multiple times. The CPLD calculates the voltage data based on the percentage deviation counting method and stores it into the first register and the second register respectively.

[0038] In one implementable embodiment, the CPLD triggers an interrupt signal, including:

[0039] Generating a first interrupt signal through the CPLD to trigger the CPU processor to read the fluctuating voltage and the corresponding time information from the NVRAM and display them in the BIOS interface;

[0040] Generating a second interrupt signal through the CPLD to trigger the BMC module to read the fluctuating voltage from the second register and display it in the Web interface.

[0041] In one implementable embodiment, the method further includes:

[0042] Reading the temperature sensor data through the BMC module and dynamically adjusting the reference voltage range according to the ambient temperature.

[0043] In one implementable embodiment, the method further includes:

[0044] Collecting the enable signals and power normal signals of the multiple ADCs and transmitting the signal states to the CPLD.

[0045] In one implementable embodiment, the method further includes:

[0046] When a power anomaly signal is detected, the CPLD is used to control the multi-segment digital tube to display the abnormal channel number.

[0047] When a fluctuating voltage is detected, the CPLD is used to control the multi-segment digital tube to flash and display the abnormal channel number at a frequency corresponding to the number of fluctuations.

[0048] In an implementable embodiment, the method further includes:

[0049] The CPU processor and the BMC module respectively control the channel enabling states of the multiple ADCs through the register enabling control ports.

[0050] In an implementable embodiment, the time window from when the monitoring server is powered on to when the startup of the baseboard management controller BMC module is completed includes:

[0051] Monitoring the power-on signal of the monitoring server, the server reset signal, the BMC startup signal, the BMC reset signal, and the I2C clock signal to determine the time window.

[0052] According to a third aspect of the present disclosure, an electronic device is provided, including:

[0053] At least one processor; and

[0054] A memory communicatively connected to the at least one processor; wherein,

[0055] The memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor is enabled to execute the method described in the present disclosure.

[0056] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, and the computer instructions are used to cause the computer to execute the method described in the present disclosure.

[0057] The server voltage monitoring system, method, electronic device and storage medium of the present disclosure. The system includes a CPLD, and an initial timing module, a voltage acquisition module, an abnormal data storage module, a CPU processor and a baseboard management controller BMC module that are respectively communicatively connected to the CPLD. Among them, the initial timing module activates the CPLD monitoring function through a power-on signal; the voltage acquisition module acquires voltage data under the control of the CPLD to realize the reading of voltage data of various types on the server motherboard; the CPLD compares the acquired voltage data with the reference voltage range in the abnormal data storage module, and triggers an interrupt signal and feeds it back to the CPU and BMC after identifying abnormal fluctuating voltage, so that they can quickly output an alarm. The system covers the full-cycle monitoring from power-on to BMC startup, supports efficient acquisition of multiple voltages, dynamic detection and low-latency response, relieves the pressure of the BMC to monitor the motherboard voltage, and provides a reliable guarantee for the power supply safety of the server.

[0058] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become easily understood. In the drawings, several embodiments of the present disclosure are shown in an exemplary rather than restrictive manner, wherein:

[0060] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0061] Figure 1 The structural schematic diagram of the server voltage monitoring system according to the embodiment of the present disclosure is shown;

[0062] Figure 2 The topology diagram of the voltage acquisition module according to the embodiment of the present disclosure is shown;

[0063] Figure 3 The topology diagram of the power status monitoring module according to the embodiment of the present disclosure is shown;

[0064] Figure 4 The schematic diagram of the implementation process of the server voltage monitoring method according to the embodiment of the present disclosure is shown;

[0065] Figure 5 The composition structural schematic diagram of an electronic device according to the embodiment of the present disclosure is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0066] To make the objectives, features, and advantages of the present disclosure more apparent and understandable, the following will clearly and completely describe the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present disclosure.

[0067] In the following description, reference is made to "some embodiments", which describe subsets of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict.

[0068] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of this disclosure and are not intended to limit this disclosure.

[0069] Before further elaborating on the embodiments of the present disclosure, the nouns and terms involved in the embodiments of the present disclosure are described. The nouns and terms involved in the embodiments of the present disclosure are subject to the following explanations.

[0070] The BMC (Board Management Controller) is integrated on the server motherboard and is the core component of the server management system. It has independent resources such as a processor and memory and is used to monitor and manage the server hardware status. The BMC communicates with the server hardware through the IPMI protocol to implement functions such as device information management, server status monitoring, remote control management, and operation and maintenance management. The BMC can work properly without relying on the server operating system or other hardware components and can work normally when the system is not started.

[0071] CPLD (Complex Programmable Logic Device) is a programmable digital integrated circuit, which is mainly composed of programmable logic macro cells, programmable I / O units, and programmable internal connections inside. Therefore, configuration data can be written into the CPLD through a programming device to define its internal logic functions.

[0072] ADC (Analog-to-Digital Converter) is an electronic device that converts analog signals into digital signals and is the key to the interface between digital circuits and the real world. Its working principle includes four steps: sampling, holding, quantization, and encoding. Through these steps, the ADC converts continuously changing analog signals into discrete digital signals.

[0073] NVRAM (Non-Volatile Random Access Memory) is a type of memory that combines random access and non-volatile characteristics. The working principle of NVRAM is based on charge storage or phase change storage technology, enabling it to retain data even after power-off. Due to the advantages of non-volatility, fast access speed, and high reliability, NVRAM is commonly used in scenarios that require quick startup and persistent storage of system status information.

[0074] CRC checksum (Cyclic Redundancy Check) is an error detection coding technology based on polynomial division, used to verify the integrity of data during transmission or storage. Its core principle is to append a fixed-length checksum (CRC code) to the original data, enabling the receiving end to determine whether the data has been tampered with or has errors through calculation.

[0075] This disclosure provides a server voltage monitoring system, as Figure 1 shown. The system includes a Complex Programmable Logic Device (CPLD) 10, an initial timing module 20, a voltage acquisition module 30, an abnormal data storage module 40, a CPU processor 50, and a Baseboard Management Controller (BMC) module 60 that are respectively communicatively connected to the CPLD 10, where:

[0076] The initial timing module 20 is used to monitor the time window from when the server is powered on until the startup of the Baseboard Management Controller (BMC) module 60 is completed, and activate the monitoring function of the CPLD 10 within this time window.

[0077] In this example, the initial timing module 20 is responsible for monitoring various key signals during the period from when the server is powered on until the startup of the Baseboard Management Controller module is completed, in order to obtain the time window for activating the monitoring function of the CPLD 10, thereby ensuring comprehensive monitoring of the initial state of the server startup. Moreover, the initial timing module 20 records time information in real time during the process of the CPLD 10 monitoring the server voltage, providing an accurate time point basis for subsequent abnormal analysis.

[0078] The voltage acquisition module 30 is used to acquire multi-channel voltage data of the server motherboard power supply and transmit it to the CPLD 10.

[0079] In this example, the voltage acquisition module 30 controls the real-time acquisition of voltage data of the multi-channel power supply of the server motherboard through the CPLD 10. Specifically, the voltage acquisition module 30 acquires the voltage data of each circuit on the server motherboard by responding to the acquisition instruction from the CPLD 10, converts the voltage data from analog signal to digital signal, and then transmits it to the CPLD 10 through the I2C communication interface, providing data input for subsequent abnormal detection.

[0080] The CPLD 10 is used to control the voltage acquisition operation of the voltage acquisition module 30, cache the voltage data into a register, compare the voltage data with a reference voltage range, identify a fluctuating voltage exceeding the reference voltage range, and trigger an interrupt signal.

[0081] In this example, the CPLD 10 selects the CPLD 10 chip LCMXO2-7000HC-4FG484C, which is mainly responsible for controlling the intelligent acquisition of multi-channel voltage data of the server. That is, the CPLD 10 is the main body for controlling the voltage acquisition, replacing the traditional CPU and BMC to control the voltage acquisition operation of the voltage acquisition module 30. Specifically, the CPLD 10 sends an acquisition instruction to the voltage acquisition module 30 to control its execution of the voltage acquisition operation, and after processing the acquired original voltage data, stores it in the register inside the CPLD 10. At the same time, the CPLD 10 reads the preset reference voltage range from the abnormal data storage module 40, and compares the voltage data cached in the register with the reference voltage range. When the voltage data continuously exceeds the reference voltage range for a preset number of times, the CPLD 10 determines that there is an abnormality in the server voltage. At this time, the CPLD 10 triggers an interrupt signal (PWR_INTn) according to the fluctuating voltage, and transmits this signal to the CPU processor 50 and / or the BMC module 60, so that they call the corresponding interrupt handling program for interrupt handling.

[0082] The abnormal data storage module 40 is used to store the reference voltage range in the non-volatile random access memory NVRAM, and alternately store the fluctuating voltage obtained from the CPLD 10 through two of the NVRAMs.

[0083] In this example, the reference voltage ranges of each path of voltage are pre-stored in the NVRAM for the CPLD 10 to read. And, two NVRAMs are set in the abnormal data storage module 40, which are used to alternately write the fluctuating voltage and the time information of the fluctuating voltage provided by the initial timing module 20 into two NVRAM chips after the CPLD 10 detects a fluctuating voltage exceeding the reference voltage range. For example, the fluctuating voltage of the first anomaly and the corresponding time information are written into NVRAM_A, and the next time it is written into NVRAM_B. By circularly overwriting the old data, while avoiding data storage overflow, the conflict of simultaneous access by the CPLD 10 and the BMC module 60 is solved.

[0084] The CPU processor 50 and the BMC module 60 are used to read the voltage data from the register of the CPLD 10, and trigger an interrupt in response to the interrupt signal and feedback the fluctuating voltage.

[0085] In this example, the operation and maintenance personnel will obtain abnormal fluctuating voltage data through different interfaces (local / remote). The CPU processor 50 and the BMC module 60 will respectively respond to the interrupt signal of the CPLD10, trigger the interrupt program, obtain the fluctuating voltage, and give feedback. In addition, the CPU processor 50 and the BMC module 60 can also read the voltage data in real time from the registers of the CPLD10 and display and give feedback in real time through the interface.

[0086] The present disclosure provides a server voltage monitoring system, including a CPLD10, and an initial timing module 20, a voltage acquisition module 30, an abnormal data storage module 40, a CPU processor 50, and a baseboard management controller BMC module 60 that are respectively communicatively connected to the CPLD10. Among them, the initial timing module 20 activates the monitoring function of the CPLD10 through a power-on signal; the voltage acquisition module 30 acquires voltage data under the control of the CPLD10 to realize the reading of voltage data of various types of the server motherboard; the CPLD10 compares the acquired voltage data with the reference voltage range in the abnormal data storage module 40, and triggers an interrupt signal and feeds it back to the CPU and BMC after identifying abnormal fluctuating voltage, so that they can quickly output an alarm. This system covers the full-cycle monitoring from power-on to BMC startup, supports efficient acquisition of multiple paths of voltage, dynamic detection, and low-latency response, alleviates the voltage monitoring pressure of the BMC on the motherboard, and provides a reliable guarantee for the power supply safety of the server.

[0087] In one example, the voltage acquisition module 30 includes a plurality of analog-to-digital converters ADC301, and each of the ADCs is assigned an independent address and is connected to the CPLD10 through an I2C bus for parallel acquisition of voltage data of multiple paths of power supply of the server motherboard.

[0088] In this example, the voltage acquisition module 30 includes a plurality of ADC301s, and each ADC301 is assigned an independent I2C address and is connected to the CPLD10 through an I2C bus for parallel acquisition of voltage data of multiple paths of power supply of the server motherboard. Each ADC301 supports multiple paths of analog voltage input, and the independent address avoids bus conflicts and realizes synchronous acquisition of multiple paths of voltage. For example, by parallel operation of multiple ADC301 chips, the acquisition time of 40 paths of voltage can be reduced to 1 / 5 of that of a single ADC301. The CPLD10 sends acquisition instructions to each ADC301 through the I2C bus and receives the converted digital voltage signal, and the data is stored in the internal register after being processed.

[0089] For example Figure 2The topology diagram of the voltage acquisition module 30 is shown. The voltage acquisition module 30 is composed of 5 ADC301128D818CIMTX chips, which are responsible for acquiring the 40-way main board power supply voltage. The module designs 40 voltage acquisition channels, marked as ADC301_IN[39:0]. Through the I2C_C[4:0] bus, the CPLD10 can send acquisition instructions. According to the I2C addresses of the ADC301 chips (0x3A, 0x3C, 0x3E, 0x6A, 0x6C respectively), the CPLD10 can simultaneously access and read the voltage data of these 5 ADC301 chips, and finally transmit it to the internal register through the parallel bus. Multiple ADC301 chips perform the voltage data acquisition operation in parallel. Compared with the traditional BMC polling method, it significantly reduces the time required for I2C to read the voltage.

[0090] In one example, the CPLD10 communicates with the CPU processor 50 and the BMC module 60 through the I2C protocol, and performs verification processing on the transmitted data based on the multi-byte data group transmission protocol and the cyclic redundancy check code.

[0091] In this example, the CPLD10 communicates with the CPU processor 50 and the BMC module 60 through the I2C protocol, and performs verification on the transmitted data based on the multi-byte data group transmission protocol (I2C_BLOCK protocol) and the cyclic redundancy check code (CRC). The data packet consists of a packet header (identifying the data type and length), a data segment (multi-byte voltage value), and a CRC check field. The sending end (CPLD10) calculates the CRC code before transmission and appends it to the end of the data packet; the receiving end (CPU / BMC) verifies the CRC code after parsing the data. If the verification fails, it triggers the retransmission process through the interrupt signal. This protocol supports batch transmission of multi-byte voltage data, reduces the bus occupancy time, and at the same time, the CRC check provides hardware-level fault tolerance to avoid data errors caused by noise interference.

[0092] In one example, the CPLD10 includes: a first register 101 for storing the voltage data read by the CPU processor 50; a second register 102 for storing the voltage data read by the BMC module 60; the first register 101 and the second register 102 respectively reserve storage spaces for multiple acquisitions of voltage data, and the CPLD10 calculates the voltage data based on the percentage deviation counting method and stores it in the first register 101 and the second register 102 respectively.

[0093] In this example, to avoid data read latency or conflicts when the CPU and BMC obtain voltage data from the same register, physical isolation of the acquired data sources is performed in the CPLD 10, that is, the address space of the first register 101 is set to 0x00 to 0xA27 to store the voltage data that the CPU processor 50 needs to read; the address space of the second register 102 is set to 0x00 to 0xB27 to store the voltage data that the BMC module 60 needs to read. The two are physically isolated and accessed through independent buses (such as Figure 2 and 3 I2C_A and I2C_B in

[0094] ) to avoid read-write conflicts.

[0095] After the CPLD 10 obtains the voltage data from the voltage acquisition module 30, the original voltage data is processed by the percentage deviation counting method, including: adaptively adjusting the sample size through staged data acquisition and deviation range determination to accurately reflect the fluctuation characteristics. The specific process is as follows:

[0096] Staged data acquisition includes: Step 1: Acquire a preset number of voltage data as the basic sample and use it as the benchmark for evaluating the fluctuating voltage. Step 2: Determine the extreme deviation percentage based on the basic sample and determine whether to trigger extended acquisition. Among them, the extreme deviation calculation includes: calculating the extreme deviation percentage based on the ratio of the range (the difference between the maximum value and the minimum value) of the current data set to the minimum value. According to the preset interval where the extreme deviation percentage is located, dynamically adjust the subsequent acquisition strategy to ensure that the data scale matches the fluctuation intensity.

[0097] The above percentage deviation counting method is described in detail by giving examples:

[0098] For example, five voltage data are collected as basic samples and the percentage of extreme value deviation is calculated. If the percentage of extreme value deviation is lower than the first threshold (e.g., 5%), the basic samples are directly adopted. If the percentage of extreme value deviation is between the first threshold and the second threshold (e.g., 5% - 10%), additional extended samples (e.g., 10) are collected, and the basic samples are combined to form a complete data set. If the percentage of extreme value deviation is between the second threshold and the third threshold (e.g., 10% - 20%), additional collection continues until the upper limit of the data scale is met (e.g., 20). If the percentage of extreme value deviation exceeds the third threshold (e.g., 20%), the collection is terminated, the voltage data is determined, and stored in the corresponding register.

[0099] After each data processing is completed, the CPLD10 writes the data into the register and sets the PWR_ADC301_BUSY signal, marking the register status as "update completed"; the CPU processor 50 and the BMC module 60 judge the data readability by monitoring the PWR_ADC301_BUSY signal to avoid reading intermediate state data.

[0100] In one example, the CPLD10 generates a first interrupt signal to trigger the CPU processor 50 to read the fluctuating voltage and the corresponding time information from the abnormal data storage module 40 and display them in the BIOS interface; the CPLD10 generates a second interrupt signal to trigger the BMC module 60 to read the fluctuating voltage from the second register 102 and display it in the Web interface.

[0101] In this example, when the CPLD10 detects that the voltage data of a certain channel on a certain server motherboard exceeds the reference voltage range, it is determined as fluctuating voltage; at the same time, the CPLD10 generates a first interrupt signal by pulling down the level of the PWR_INTn_A pin and notifies the CPU processor 50. The CPU processor 50 responds to the first interrupt signal, interrupts the current task, and accesses the abnormal data storage module 40 through the I2C_A bus to read the fluctuating voltage and the corresponding time information; after parsing the data, the fluctuating voltage and the corresponding time information are displayed in a highlighted form in the BIOS interface through the UEFI driver.

[0102] The second interrupt signal is triggered synchronously with the first interrupt signal. Specifically, the CPLD10 generates a second interrupt signal by pulling down the level of the PWR_INTn_B pin and notifies the BMC module 60. The BMC module 60 responds to the second interrupt signal, reads the filtered fluctuating voltage of the second register 102 through the I2C_B bus, and integrates the data into the Web interface of the BMC to display the voltage status in real time.

[0103] In one example, the BMC module 60 is further configured to dynamically adjust the reference voltage range in the abnormal data storage module 40 according to the ambient temperature, including: the BMC module 60 reads the temperature sensor data and dynamically adjusts the reference voltage range according to the ambient temperature.

[0104] In this example, changes in the ambient temperature may cause fluctuations in the supply voltage, and fixed thresholds are prone to false alarms. The BMC module 60 dynamically adjusts the reference voltage range according to the ambient temperature. Specifically, after the BMC is started, it reads the temperature sensor data and calculates the reference voltage offset corresponding to the current temperature based on a preset temperature-voltage compensation algorithm (such as a linear offset model), and updates the reference voltage range in the abnormal data storage module 40. For example, for every 10°C increase in temperature, the upper limit of the reference voltage increases by 0.05V to adapt to the voltage fluctuations caused by changes in the internal resistance of the power supply module and reduce misjudgments caused by environmental interference.

[0105] In one example, the system further includes: a power status monitoring module 70, configured to collect the enable signal and the power normal signal of the voltage acquisition module 30 and transmit the signal status to the CPLD 10.

[0106] In this example, the system further includes a power status monitoring module 70, configured to collect the enable signal (Enable, EN) and the power normal signal (Power Good, PG) of the voltage generation module and transmit the signal status to the CPLD 10. The power status monitoring module 70 converts the analog signals of EN and PG into high and low level digital signals through a level conversion circuit. The CPLD 10 determines whether the power supply module is abnormally disabled according to the EN signal and whether the output voltage meets the standard according to the PG signal. If the EN signal is low level and the PG signal is abnormal, the CPLD 10 triggers an interrupt and marks the fault channel number of the power supply module to achieve accurate fault location.

[0107] As Figure 3 shown in the topology diagram of the power status monitoring module 70, the CPLD can read the PG status of each voltage through I2C_D[2:0]. Under normal circumstances, it is high level, and in abnormal cases, a low level is read.

[0108] In one example, the system further includes: an LED status indication module 80, where the LED status indication module 80 includes a multi-segment digital tube; when the power status monitoring module 70 detects a power abnormality signal, the CPLD 10 controls the LED status indication module 80 to display the abnormal channel number; when the CPLD 10 detects a fluctuating voltage, it controls the LED status indication module 80 to flash and display the abnormal channel number at a frequency corresponding to the number of fluctuations.

[0109] In this example, the LED status indication module 80 adopts a multi-segment digital tube design to indicate whether there is an abnormality or a fluctuation status in the current voltage supply. When the CPLD 10 monitors that there is no abnormality in the power supply module status monitoring, it displays "FF". FF corresponds to the full segment lighting of the digital tube, indicating no abnormal status. When the CPLD 10 monitors that any power PG signal in the power supply module status monitoring is abnormal, the CPLD 10 will control the LED status indication module 80 to display the specific channel value of the channel. For example, when channel 3 is displayed as "03", it indicates that there is a voltage fault in the main board voltage. When the CPLD 10 monitors that the fluctuating voltage of a certain path has fluctuated N times, at this time, the LED status indication module 80 will flash and display the specific channel value at the same frequency as the number of fluctuations. For example, when it is detected that there are 2 fluctuating voltages in a certain path, the LED status indication module 80 will flash the corresponding channel value at a frequency of 2 Hz. And so on, when it is detected that there are 10 or more voltage fluctuations in this channel, the LED status indication module 80 will flash the corresponding channel value at a maximum frequency of 10 Hz.

[0110] In one example, the CPU processor 50 and the BMC module 60 respectively control the channel enable status of the voltage acquisition module 30 through the register enable control ports.

[0111] In this example, the CPU processor 50 and the BMC module 60 need to selectively monitor specific power supply nodes in different operation and maintenance scenarios. Therefore, the CPU processor 50 and the BMC module 60 respectively send control instructions through independent register enable control ports (such as PWR_CN_EN_A, PWR_CN_EN_B). After analyzing the control instructions, the CPLD 10 enables or disables the corresponding acquisition channels. For example, the register enable control instruction maps to the corresponding channel number through binary bits. For example, 0x01 corresponds to channel 1, and 0x02 corresponds to channel 2; sending 0x3F enables all channels. The dual control port design allows the CPU and the BMC to independently manage the monitoring range, supporting both a full-scale inspection and targeted monitoring of the faulty channels, improving the operation and maintenance efficiency.

[0112] In one example, the initial timing module 20 monitors the server power-on signal, the server reset signal, the BMC startup signal, the BMC reset signal, and the I2C clock signal to determine the time window.

[0113] In this example, monitoring tasks cannot be performed during the BMC startup. Therefore, the initial timing module 20 is required to clarify the monitoring period of the CPLD10. The initial timing module 20 monitors the server power-on signal, the server reset signal, the BMC startup signal (BOOT_OK), the reset signal (BOOT_RSTn), and the I2C clock signal in real time to determine the time window from power-on to BMC readiness, so that the CPLD10 can independently perform monitoring within this window, avoid data loss when the BMC has not started, and ensure voltage stability guarantee covering the entire cycle.

[0114] The present disclosure also provides a server voltage monitoring method, as Figure 4 shown, the method includes:

[0115] Step 401: Monitor the time window from the server power-on to the completion of the startup of the baseboard management controller BMC module, and activate the monitoring function of the complex programmable logic device CPLD within the time window.

[0116] In this example, multiple key signals during the period from the server power-on to the completion of the startup of the baseboard management controller module are monitored to obtain the time window for activating the monitoring function of the CPLD, thereby ensuring comprehensive monitoring of the initial state of the server startup. Moreover, time information is recorded in real time during the process of the CPLD monitoring the server voltage, providing an accurate time point basis for subsequent anomaly analysis.

[0117] Step 402: Control multiple analog-to-digital converters ADCs through the CPLD to collect multiplexed voltage data of the server motherboard power supply, cache the voltage data into a register, and compare it with the reference voltage range stored in the non-volatile random access memory NVRAM to identify the fluctuating voltage exceeding the range and trigger an interrupt signal.

[0118] In this example, multiple ADCs are controlled by the CPLD to collect voltage data of the multiplexed power supplies of the server motherboard in real time. Specifically, the multiple ADCs collect voltage data of each circuit on the server motherboard by responding to the voltage acquisition operation from the CPLD, convert the voltage data from an analog signal to a digital signal, and then transmit it to the CPLD through the I2C communication interface, providing data input for subsequent anomaly detection.

[0119] The CPLD selects the CPLD chip LCMXO2-7000HC-4FG484C, which is mainly responsible for controlling the intelligent acquisition of multiplexed voltage data of the server, that is, using the CPLD as the main body to control the voltage data acquisition, replacing the traditional CPU and BMC to control the voltage acquisition operations of multiple ADCs. Specifically, the CPLD sends acquisition instructions to multiple ADCs to control their voltage acquisition operations, and after processing the acquired original voltage data, stores it in the registers inside the CPLD. The reference voltage ranges of each path of voltage are pre-stored in the NVRAM. The CPLD reads the preset reference voltage range from the NVRAM, and compares the voltage data cached in the register with the reference voltage range. When the voltage data continuously exceeds the reference voltage range for a preset number of times, the CPLD determines that there is an abnormality in the server voltage. At this time, the CPLD triggers an interrupt signal (PWR_INTn) according to the fluctuating voltage, and transmits this signal to the CPU processor and / or BMC module, so that it calls the corresponding interrupt handling program for interrupt handling.

[0120] Step 403: Alternately store the fluctuating voltage through two NVRAMs.

[0121] In this example, two NVRAMs are set up to alternately write the fluctuating voltage and the time information of the fluctuating voltage into two NVRAM chips after the CPLD detects the fluctuating voltage exceeding the reference voltage range. For example, the first abnormal fluctuating voltage and the corresponding time information are written into NVRAM_A, and the next time it is written into NVRAM_B. By cycling to overwrite the old data, it can avoid data storage overflow while solving the conflict of simultaneous access by the CPLD and BMC module.

[0122] Step 404: The CPU processor and BMC module read the voltage data from the registers of the CPLD, and trigger an interrupt in response to the interrupt signal and feedback the fluctuating voltage.

[0123] In this example, the operation and maintenance personnel will obtain the abnormal fluctuating voltage data through different interfaces (local / remote). The CPU processor and BMC module will respectively respond to the interrupt signal of the CPLD, trigger the interrupt program and obtain the fluctuating voltage for feedback. In addition, the CPU processor and BMC module can also read the voltage data from the registers of the CPLD in real time and perform real-time display feedback through the interface.

[0124] In one example, the acquisition of multiplexed voltage data of the main board power supply of the server includes:

[0125] Parallelly acquire multiplexed voltage data of the main board power supply of the server through multiple ADCs, and each of the ADCs is assigned an independent address and connected to the CPLD through the I2C bus.

[0126] In this example, each ADC is assigned an independent I2C address and connected to the CPLD via the I2C bus for parallel acquisition of multiplexed voltage data of the server motherboard power supply. Each ADC supports multiple analog voltage inputs, and the independent addresses avoid bus conflicts and enable synchronous acquisition of multiplexed voltages. For example, by having multiple ADC chips work in parallel, the acquisition time for 40 channels of voltage can be reduced to 1 / 5 of that of a single ADC. The CPLD sends acquisition commands to each ADC via the I2C bus and receives the converted digital voltage signals, which are stored in internal registers after being processed.

[0127] For example Figure 2 As shown, it consists of 5 ADC128D818CIMTX chips responsible for acquiring 40 channels of motherboard power supply voltages. It has 40 voltage acquisition channels designed, labeled as ADC_IN[39:0]. Through the I2C_C[4:0] bus, the CPLD can send acquisition commands. Based on the I2C addresses of the ADC chips (0x3A, 0x3C, 0x3E, 0x6A, 0x6C respectively), the CPLD can simultaneously access and read the voltage data of these 5 ADC chips, and finally transmit it to its internal registers via a parallel bus. Multiple ADC chips perform voltage data acquisition operations in parallel, significantly reducing the time required for I2C to read voltages compared to the traditional BMC polling method.

[0128] In one example, the CPLD communicates with the CPU processor and the BMC module via the I2C protocol, and performs verification processing on the transmitted data based on the multi-byte data group transmission protocol and the cyclic redundancy check code.

[0129] In this example, the CPLD communicates with the CPU processor and the BMC module via the I2C protocol, and performs verification on the transmitted data based on the multi-byte data group transmission protocol (I2C_BLOCK protocol) and the cyclic redundancy check code (CRC). The data packet consists of a packet header (identifying the data type and length), a data segment (multi-byte voltage values), and a CRC check field. The sending end (CPLD) calculates the CRC code before transmission and appends it to the end of the data packet; the receiving end (CPU / BMC) verifies the CRC code after parsing the data. If the verification fails, a retransmission process is triggered via an interrupt signal. This protocol supports batch transmission of multi-byte voltage data, reducing the bus occupancy time. At the same time, the CRC check provides hardware-level fault tolerance to avoid data errors caused by noise interference.

[0130] In one example, the CPLD caches the voltage data in a register, including: storing the voltage data read by the CPU processor in the first register of the CPLD; storing the voltage data read by the BMC module in the second register of the CPLD; the first register and the second register respectively reserve storage spaces for collecting voltage data multiple times, and the CPLD calculates the voltage data based on the percentage deviation counting method and then stores them in the first register and the second register respectively.

[0131] In this example, to avoid data read delay or conflict when the CPU and the BMC obtain voltage data from the same register, in this example, physical isolation of the acquired data sources is performed in the CPLD, that is, the address space of the first register is set to 0x00 to 0xA27 to store the voltage data that the CPU processor needs to read; the address space of the second register is set to 0x00 to 0xB27 to store the voltage data that the BMC module needs to read. The two are physically isolated and accessed through independent buses (such as I2C_A and I2C_B), thus avoiding read-write conflicts.

[0132] In addition, storage spaces for collecting data multiple times are also reserved in each register. Taking the first register reserving storage spaces for collecting data five times as an example: the address space of the first register will be divided into 0x27 to 0x00 (the 1st time), 0x57 to 0x30 (the 2nd time), 0x87 to 0x60 (the 3rd time), 0xB7 to 0x90 (the 4th time), 0xE7 to 0xC0 (the 5th time). Similarly, the voltage data obtained by the second register each time is stored in the corresponding address to ensure data synchronization.

[0133] After the CPLD obtains the voltage data, it processes the original voltage data through the percentage deviation counting method, including: adaptively adjusting the sample size through staged data acquisition and deviation range determination to accurately reflect the fluctuation characteristics. The specific process is as follows:

[0134] Staged data acquisition includes: Step 1: Collect a preset number of voltage data as basic samples and use them as the benchmark for evaluating the fluctuating voltage. Step 2: Determine the extreme deviation percentage based on the basic samples and determine whether to trigger extended acquisition. Among them, the extreme deviation calculation includes: calculating the extreme deviation percentage based on the ratio of the range (the difference between the maximum value and the minimum value) of the current data set to the minimum value. According to the preset interval where the extreme deviation percentage is located, dynamically adjust the subsequent acquisition strategy to ensure that the data size matches the fluctuation intensity.

[0135] The above percentage deviation counting method is described in detail by giving examples:

[0136] For example, collect 5 voltage data as the basic samples and calculate the percentage of extreme value deviation. If the percentage of extreme value deviation is lower than the first threshold (e.g., 5%), directly use the basic samples. If the percentage of extreme value deviation is between the first threshold and the second threshold (e.g., 5% - 10%), additionally collect extended samples (e.g., 10), and merge the basic samples to form a complete data set. If the percentage of extreme value deviation is between the second threshold and the third threshold (e.g., 10% - 20%), continue to additionally collect until the upper limit of the data scale is met (e.g., 20). If the percentage of extreme value deviation exceeds the third threshold (e.g., 20%), terminate the collection, determine the voltage data, and store it in the corresponding register.

[0137] After each data processing is completed, the CPLD writes the data into the register and sets the PWR_ADC_BUSY signal, marking the register status as "update completed"; the CPU processor and the BMC module determine the data readability by monitoring the PWR_ADC_BUSY signal to avoid reading intermediate state data.

[0138] In one example, the CPLD triggering the interrupt signal includes: generating a first interrupt signal through the CPLD to trigger the CPU processor to read the fluctuating voltage and the corresponding time information from the NVRAM and display them in the BIOS interface; generating a second interrupt signal through the CPLD to trigger the BMC module to read the fluctuating voltage from the second register and display it in the Web interface.

[0139] In this example, when the CPLD detects that the voltage data of a certain channel on a certain server motherboard exceeds the reference voltage range, it is determined as the fluctuating voltage; at the same time, the CPLD generates a first interrupt signal by pulling down the level of the PWR_INTn_A pin and notifies the CPU processor. The CPU processor responds to the first interrupt signal, interrupts the current task, and accesses the NVRAM through the I2C_A bus to read the fluctuating voltage and the corresponding time information; after parsing the data, the fluctuating voltage and the corresponding time information are highlighted and displayed in the BIOS interface through the UEFI driver.

[0140] The second interrupt signal is triggered synchronously with the first interrupt signal. Specifically, the CPLD generates a second interrupt signal by pulling down the level of the PWR_INTn_B pin and notifies the BMC module. The BMC module responds to the second interrupt signal, reads the filtered fluctuating voltage of the second register through the I2C_B bus, and integrates the data into the Web interface of the BMC to display the voltage status in real time.

[0141] In one example, the method further includes: reading the temperature sensor data through the BMC module and dynamically adjusting the reference voltage range according to the ambient temperature.

[0142] In this example, changes in the ambient temperature may cause fluctuations in the supply voltage, and fixed thresholds are prone to false alarms. The BMC module dynamically adjusts the reference voltage range according to the ambient temperature, specifically including: after the BMC starts, it reads the data of the temperature sensor and calculates the reference voltage offset corresponding to the current temperature based on a preset temperature-voltage compensation algorithm (such as a linear offset model), and updates the reference voltage range in the NVRAM. For example, for every 10°C increase in temperature, the upper limit of the reference voltage increases by 0.05V to adapt to the voltage fluctuations caused by the change in the internal resistance of the power supply module and reduce misjudgments caused by environmental interference.

[0143] In one example, the method further includes: collecting the enable signals and power normal signals of the multiple ADCs and transmitting the signal states to the CPLD.

[0144] In this example, the enable signals (Enable, EN) and power normal signals (Power Good, PG) of multiple ADCs are collected, and the signal states are transmitted to the CPLD. The analog signals of EN and PG are converted into high and low level digital signals through a level conversion circuit. The CPLD determines whether the power supply module is abnormally disabled according to the EN signal and whether the output voltage meets the standard according to the PG signal. If the EN signal is at a low level and the PG signal is abnormal, the CPLD triggers an interrupt and marks the fault channel number of the power supply module to achieve precise fault location.

[0145] In one example, the method further includes: when a power anomaly signal is detected, controlling a multi-segment digital tube to display the abnormal channel number through the CPLD; when a fluctuating voltage is detected, controlling the multi-segment digital tube to flash and display the abnormal channel number at a frequency corresponding to the number of fluctuations through the CPLD.

[0146] In this example, a multi-segment digital tube design is adopted to indicate whether there are any abnormalities and fluctuating states in the current voltage supply. When the CPLD monitors that there are no abnormalities in the power supply module status monitoring, it displays "FF", and FF corresponds to all segments of the digital tube being lit, indicating no abnormal status. When the CPLD monitors that any power PG signal in the power supply module status monitoring is abnormal, the CPLD will control the multi-segment digital tube to display the specific channel value of the channel. For example, when channel 3 is displayed as "03", it indicates that there is a voltage fault in the motherboard voltage. When the CPLD monitors that a certain fluctuating voltage has fluctuated N times, at this time, the multi-segment digital tube will flash and display the specific channel value at the same frequency as the number of fluctuations. For example, when it is detected that a certain path has had 2 fluctuating voltages, the multi-segment digital tube will flash the corresponding channel value at a frequency of 2Hz, and so on. When it is detected that the channel has had 10 or more voltage fluctuations, the multi-segment digital tube will flash the corresponding channel value at a maximum frequency of 10Hz.

[0147] In one example, the method further includes: controlling the channel enable states of the plurality of ADCs respectively through the register enable control ports by the CPU processor and the BMC module.

[0148] In this example, the CPU processor and the BMC module need to selectively monitor specific power supply nodes in different operation and maintenance scenarios. Therefore, the CPU processor and the BMC module respectively send control instructions through independent register enable control ports (such as PWR_CN_EN_A, PWR_CN_EN_B). After analyzing the control instructions, the CPLD enables or disables the corresponding acquisition channels. For example, the register enable control instruction maps to the corresponding channel number through binary bits. For example, 0x01 corresponds to channel 1, and 0x02 corresponds to channel 2; sending 0x3F enables all channels. The dual control port design allows the CPU and the BMC to independently manage the monitoring scope, supporting both full-scale troubleshooting and targeted monitoring of faulty channels, thus improving the operation and maintenance efficiency.

[0149] In one example, the time window from when the monitoring server is powered on until the substrate management controller BMC module starts up is completed includes: determining the monitoring time window of the CPLD before the BMC module starts up is completed through the monitoring server power-on signal, the server reset signal, the BMC start signal, the BMC reset signal, and the I2C clock signal.

[0150] In this example, the monitoring task cannot be executed during the BMC startup. Therefore, it is necessary to clarify the monitoring period of the CPLD. By real-time monitoring the server power-on signal, the server reset signal, the BMC start signal (BOOT_OK) and the reset signal (BOOT_RSTn), and the I2C clock signal, the time window from power-on to BMC readiness is determined, so that the CPLD can independently execute monitoring within this window, avoiding data loss when the BMC has not started, and ensuring voltage stability guarantee for the full cycle coverage.

[0151] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

[0152] Figure 5 FIG. shows a schematic block diagram of an exemplary electronic device 800 that can be used to implement the embodiments of the present disclosure. The electronic device is intended to represent various forms of digital computers, such as, a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, a personal digital processor, a cellular phone, a smart phone, a wearable device, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely exemplary and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0153] As Figure 5 shown, the electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0154] Multiple components in the device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, an optical disc, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0155] The computing unit 801 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include but are not limited to a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 801 executes the various methods and processes described above, such as the server voltage monitoring method. For example, in some embodiments, the server voltage monitoring method can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed onto the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the server voltage monitoring method described above can be executed. Alternatively, in other embodiments, the computing unit 801 can be configured to execute the server voltage monitoring method by any other appropriate means (e.g., by means of firmware).

[0156] The various embodiments of the systems and techniques described above in this specification can be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be a special-purpose or general-purpose programmable processor that receives data and instructions from, and transmits data and instructions to, a storage system, at least one input device, and at least one output device.

[0157] The program code for implementing the methods of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions / operations specified in the flowchart and / or block diagram to be implemented. The program code can be executed entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine, or entirely on the remote machine or server.

[0158] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0159] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and a pointing device (e.g., a mouse or a trackball) through which the user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, speech input, or tactile input).

[0160] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), and the Internet.

[0161] A computer system can include a client and a server. The client and the server are generally far from each other and usually interact through a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, or a server of a distributed system, or a server incorporating a blockchain.

[0162] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and no limitations are imposed herein.

[0163] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of this disclosure, "a plurality of" means two or more unless otherwise specifically defined.

[0164] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claimed rights.

Claims

1. A server voltage monitoring system, characterized in that, The system includes a Complex Programmable Logic Device (CPLD), an initial timing module, a voltage acquisition module, an abnormal data storage module, a CPU processor, and a Baseboard Management Controller (BMC) module that are respectively communicatively connected to the CPLD, where: The initial timing module is used to monitor the time window from when the server is powered on to when the BMC module starts up, and activate the monitoring function of the CPLD within the time window; The voltage acquisition module is used to acquire multi-channel voltage data of the server motherboard power supply and transmit it to the CPLD; The CPLD is used to control the voltage acquisition operation of the voltage acquisition module, cache the voltage data into a register; compare the voltage data with a reference voltage range, identify the fluctuating voltage exceeding the reference voltage range, and trigger an interrupt signal; The abnormal data storage module is used to store the reference voltage range in a Non-Volatile Random Access Memory (NVRAM), and alternately store the fluctuating voltage obtained from the CPLD through two of the NVRAMs; The CPU processor and the BMC module are used to read the voltage data from the register of the CPLD, and trigger an interrupt and feedback the fluctuating voltage in response to the interrupt signal.

2. The system according to claim 1, wherein The voltage acquisition module includes multiple Analog-to-Digital Converters (ADCs), each of which is assigned an independent address and connected to the CPLD through an I2C bus, and is used to parallelly acquire multi-channel voltage data of the server motherboard power supply.

3. The system according to claim 1, wherein, The CPLD communicates with the CPU processor and the BMC module through the I2C protocol, and performs error checking processing on the transmitted data based on a multi-byte data group transmission protocol and a Cyclic Redundancy Check (CRC) code.

4. The system according to claim 1, characterized in that, The CPLD includes: A first register for storing the voltage data read by the CPU processor; A second register for storing the voltage data read by the BMC module; The first register and the second register respectively reserve storage spaces for acquiring voltage data multiple times, and the CPLD calculates the voltage data based on a percentage deviation counting method and stores it into the first register and the second register respectively.

5. The system according to claim 4, wherein The CPLD generates a first interrupt signal, triggers the CPU processor to read the fluctuating voltage and the corresponding time information from the abnormal data storage module, and displays them in the BIOS interface; The CPLD generates a second interrupt signal, triggers the BMC module to read the fluctuating voltage from the second register, and displays it in the Web interface.

6. The system according to claim 1, wherein The BMC module is further used to dynamically adjust the reference voltage range in the abnormal data storage module according to the ambient temperature, including: the BMC module reads the temperature sensor data and dynamically adjusts the reference voltage range according to the ambient temperature.

7. The system according to claim 1, wherein The system further includes: a power status monitoring module, which is used to acquire the enable signal and the power normal signal of the voltage acquisition module, and transmit the signal status to the CPLD.

8. The system according to claim 7, wherein The system further includes: an LED status indication module, and the LED status indication module includes a multi-segment digital tube; When the power status monitoring module detects a power anomaly signal, the CPLD controls the LED status indication module to display the abnormal channel number; When the CPLD detects a fluctuating voltage, it controls the LED status indication module to flash and display the abnormal channel number at a frequency corresponding to the number of fluctuations.

9. The system according to claim 1, characterized in that, The CPU processor and the BMC module respectively control the channel enable status of the voltage acquisition module through the register enable control ports.

10. The system according to claim 1, wherein The initial timing module determines the time window by monitoring the server power-on signal, the server reset signal, the BMC start signal, the BMC reset signal, and the I2C clock signal.

11. A server voltage monitoring method, characterized in that, The method includes: Monitoring the time window from when the server is powered on until the start-up of the baseboard management controller (BMC) module is completed, and activating the monitoring function of the complex programmable logic device (CPLD) within this time window; Controlling, through the CPLD, multiple analog-to-digital converters (ADCs) to collect multi-channel voltage data of the server motherboard power supply, caching the voltage data in a register, and comparing it with the reference voltage range stored in the non-volatile random access memory (NVRAM) to identify fluctuating voltages outside the range and trigger an interrupt signal; Storing the fluctuating voltages alternately in two NVRAMs; Reading the voltage data from the register of the CPLD by the CPU processor and the BMC module, and triggering an interrupt and feeding back the fluctuating voltage in response to the interrupt signal.

12. The method according to claim 11, characterized in that Collecting the multi-channel voltage data of the server motherboard power supply includes: Parallelly collecting the multi-channel voltage data of the server motherboard power supply through multiple ADCs, each ADC being assigned an independent address and connected to the CPLD via the I2C bus.

13. The method according to claim 11, wherein The CPLD communicates with the CPU processor and the BMC module through the I2C protocol, and performs error checking on the transmitted data based on the multi-byte data group transmission protocol and the cyclic redundancy check code.

14. The method according to claim 11, wherein The CPLD caching the voltage data in a register includes: Storing the voltage data read by the CPU processor in the first register of the CPLD; Storing the voltage data read by the BMC module in the second register of the CPLD; The first register and the second register respectively reserve storage spaces for collecting voltage data multiple times, and the CPLD calculates the voltage data based on the percentage deviation counting method and stores it in the first register and the second register respectively.

15. The method according to claim 14, wherein The CPLD triggering the interrupt signal includes: Generating a first interrupt signal through the CPLD to trigger the CPU processor to read the fluctuating voltage and the corresponding time information from the NVRAM and display it in the BIOS interface; Generating a second interrupt signal through the CPLD to trigger the BMC module to read the fluctuating voltage from the second register and display it in the Web interface.

16. The method according to claim 11, characterized in that, The method further includes: Reading the temperature sensor data through the BMC module and dynamically adjusting the reference voltage range according to the ambient temperature.

17. The method according to claim 11, wherein The method further includes: Collecting the enable signals and the power normal signals of the multiple ADCs and transmitting the signal status to the CPLD.

18. The method according to claim 17, wherein The method further includes: When an abnormal power supply signal is detected, the CPLD controls the multi-segment digital tube to display the abnormal channel number; When a fluctuating voltage is detected, the CPLD controls the multi-segment digital tube to flash and display the abnormal channel number at a frequency corresponding to the number of fluctuations.

19. The method according to claim 11, wherein The method further comprises: The CPU processor and the BMC module respectively control the channel enable states of the multiple ADCs through register enable control ports.

20. The method according to claim 11, wherein The monitoring server is powered on to the time window when the baseboard management controller BMC module is started, including: The server power-on signal and server reset signal, the BMC start signal and BMC reset signal, and the I2C clock signal are monitored to determine the time window.

21. An electronic device, characterized in that, include: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 11 to 20.

22. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the method according to any one of claims 11-20.

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