A PCIe-based high-speed data transmission method, device and system

Abstract

The application discloses a PCIe-based high-speed data transmission method, device and system. The PCIe-based high-speed data transmission method comprises the following steps: determining a host device and a slave device in a PCIe link in advance, wherein the host device and the slave device comprise a standard mode and a high-speed mode; when the host device is in the standard mode, a transaction request layer of the host device sends an open high-speed mode request to a data link layer thereof; the data link layer of the host device judges whether the high-speed mode is supported according to a current link state thereof, and if yes, the data link layer of the host device sends the open high-speed mode request to the slave device; the data link layer of the slave device judges whether the high-speed mode is supported according to a current link state of the slave device after receiving the open high-speed mode request, and if yes, the data link layer of the slave device returns a first agreement signal to the host device; and the host device starts the high-speed mode in response to receiving the first agreement signal. The application can more reasonably and efficiently perform high-speed data transmission.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a PCIe-based high-speed data transmission method, device, and system. Background Art

[0002] In modern computer architectures, the efficiency and speed of data transmission have become key performance indicators. With the continuous evolution of computer technology, the demand for data transmission has exploded across various fields, especially in big data processing and high-performance computing.

[0003] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard. It relies on SERDES (Serializer / Deserializer) technology to achieve high-speed serial data transmission, converting parallel data into serial data for long-distance transmission and then restoring it to parallel data for processing at the receiving end. Due to its superior performance, PCIe occupies a core position in numerous computing devices such as personal computers, servers, and workstations, providing a stable, high-speed connection channel for various expansion cards and devices.

[0004] Currently, PCIe devices generally use fixed configuration schemes or simple automatic detection mechanisms to switch between high-speed modes. For example, most devices rely on a fixed, pre-set option in the BIOS to determine whether to activate high-speed mode, but lack the flexibility to switch modes based on dynamic factors such as the link's real-time transmission status, the device's instantaneous processing performance, and data flow. This can easily result in devices failing to fully exploit the potential of high-speed mode in specific scenarios. It can even negatively impact the stability and accuracy of data transmission by forcing high-speed mode into inappropriate situations.

[0005] The disclosure of the above background technology content is only used to assist in understanding the inventive concept and technical solution of the present invention. It does not necessarily belong to the prior art of the present application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above content has been disclosed before the filing date of the present application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the Invention

[0006] The purpose of the present invention is to provide a PCIe-based high-speed data transmission method, device and system, which can perform high-speed data transmission more reasonably and efficiently.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] A high-speed data transmission method based on PCIe, comprising the following steps:

[0009] A master device and a slave device in a PCIe link are pre-determined, wherein the master device and the slave device include a standard mode and a high-speed mode, and the data transmission speed corresponding to the high-speed mode is greater than the data transmission speed corresponding to the standard mode; wherein the standard mode is the PCIe standard mode, and the high-speed mode generally refers to a mode in which a higher data transmission rate than the standard mode is achieved in certain specific application scenarios, PCIe links, or devices by optimizing hardware design, adopting more advanced signal processing technology, or increasing link width. For example, in the standard mode of PCIe 5.0, the transmission rate of each channel is less than or equal to 32 GT / s, while in the corresponding high-speed mode, the transmission rate of each channel is not less than 32 GT / s;

[0010] When the master device is in standard mode, the transaction layer of the master device sends a high-speed mode start request to its data link layer;

[0011] In response to receiving the high-speed mode start request, the data link layer of the master device determines whether the high-speed mode is supported according to its current link state, and if supported, the data link layer of the master device sends the high-speed mode start request to the slave device;

[0012] In response to receiving the high-speed mode start request, the data link layer of the slave device determines whether the high-speed mode is supported according to its current link state, and if supported, the data link layer of the slave device returns a first consent signal to the master device;

[0013] In response to receiving the first consent signal, the master device starts the high-speed mode.

[0014] Furthermore, any one of the above technical solutions or a combination of multiple technical solutions may further include the following steps:

[0015] The master device replies with a second consent signal to the slave device while starting the high-speed mode;

[0016] In response to receiving the second consent signal, the slave device starts the high-speed mode.

[0017] Furthermore, based on any one of the above technical solutions or a combination of multiple technical solutions, the master device / slave device starts the high-speed mode in the following manner:

[0018] The transaction layer of the master device / slave device updates the transaction processing strategy to match the high-speed mode, including adjusting the frequency of sending data and increasing the upper limit of the number of transaction requests; and / or,

[0019] The data link layer of the master device / slave device reconfigures data transmission parameters to match the high-speed mode, including: adjusting the flow upper limit and error control parameters; and / or,

[0020] The physical layer optimization signal reception parameters of the master device / slave device include: equalization parameters, clock data recovery parameters and data sampling parameters.

[0021] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions described above, when the data link layer of the master device sends the high-speed mode start request to the slave device, the transaction layer of the master device waits for the slave device to return a first approval signal or a rejection signal, and during the waiting process, the physical layer of the master device maintains the standard mode, and the data link layer of the master device suspends the sending of user service data.

[0022] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, when the master device and the slave device enter the high-speed mode, one of the master device and the slave device is a transmitter and the other is a receiver, and the transmitter transmits data to the receiver in the following manner:

[0023] The transaction layer of the sending end adds a header and a CRC1 check to the target transmission data to obtain first data, and sends the first data to the data link layer of the sending end;

[0024] The data link layer of the transmitting end verifies the first data, and after the verification passes, first deletes the CRC1 check in the first data and then adds the CRC2 check to obtain second data, and transmits the second data to the physical layer of the transmitting end;

[0025] The physical layer of the transmitting end adds STAR and END tags to the second data to obtain third data, and transmits the third data to the receiving end.

[0026] Furthermore, based on any one of the above technical solutions or a combination of multiple technical solutions, the receiving end receives the target transmission data in the following manner:

[0027] The physical layer of the receiving end receives the third data and decodes the data, including removing STAR and END flags in the third data to obtain fourth data, and transmitting the fourth data to the data link layer of the receiving end;

[0028] The data link layer of the receiving end receives the fourth data, performs a CRC2 check on the fourth data, deletes the CRC2 check in the fourth data if the check passes to obtain fifth data, and transmits the fifth data to the transaction layer of the receiving end;

[0029] The transaction layer of the receiving end receives the fifth data, extracts the payload in the fifth data, obtains the transferred data, and the data reception is completed.

[0030] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, after the data link layer of the transmitting end deletes the CRC1 check in the first data, it adds a Sequence flag while adding the CRC2 check to obtain the second data;

[0031] The physical layer of the receiving end receives the target transmission data in sequence according to the Sequence flag, STAR and END flag in the third data.

[0032] Further, according to any one of the above technical solutions or a combination of multiple technical solutions, the transaction layer of the receiving end sends a data reception completion signal to the sending end after confirming that the data reception is completed;

[0033] In response to receiving the data reception completion signal, the transmitting end self-checks whether there is other data to be sent. If not, the transmitting end switches to standard mode and sends a request to end high-speed mode to the receiving end. In response to receiving the request to end high-speed mode, the receiving end switches to standard mode.

[0034] Furthermore, any one of the above technical solutions or a combination of multiple technical solutions may further include the following steps:

[0035] When the master device and the slave device are in high-speed mode, the master device and the slave device monitor the link status of their own data link layers in real time;

[0036] When the link status of the data link layer of any of the two devices, the master device and the slave device, meets one of the following conditions:

[0037] The link traffic is lower than the preset traffic threshold;

[0038] The number of data errors exceeds a preset first threshold;

[0039] The bit error rate is higher than a preset first bit error rate threshold;

[0040] The data transmission amount is lower than a preset first rate threshold;

[0041] The device that meets one of the above conditions exits the high-speed mode to switch to the standard mode, and sends a request to exit the high-speed mode to the other device.

[0042] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, when the master device / slave device is in high-speed mode, if one of the following conditions is met:

[0043] The data transmission delay is greater than a preset first duration threshold;

[0044] The data retransmission rate is greater than a preset first retransmission rate threshold;

[0045] The master device / slave device then exits the high-speed mode to switch to the standard mode.

[0046] Furthermore, based on any one of the above technical solutions or a combination of multiple technical solutions, predetermining the master device and the slave device in the PCIe link includes:

[0047] An upstream device in a PCIe link is determined to be the master device, and a downstream device in the PCIe link is determined to be the slave device.

[0048] Furthermore, based on any one of the above technical solutions or a combination of multiple technical solutions, whether the current link state supports the high-speed mode is evaluated in the following manner:

[0049] Obtaining the current link status, including the current data transmission rate, available space in the receiving end buffer, number of data transmission errors, and bit error rate;

[0050] If the current data transmission rate meets the requirements of not higher than the preset second rate threshold, the available space of the receiving end cache is not lower than the preset storage space, the number of data transmission errors is lower than the preset second number threshold and the bit error rate is not lower than the preset bit error rate threshold, then it is determined that the current link status supports high-speed mode; otherwise, it is determined that the current link status does not support high-speed mode.

[0051] According to another aspect of the present invention, a data transmission device is provided, which is configured to perform data transmission based on the PCIe-based high-speed data transmission method as described in any one of the above technical solutions or a combination of multiple technical solutions.

[0052] According to another aspect of the present invention, a computer system is provided, comprising the data transmission device as described in any one of the above technical solutions or a combination of multiple technical solutions.

[0053] The beneficial effects brought about by the technical solution provided by the present invention are as follows:

[0054] a. The present invention predetermines the master and slave devices in a PCIe link. The link status of the master device is usually more resource-constrained than that of the slave device. The master device always sends a high-speed mode activation request to the slave device. The master device's link status is first evaluated. If the master device's link status does not support high-speed mode activation, no high-speed mode activation request is sent to the slave device. This saves data transmission link resources and ensures data transmission stability.

[0055] b. The present invention sets the master device's transaction layer to wait for the slave device to return the first approval signal or the second rejection signal, and sets the master device's physical layer to maintain a standard mode to maintain the current basic data transmission function. The master device's data link layer suspends user service data transmission, without adding additional resource pressure and avoiding problems such as increased delays due to data retransmission.

[0056] c. This invention enables all layers of the devices to collaboratively enable high-speed mode during the process of enabling high-speed mode on both the master and slave devices, optimizing parameters related to signal reception. This enhances the ability to restore high-speed signals and prepares the system to receive signals / data transmitted at higher frequencies and rates. This improves data transmission speed while ensuring accuracy and reliability. Furthermore, if problems arise in high-speed mode, such as excessive data retransmissions or excessive transmission delays, the master and slave devices automatically exit high-speed mode and switch to standard mode, preventing data loss and ensuring stable data transmission.

[0057] d. The present invention proposes a high-speed mode communication frame format with lower overhead. By adding a header and CRC1 check, verifying the data, adding a sequence and then a CRC2 check, and adding STAR and END, and by adding necessary identification and verification information in a hierarchical and targeted manner, it can reduce unnecessary redundancy while ensuring data accuracy and reliability verification, lower communication overhead, and improve data transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0059] Figure 1 A flowchart of a high-speed data transmission method based on PCIe is provided as an exemplary embodiment of the present invention;

[0060] Figure 2 A schematic diagram of a principle for requesting switching to a high-speed mode provided by an exemplary embodiment of the present invention;

[0061] Figure 3 A schematic diagram of a process for optimizing a communication frame format at a transmitting end provided by an exemplary embodiment of the present invention;

[0062] Figure 4 A schematic diagram of a process for optimizing a communication frame format at a receiving end provided by an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0063] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0064] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0065] Existing data transmission technologies have significant limitations in monitoring link status during the high-speed mode switching decision process. They typically focus solely on whether the transmission rate has reached a preset threshold, while lacking comprehensive consideration of key factors such as link traffic details, data error frequency, and bit error rate. Due to the omission of this crucial information, existing link status detection methods often have biased arbitration rules when evaluating the rationale for high-speed mode switching, resulting in a lack of scientific rationality in the mode switching decision process and frequent irrational switching decisions.

[0066] In addition, during the initiation phase of the high-speed mode switching request, the existing technology has a relatively rough control over the mechanism for waiting for a reply between the initiator and the receiver, as well as the subsequent operation process. For example, after sending a request to start high-speed mode, the current mechanism only adopts a simple retransmission request processing method when no reply is received for a long time. This not only leads to a serious waste of resources, but also significantly reduces the efficiency of the switching operation. At the same time, while waiting for the reply from the receiver, there is also a lack of effective solutions for how to ensure the stable operation of basic communication functions and maintain the continuity of important data transmission, which greatly affects the smoothness of the entire high-speed mode switching process.

[0067] Furthermore, the traditional PCIe communication frame format contains excessively high amounts of redundant information, such as checksums and identifiers, during data transmission. In high-speed mode, the bandwidth and transmission resources occupied by this redundant information are considerable, directly reducing effective data transmission efficiency and making it difficult to meet the requirements of high-speed, efficient data transmission. Especially when dealing with massive amounts of data transmission, due to PCIe's inherent technical limitations, the SERDES rate cannot be maximized, resulting in a dilemma of underutilized SERDES rate, which significantly restricts the improvement of data transmission performance.

[0068] Based on the above-mentioned deficiencies in the existing technology, this application aims to provide a more flexible and intelligent PCIe-based high-speed data transmission method. By accurately determining whether it is appropriate to switch to high-speed mode based on the real-time status of the link (including transmission rate, traffic conditions, data quality and other factors) and reasonable arbitration rules, the application can give full play to the advantages of high-speed mode while ensuring the stability of data transmission.

[0069] In one embodiment of the present invention, a high-speed data transmission method based on PCIe is provided. Figure 1 As shown, the method includes the following steps:

[0070] Predetermining a master device and a slave device in a PCIe link, wherein the master device and the slave device include a standard mode (i.e., PCIe standard mode) and a high-speed mode (i.e., PCIe high-speed mode), wherein a data transmission speed corresponding to the high-speed mode is greater than a data transmission speed corresponding to the standard mode;

[0071] When the master device is in standard mode, the transaction layer of the master device sends a high-speed mode start request to its data link layer;

[0072] In response to receiving the high-speed mode start request, the data link layer of the master device determines whether the high-speed mode is supported according to its current link state, and if supported, the data link layer of the master device sends the high-speed mode start request to the slave device;

[0073] In response to receiving the high-speed mode start request, the data link layer of the slave device determines whether the high-speed mode is supported according to its current link state, and if supported, the data link layer of the slave device returns a first consent signal to the master device;

[0074] In response to receiving the first consent signal, the master device starts a high-speed mode;

[0075] The master device replies with a second consent signal to the slave device while starting the high-speed mode;

[0076] In response to receiving the second consent signal, the slave device starts the high-speed mode.

[0077] If the data link layer of the master device determines that its current link state does not support high-speed mode, the data link layer of the master device returns a first rejection signal to its transaction layer, and the transaction layer of the master device maintains the standard mode in response to receiving the first rejection signal. If the data link layer of the slave device determines that it does not support high-speed mode based on its current link state, the slave device returns a second rejection signal to the master device, and the master device maintains the standard mode in response to receiving the second rejection signal.

[0078] Wherein, the master device and the slave device in the PCIe link are predetermined. Preferably, the upstream device in the PCIe link is determined to be the master device, and the downstream device in the PCIe link is determined to be the slave device. In the PCIe link, the link status of the upstream device is usually more resource-intensive than the link status of the downstream device. Therefore, by determining that the upstream device in the PCIe link is the master device and always sending a high-speed mode activation request to the slave device, the link status of the master device can be evaluated first. If the link status of the master device does not support the activation of the high-speed mode, it is not necessary to send a high-speed mode activation request to the slave device, thereby saving link resources for data transmission and ensuring the stability of data transmission.

[0079] When the master device is in standard mode, the data link layer of the master device can send the high-speed mode start request to the slave device at a preset frequency, and the transaction layer of the master device waits for the slave device to return a first approval signal or a second rejection signal. During the waiting process, the physical layer of the master device maintains the standard mode, and the data link layer of the master device suspends the sending of user business data.

[0080] Based on the high-speed mode switching mechanism proposed in this application, when the device is initialized, the main device self-checks whether it supports high-speed mode and actively queries whether the sub-device supports high-speed mode. When both parties support high-speed mode and have high-speed transmission requirements, the transaction layer of the main device initiates a request to start high-speed mode. The request to start high-speed mode can be sent through the PCIe interface. Specifically, it can be transmitted using the PCIe3.0 or higher version standard. The request to start high-speed mode contains information that clearly identifies the request to enter high-speed transmission mode and a request packet of necessary parameters such as the device ID that initiated the request and the target device address (in some embodiments, it can also include information such as data volume and transmission requirement speed), and is passed to the data link layer of the main device.

[0081] If one of the master device and the slave device does not support high-speed mode, the master device does not initiate a request to enable high-speed mode. The high-speed transmission requirements of the master device and the slave device can be set in a variety of ways. For example, in response to receiving a user input to start high-speed mode, it is determined that there is a high-speed transmission requirement; for example, when the master device and the slave device are currently in standard mode and have a data transmission requirement, it is also determined that there is a high-speed transmission requirement, and the master device initiates a request to enable high-speed mode at a preset frequency; for example, when the master device and the slave device are currently in standard mode and have a data transmission requirement, and the amount of data to be transmitted is greater than a preset data amount threshold, it is also determined that there is a high-speed transmission requirement.

[0082] The master device's data link layer monitors and arbitrates its own link status. The data link layer comprehensively collects link status information, including the current data transmission rate (which can be achieved through statistical analysis of the physical layer's feedback signal transmission and reception rate information), link traffic (analyzing the amount of data sent and pending), and metrics such as the available space in the receiver's buffer, the number of data transmission errors, and the bit error rate, to comprehensively assess data transmission quality. Mode arbitration is then performed according to preset arbitration rules. For example, when the transmission rate is significantly lower than the high-speed rated rate, link traffic is low, and data quality is good, a switch to high-speed mode is favored. Specifically, if the current data transmission rate is no higher than a preset second rate threshold (which is lower than the data transmission rate in high-speed mode), the available space in the receiver's buffer is no lower than a preset storage space, the number of data transmission errors is no lower than a preset second number threshold, and the bit error rate is no lower than a preset bit error rate threshold, the current link status is determined to support high-speed mode. Otherwise, the current link status is determined to not support high-speed mode.

[0083] When the link status of the data link layer of the master device supports high-speed mode, the data link layer of the master device sends the high-speed mode start request to the physical layer of the master device, and the physical layer of the master device sends the high-speed mode start request to the physical layer of the slave device.

[0084] While the master device is waiting for feedback from the slave device and responding to the request to start high-speed mode, each layer of the master device performs the following operations:

[0085] The transaction layer of the master device waits for the slave device to return a first approval signal or a second rejection signal;

[0086] The physical layer of the master device maintains the PCIe standard mode to ensure basic communication;

[0087] The master device's data link layer suspends user service data (regular data transmission). Special low-priority real-time data transmission is handled according to a special mechanism. This special low-priority real-time data is a special pattern sequence, representing non-user service data such as link control and state maintenance. To maintain link health and proper operation, it must be processed promptly, but latency requirements are typically low. This special mechanism can include DLLPs (Data Link Layer Packets) for transaction layer data packet confirmation, flow control credit updates, and energy management. The physical layer uses ordered sets (such as TS1, TS2, EDB, and SKP) for link training, clock compensation, and entry and exit of electrical idle states.

[0088] The high-speed transmission switching mechanism proposed in this application sets a more refined optimization strategy as mentioned above for the waiting time. The waiting, reply and collaborative operation process of the main device during the high-speed mode switching process improves the switching efficiency, avoids resource waste and communication interruption problems caused by retransmission during the switching process, and ensures the normal maintenance of basic communication functions during the switching period and the continuity of important data transmission.

[0089] like Figure 2 As shown, when the master device receives the first consent signal ( Figure 2 After the ACK shown is an acknowledgment response), its various layers work together to start the high-speed mode.

[0090] The master device's transaction layer updates its transaction processing strategy to match high-speed mode, including adjusting the frequency of data transmission and increasing the upper limit on transaction requests. The master device's data link layer reconfigures data transmission parameters to match high-speed mode, including adjusting the upper limit on traffic and error control parameters. The master device's physical layer optimizes signal reception parameters, including equalization, clock and data recovery, and data sampling parameters. As each layer coordinates to enable high-speed mode, the master device sends an ACK (acknowledgement signal) to the slave device, indicating that it has also enabled high-speed mode and is ready for high-speed data transmission.

[0091] Based on the high-speed mode switching mechanism proposed in this application, the slave device performs the following operations: receiving a high-speed transmission request and arbitrating, and starting the high-speed mode.

[0092] The physical layer of the slave device receives the request signal and restores and decodes it before passing it to its data link layer. The data link layer monitors and arbitrates the link status from its own perspective (checking cache resources, evaluating processing capabilities, analyzing data quality, etc.). The specific link status evaluation method is the same as that of the master device and will not be repeated here.

[0093] like Figure 1 and Figure 2 As shown, if the data link layer of the slave device meets the conditions for entering the high-speed transmission mode, it sends a second consent signal (another ACK signal) to the master device to indicate that it agrees to switch to the high-speed mode. If there is a problem with its own link status (such as insufficient cache, limited processing capacity, poor link quality, etc.), it sends a rejection signal (such as Figure 2 The Nack shown is a negative response), terminates the high-speed mode switching process and maintains standard mode communication.

[0094] After the slave device sends an ACK to the master device and receives a reply ACK from the initiator, the various layers of the slave device adjust and enable high-speed mode. The slave device's transaction layer prepares to receive large-scale data transactions and optimizes the response process. The slave device's data link layer adjusts flow control and error control parameters accordingly. The slave device's physical layer optimizes signal reception parameters and officially enters high-speed transmission mode for high-speed data transmission with the initiator. The various layers of the slave device coordinate to enable high-speed mode in the same manner as the master device and will not be further described.

[0095] In one embodiment of the present invention, when the master device and the slave device enter high-speed mode, both parties optimize the communication frame format in the following manner to reduce redundant information and improve the transmission efficiency of valid data while ensuring data accuracy and integrity, so as to better adapt to the data transmission requirements in high-speed mode.

[0096] When the master device and the slave device enter the high-speed mode, one of the master device and the slave device is a transmitter and the other is a receiver, and the transmitter transmits data to the receiver in the following manner.

[0097] The operation of the sending end is as follows Figure 3 As shown, the transaction layer of the sending end adds a header and CRC1 check to the target transmission data to obtain first data, and sends the first data to the data link layer of the sending end. Adding the header and CRC1 is used to identify basic information such as the data source and type and to perform preliminary data accuracy verification.

[0098] The data link layer at the transmitting end verifies the first data. If the verification passes, it removes the CRC1 checksum from the first data and then adds the sequence flag and CRC2 checksum to obtain the second data. The second data is then transmitted to the physical layer at the transmitting end. The sequence flag is added to identify the order of the data, facilitating data reassembly at the receiving end. The addition of the CRC2 checksum further ensures the integrity and accuracy of the data during link transmission.

[0099] The physical layer of the transmitting end adds STAR (start marker) and END (end marker) markers to the second data to generate third data, and then sends the third data to the receiving end. By adding necessary markers and verification information in a layered and targeted manner, data accuracy and reliability can be verified while reducing unnecessary redundancy and lowering communication overhead.

[0100] The operation of the receiving end is as follows Figure 4 As shown, the receiving end receives the target transmission data in the following manner:

[0101] The physical layer of the receiving end receives the target transmission data in sequence according to the Sequence flag, STAR flag and END flag in the third data, removes the STAR and END flags in the third data after receiving and decoding the third data to obtain fourth data, and transmits the fourth data to the data link layer of the receiving end;

[0102] The data link layer of the receiving end receives the fourth data, performs a CRC2 check on the fourth data, deletes the CRC2 checksum and a Sequence flag in the fourth data if the check passes to obtain fifth data, and transmits the fifth data to the transaction layer of the receiving end;

[0103] The transaction layer of the receiving end receives the fifth data, extracts the payload in the fifth data, obtains the transferred data, and the data reception is completed.

[0104] When the master device and the slave device are in high-speed mode, the master device and the slave device monitor the link status of their own data link layer in real time. When the link status of the data link layer of either the master device or the slave device meets one of the following conditions, the high-speed mode exit mechanism is triggered:

[0105] (1) The link traffic is lower than the preset traffic threshold;

[0106] (2) The number of data errors exceeds the preset first threshold;

[0107] (3) The bit error rate is higher than the preset first bit error rate threshold;

[0108] (4) The amount of data transmission is lower than the preset first rate threshold;

[0109] (5) The data transmission delay is greater than the preset first duration threshold;

[0110] (6) The data retransmission rate is greater than the preset first retransmission rate threshold.

[0111] A device that meets one of the above conditions exits the high-speed mode to switch to the standard mode, and sends a request to exit the high-speed mode to another device.

[0112] After the transaction layer of the receiving end confirms that the data reception is completed, it sends a data reception completion signal to the sending end; the sending end responds to receiving the data reception completion signal and self-checks whether there is other data to be sent. If not, the sending end switches to standard mode and sends a request to end high-speed mode to the receiving end. In response to receiving the request to end high-speed mode, the receiving end switches to standard mode and ends high-speed mode.

[0113] Compared with existing technologies, the beneficial effects of this technical solution include:

[0114] (1) Reduced latency and overhead: When requesting to enter high-speed mode, the present invention does not require simultaneous complex link status monitoring and arbitration processes for both the receiving and transmitting devices. Instead, the master device always sends a high-speed mode activation request to the slave device. The master device's link status can be evaluated first. If the master device's link status does not support high-speed mode activation, there is no need to send a high-speed mode activation request to the slave device. This not only reduces latency but also reduces overhead, thereby improving data transmission efficiency and ensuring data transmission stability.

[0115] (2) Improve transmission accuracy and reliability: When the master device and the slave device are in high-speed mode, their layers work together to enable high-speed mode, optimize parameters related to signal reception, improve the ability to restore high-speed signals, and prepare to receive electrical signals transmitted at higher frequencies and higher rates; this not only improves data transmission speed, but also improves data transmission accuracy and reliability;

[0116] (3) Automatically exit high-speed mode: During high-speed transmission, if problems occur, such as excessive data retransmission or excessive transmission delay, the master and slave devices will automatically exit high-speed mode and switch to standard mode, which can avoid data loss and ensure data transmission stability;

[0117] (4) Optimizing the communication frame format: This technical solution proposes a high-speed mode communication frame format with lower overhead. By adding a header and CRC1 check, verifying the data, adding a sequence and then a CRC2 check, and adding STAR and END, the communication frame format is optimized and the data transmission efficiency is improved.

[0118] (5) Wide scope of application: This technical solution mainly involves the fields of "computer hardware technology", "data transmission technology" and "high-speed interface technology". It can be widely used in personal computers, servers, workstations and other equipment to connect various expansion cards and devices, and has broad application prospects.

[0119] In one embodiment of the present invention, a data transmission device is provided, wherein the data transmission device is configured to perform data transmission based on the PCIe-based high-speed data transmission method as described in any of the above embodiments.

[0120] In one embodiment of the present invention, a computer system is provided, including the data transmission device described in the above embodiment.

[0121] It should be noted that the data transmission equipment and computer system embodiments provided by the present invention have the same inventive concept as the above-mentioned PCIe-based high-speed data transmission method embodiment, and the entire content of the PCIe-based high-speed data transmission method embodiment is incorporated into the data transmission equipment and computer system embodiments by introduction.

[0122] Due to the advanced nature of this technical solution, it can be widely used in the fields of computer systems, data transmission and high-performance computing. First, this technical solution proposes a high-speed mode communication frame format with lower overhead, which can greatly improve the efficiency and speed of data transmission, especially in the fields of big data processing and high-performance computing, which will greatly improve the performance and response speed of the system. Secondly, when requesting to enter high-speed mode, this technical solution determines whether it has the conditions to enter high-speed transmission mode at one time through the master device and the slave device, which can reduce the overhead in the link status monitoring and arbitration process and improve the response speed of the system. In addition, during the data transmission process in high-speed mode, this technical solution can effectively solve problems such as signal distortion and interference by adjusting flow control parameters, error control parameters, etc., which will improve the accuracy and reliability of data transmission. Therefore, this technical solution has great advantages and broad application prospects in high-speed data transmission, and will meet the growing demand for data transmission efficiency and speed in modern computer systems.

[0123] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0124] The above is only a specific implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A high-speed data transmission method based on PCIe, characterized in that: The following steps are involved: A master device and a slave device in a PCIe link are predetermined, wherein the master device and the slave device include a standard mode and a high-speed mode, wherein a data transmission speed corresponding to the high-speed mode is greater than a data transmission speed corresponding to the standard mode, and the master device always sends a request to the slave device to enable the high-speed mode; When the master device is in standard mode, the transaction layer of the master device sends a high-speed mode start request to its data link layer. In response to receiving the high-speed mode start request, the data link layer of the master device determines whether the high-speed mode is supported according to its current link state. If supported, the data link layer of the master device sends the high-speed mode start request to the slave device. The transaction layer of the master device waits for the slave device to return a first approval signal or a rejection signal. During the waiting process, the physical layer of the master device maintains the standard mode, and the data link layer of the master device suspends sending user service data. If the data link layer of the master device determines that its current link state does not support the high-speed mode, the data link layer of the master device returns a first rejection signal to its transaction layer, and the transaction layer of the master device maintains the standard mode in response to receiving the first rejection signal; In response to receiving the high-speed mode start request, the data link layer of the slave device determines whether the high-speed mode is supported according to its current link state, and if supported, the data link layer of the slave device returns a first consent signal to the master device; In response to receiving the first consent signal, the master device starts the high-speed mode and replies a second consent signal to the slave device. In response to receiving the second consent signal, the slave device starts the high-speed mode.

2. The PCIe-based high-speed data transmission method according to claim 1, wherein: The master / slave device starts the high-speed mode in the following way: The transaction layer of the master device / slave device updates the transaction processing strategy to match the high-speed mode, including adjusting the frequency of sending data and increasing the upper limit of the number of transaction requests; and / or, The data link layer of the master device / slave device reconfigures data transmission parameters to match the high-speed mode, including: adjusting the flow upper limit and error control parameters; and / or, The physical layer optimization signal reception parameters of the master device / slave device include: equalization parameters, clock data recovery parameters and data sampling parameters.

3. The PCIe-based high-speed data transmission method according to claim 1, wherein: When the master device and the slave device enter the high-speed mode, one of the master device and the slave device is a transmitter and the other is a receiver, and the transmitter transmits data to the receiver in the following manner: The transaction layer of the sending end adds a header and a CRC1 check to the target transmission data to obtain first data, and sends the first data to the data link layer of the sending end; The data link layer of the transmitting end verifies the first data, and after the verification passes, first deletes the CRC1 check in the first data and then adds the CRC2 check to obtain second data, and transmits the second data to the physical layer of the transmitting end; The physical layer of the transmitting end adds STAR and END tags to the second data to obtain third data, and transmits the third data to the receiving end.

4. The PCIe-based high-speed data transmission method according to claim 3, wherein: The receiving end receives the target transmission data in the following manner: The physical layer of the receiving end receives the third data and decodes the data, including removing STAR and END flags in the third data to obtain fourth data, and transmitting the fourth data to the data link layer of the receiving end; The data link layer of the receiving end receives the fourth data, performs a CRC2 check on the fourth data, deletes the CRC2 check in the fourth data if the check passes to obtain fifth data, and transmits the fifth data to the transaction layer of the receiving end; The transaction layer of the receiving end receives the fifth data, extracts the payload in the fifth data, obtains the transferred data, and the data reception is completed.

5. The PCIe-based high-speed data transmission method according to claim 4, wherein: After the data link layer of the transmitting end deletes the CRC1 check in the first data, the data link layer simultaneously adds the Sequence flag during the process of adding the CRC2 check to obtain the second data; The physical layer of the receiving end receives the target transmission data in sequence according to the Sequence flag, STAR and END flag in the third data.

6. The PCIe-based high-speed data transmission method according to claim 3, wherein: After the transaction layer of the receiving end confirms that the data reception is completed, it sends a data reception completion signal to the sending end; In response to receiving the data reception completion signal, the transmitting end self-checks whether there is other data to be sent. If not, the transmitting end switches to standard mode and sends a request to end high-speed mode to the receiving end. In response to receiving the request to end high-speed mode, the receiving end switches to standard mode.

7. The PCIe-based high-speed data transmission method according to claim 1, wherein: The following steps are also included: When the master device and the slave device are in high-speed mode, the master device and the slave device monitor the link status of their own data link layers in real time; When the link status of the data link layer of any of the two devices, the master device and the slave device, meets one of the following conditions: The link traffic is lower than the preset traffic threshold; The number of data errors exceeds a preset first threshold; The bit error rate is higher than a preset first bit error rate threshold; The data transmission amount is lower than a preset first rate threshold; The device that meets one of the above conditions exits the high-speed mode to switch to the standard mode, and sends a request to exit the high-speed mode to the other device.

8. The PCIe-based high-speed data transmission method according to claim 1, wherein: When the master device / slave device is in high-speed mode, if one of the following conditions is met: The data transmission delay is greater than a preset first duration threshold; The data retransmission rate is greater than a preset first retransmission rate threshold; The master device / slave device then exits the high-speed mode to switch to the standard mode.

9. The PCIe-based high-speed data transmission method according to claim 1, wherein: Predetermine the master and slave devices in the PCIe link, including: An upstream device in a PCIe link is determined to be the master device, and a downstream device in the PCIe link is determined to be the slave device.

10. The PCIe-based high-speed data transmission method according to claim 1, wherein: Use the following methods to evaluate whether the current link status supports high-speed mode: Obtaining the current link status, including the current data transmission rate, available space in the receiving end buffer, number of data transmission errors, and bit error rate; If the current data transmission rate meets the requirements of not higher than the preset second rate threshold, the available space of the receiving end cache is not lower than the preset storage space, the number of data transmission errors is lower than the preset second number threshold and the bit error rate is not lower than the preset bit error rate threshold, then it is determined that the current link status supports high-speed mode; otherwise, it is determined that the current link status does not support high-speed mode.

11. A data transmission device, characterized in that: The data transmission device is configured to perform data transmission based on the PCIe-based high-speed data transmission method according to any one of claims 1 to 10.

12. A computer system, characterized in that: Comprising the data transmission device as claimed in claim 11.

Images