In-memory three-valued logic operation method based on in-memory three-valued logic circuit
By using the RRAM resistance-change characteristics of the in-memory three-value logic circuit, the three-value logic operation is realized, which solves the problem of large area and speed overhead of the traditional in-memory logic circuit, and realizes efficient in-memory three-value logic calculation.
Patent Information
- Application Number
- CN202510387670.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2025-07-18
AI Technical Summary
Traditional in-memory logic circuits based on nonvolatile memory mainly study binary Boolean logic, resulting in large circuit area and speed overhead, making it impossible to efficiently implement memory writing.
The three-value logic circuit based on in-memory is adopted, and the resistance-change characteristics of RRAM are used to realize three-value logic operations by controlling Vgate and VSL voltages, including AND, OR, NOT, and COPY logic operations, reducing auxiliary memory cells and write cycles.
Significantly reduces circuit area and speed overhead, realizes high-integration and high-efficiency in-memory three-value logic calculations, and reduces interconnection difficulty and power consumption.
Smart Images
Figure CN120336250A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and particularly to an in-memory ternary logic operation method based on an in-memory ternary logic circuit. Background Art
[0002] The in-memory logic circuit is a new architecture that solves the von Neumann bottleneck and memory wall problems in current computers. The memories that implement the functions of the in-memory logic circuit can be divided into volatile memories and non-volatile memories. Volatile memories include Static Random-Access Memory (SRAM), Dynamic Random Access Memory (DRAM), etc. Non-volatile memories include Resistive Random Access Memory (RRAM), Phase-Change Random Access Memory (PCRAM), Magnetoresistive Random Access Memory (MRAM), etc. Among them, the in-memory logic circuit based on the non-volatile memory RRAM has the following advantages: 1) Non-volatility after logic completion: It can store the logic result in situ; 2) Zero static power consumption: No power supply voltage needs to be applied in the standby state when the system does not perform logic operations; 3) Online programmability of logic: It can perform specific calculation methods according to different calculation requirements. Therefore, the in-memory logic circuit based on the new non-volatile memory is an important new computer paradigm of the non-von Neumann architecture.
[0003] Traditional in-memory logic based on non-volatile memories mainly studies binary Boolean logic, and current computer systems are mostly implemented based on binary Boolean logic. However, in the traditional Boolean logic operation method, a large number of auxiliary memory units are required and multiple cycles are needed for memory writing, so its circuit area and speed overhead are relatively large. Summary of the Invention
[0004] Aiming at the problems pointed out in the background art, the purpose of the present application is to provide an in-memory ternary logic operation method based on an in-memory ternary logic circuit, which can implement in-memory ternary AND, OR, NOT, and COPY logic operations, and significantly reduce the circuit area and speed overhead.
[0005] To achieve the above purpose, the present application provides the following solutions.
[0006] The present application provides a method for in-memory ternary logic operation based on an in-memory ternary logic circuit. The in-memory ternary logic circuit includes: a 1T1R cell, a word line WL, a bit line BL, and a source line SL; the 1T1R cell includes an NMOS transistor and an RRAM; wherein, the drain of the NMOS transistor is connected to the bottom electrode of the RRAM; the gate of the NMOS transistor is connected to the word line WL; the source of the NMOS transistor is connected to the source line SL; the top electrode of the RRAM is connected to the bit line BL;
[0007] The method for in-memory ternary logic operation includes:
[0008] Define the initial resistance state of the RRAM as the logic input P, the gate voltage V of the NMOS transistor gate as the logic input Q, and the resistance state of the RRAM after resistance change as the logic output Y. Implement the in-memory ternary AND logic operation by applying a corresponding level of V gate voltage to the RRAM;
[0009] Define the initial resistance state of the RRAM as the logic input P, the source line voltage V of the 1T1R cell SL as the logic input Q, and the resistance state of the RRAM after resistance change as the logic output Y. Implement the in-memory ternary OR logic operation by applying a corresponding level of V SL voltage to the RRAM;
[0010] Define the gate voltage V of the NMOS transistor gate as the single-input logic variable P, and the resistance state of the RRAM after resistance change as the logic output Y. Implement the in-memory ternary NOT logic operation by applying a corresponding level of V gate voltage to the RRAM;
[0011] Define the source line voltage V of the 1T1R cell SL as the single-input logic variable P, and the resistance state of the RRAM after resistance change as the logic output Y. Implement the in-memory ternary COPY logic operation by applying a corresponding level of V SL voltage to the RRAM.
[0012] Optionally, when implementing the in-memory ternary AND logic operation, for the logic input P, define the high resistance state HRS of the RRAM as the logic value 2, the middle resistance state MRS as the logic value 1, and the low resistance state LRS as the logic value 0; for the logic input Q, define the high voltage level HVG of the V gate voltage value as the logic value 0, the medium voltage level MVG as the logic value 1, and the low voltage level LVG as the logic value 2.
[0013] Optionally, the implementation of the in-memory ternary AND logic operation specifically includes:
[0014] First, initialize the resistance state of the RRAM according to the logical value of the logical input P to complete the writing of the logical input P; second, apply a V with a corresponding voltage level according to the logical value of the logical input Q gate ; at the same time, apply a corresponding V to both ends of the source line SL and the bit line BL of the 1T1R SL and V BL voltages to implement the SET operation of the RRAM; after the RRAM completes the resistive switching operation, read the logical value corresponding to the resistive state of the RRAM after the resistive switching as the logical output Y.
[0015] Optionally, when implementing the SET operation of the RRAM, set the source line voltage V of the 1T1R cell SL to 0V, and apply a V BL voltage pulse to the word line voltage V of the 1T1R cell SET .
[0016] Optionally, when implementing the in-memory ternary OR logic operation, for the logical input P, define the high resistance state HRS of the RRAM as the logical value 2, the middle resistance state MRS as the logical value 1, and the low resistance state LRS as the logical value 0; for the logical input Q, define the high voltage level HV of the V SL voltage value as the logical value 2, the medium voltage level MV as the logical value 1, and the low voltage level LV as the logical value 0.
[0017] Optionally, the implementation of the in-memory ternary OR logic operation specifically includes:
[0018] First, initialize the resistance state of the RRAM according to the logical value of the logical input P to complete the writing of the logical input P; second, apply a V with a corresponding voltage level according to the logical value of the logical input Q SL ; at the same time, apply a corresponding V to both ends of the bit line BL and the word line WL of the 1T1R BL and V gate voltages to implement the RESET operation of the RRAM; after the RRAM completes the resistive switching operation, read the logical value corresponding to the resistive state of the RRAM after the resistive switching as the logical output Y.
[0019] Optionally, when implementing the in-memory ternary NOT logic operation, for the single-input logical variable P, define the high voltage level HVG of the V gate voltage value as the logical value 2, the medium voltage level MVG as the logical value 1, and the low voltage level LVG as the logical value 0.
[0020] Optionally, the implementation of the in-memory ternary NOT logic operation specifically includes:
[0021] First, initialize the resistance state of the RRAM to the high resistance state (HRS); second, apply a V with a corresponding voltage level according to the logical value of the single-input logical variable P gate ; at the same time, apply a corresponding V SL and V BL voltage across both ends of the source line (SL) and the bit line (BL) of the 1T1R cell to implement the SET operation on the RRAM; after the RRAM completes the resistive switching operation, read the logical value corresponding to the resistance state of the RRAM after resistive switching as the logical output Y.
[0022] Optionally, when implementing the in-memory ternary COPY logic operation, for the single-input logical variable P, define the high voltage level (HV) of the V SL voltage value as the logical value 2, the medium voltage level (MV) as the logical value 1, and the low voltage level (LV) as the logical value 0.
[0023] Optionally, the implementation of the in-memory ternary COPY logic operation specifically includes:
[0024] First, initialize the resistance state of the RRAM to the low resistance state (LRS); second, apply a V with a corresponding voltage level according to the logical value of the single-input logical variable P SL ; at the same time, apply a corresponding V BL and V gate voltage across both ends of the bit line (BL) and the word line (WL) of the 1T1R cell to implement the RESET operation on the RRAM; after the RRAM completes the resistive switching operation, read the logical value corresponding to the resistance state of the RRAM after resistive switching as the logical output Y.
[0025] According to the specific embodiments provided in the present application, the following technical effects are disclosed in the present application.
[0026] An in-memory ternary logic operation method based on an in-memory ternary logic circuit provided in the present application utilizes the resistive switching characteristics of the RRAM resistive memory device to achieve three-state conversion, and further realizes in-memory ternary AND, OR, NOT, and COPY logic operations, avoiding the circuit area and speed overheads brought by a large number of auxiliary memory cells and multiple cycles of memory writing in the traditional Boolean logic operation method, realizing high-integration and high-efficiency in-memory ternary logic calculation, and having broad application prospects. Description of the Drawings
[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0028] Figure 1Schematic diagram of the in-memory ternary logic circuit of the present application;
[0029] Figure 2 Schematic diagram of performing in-memory ternary AND logic operation based on the in-memory ternary logic circuit;
[0030] Figure 3 Truth table of performing in-memory ternary AND logic operation based on the in-memory ternary logic circuit;
[0031] Figure 4 Schematic diagram of performing in-memory ternary OR logic operation based on the in-memory ternary logic circuit;
[0032] Figure 5 Truth table of performing in-memory ternary OR logic operation based on the in-memory ternary logic circuit;
[0033] Figure 6 Schematic diagram of performing in-memory ternary NOT logic operation based on the in-memory ternary logic circuit;
[0034] Figure 7 Truth table of performing in-memory ternary NOT logic operation based on the in-memory ternary logic circuit;
[0035] Figure 8 Schematic diagram of performing in-memory ternary COPY logic operation based on the in-memory ternary logic circuit;
[0036] Figure 9 Truth table of performing in-memory ternary COPY logic operation based on the in-memory ternary logic circuit. Specific implementation manner
[0037] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.
[0038] The objective of the present application is to propose an in-memory ternary logic operation method based on an in-memory ternary logic circuit, which can implement in-memory ternary AND, OR, NOT, and COPY logic operations, and significantly reduce the circuit area and speed overhead.
[0039] To make the above objectives, features, and advantages of the present application more obvious and understandable, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.
[0040] In an exemplary embodiment, the present application provides an in-memory ternary logic operation method based on an in-memory ternary logic circuit. As Figure 1As shown in the figure, the in-memory ternary logic circuit structure includes: 1T1R unit, word line (Word Line) WL, bit line (Bit Line) BL, and source line (Source Line) SL. Among them, the 1T1R unit includes an NMOS transistor (abbreviated as NMOS transistor) and an RRAM. Specifically, the drain of the NMOS transistor is connected to the bottom electrode of the RRAM. The gate of the NMOS transistor is connected to the word line WL. The source of the NMOS transistor is connected to the source line SL. The top electrode of the RRAM is connected to the bit line BL.
[0041] One NMOS transistor in the 1T1R unit is the 1T described in this application, and one RRAM is the 1R described in this application. This 1T (NMOS transistor) 1R (RRAM) unit is the basic unit for implementing this application. The in-memory ternary logic operation method of this application is to implement the function of a ternary logic gate circuit based on the 1T1R unit, including in-memory ternary AND logic operation, in-memory ternary OR logic operation, in-memory ternary NOT logic operation, and in-memory ternary COPY logic operation.
[0042] (1) In-memory ternary AND logic operation
[0043] As Figure 2 shown, when performing the in-memory ternary AND logic operation, the initial resistance state of the RRAM is defined as the logical input (variable) P, the gate voltage V gate of the NMOS transistor is defined as the logical input (variable) Q, and the resistance state of the RRAM after resistive change is defined as the logical output (variable) Y. The in-memory ternary AND logic operation is realized by applying a corresponding level of V gate voltage to the RRAM. In this article, the term resistance state is also abbreviated as resistance state.
[0044] Specifically, the truth table of the in-memory ternary AND logic operation is shown in Figure 3 . When implementing the in-memory ternary AND logic operation, for the logical input P, the high resistance state HRS of the RRAM is defined as the logical value 2, the middle resistance state MRS is defined as the logical value 1, and the low resistance state LRS is defined as the logical value 0. That is, the logical input P = {0, 1, 2} is mapped to {LRS, MRS, HRS}. For the logical input Q, the high voltage level HVG (HighV gate ) of the V gate voltage value is defined as the logical value 0, the medium voltage level MVG (MiddleV gate ) is defined as the logical value 1, and the low voltage level LVG (LowV gate ) is defined as the logical value 2. That is, the logical input Q = {0, 1, 2} is quantified as {HVG, MVG, LVG}.
[0045] Among them, V gate The specific definition of the voltage value involved is as follows. The V that can be completely SET to the low resistance state LRS in the high resistance state HRS gate The current limiting level is defined as the high voltage level HVG (High V gate ). The V that can be partially SET to the middle resistance state MRS in the high resistance state HRS gate The current limiting level is defined as the medium voltage level MVG (Middle V gate ). The V that is not sufficient to be SET and remains in the high resistance state HRS in the high resistance state HRS gate The current limiting level is defined as the low voltage level LVG (Low V gate ). Obviously, HVG > MVG > LVG at the numerical level. In practical applications, the magnitude of the specific implementation voltage value of V gate varies according to different process conditions, different device characteristics, and different test environments, and the specific value needs to be determined according to experiments.
[0046] See Figure 2 , for the in-memory ternary AND logic operation mode, first initialize the resistance state of the RRAM according to the logic value of the logic input P to complete the writing of the logic input P. Secondly, apply the V of the corresponding voltage level according to the logic value of the logic input Q gate ; at the same time, apply the corresponding V SL and V BL voltages to both ends of the source line SL and the bit line BL of the 1T1R. This voltage is the pulse used in the SET process of the RRAM device to implement the SET operation of the RRAM. Specifically, when implementing the SET operation of the RRAM, set the source line voltage V SL of the 1T1R unit to 0V, and apply a V BL voltage pulse to the word line voltage V SET of the 1T1R unit during logical operations. After the RRAM completes the resistive switching operation, read the logic value corresponding to the resistive state of the RRAM after resistive switching as the logic output Y.
[0047] The following takes P = 2 and Q = 1 as an example for illustration. P = 2 represents that the initial resistance state (abbreviated as the initial state) of the RRAM is the high resistance state HRS, that is, the RRAM device is completely RESET to the high resistance state. At this time, the conductive filaments inside the RRAM device are completely disconnected, and the resistance is in the highest state. Q = 1 represents V gateFor the medium voltage level MVG, that is, this voltage level is the one that causes partial breakage of the conductive filament, making the resistance in the intermediate state. At this time, the in-memory ternary AND logic operation is as follows: First, use the RESET operation to change the RRAM to the high resistance state HRS; secondly, apply the voltage V of the medium voltage level MVG to the 1T1R cell, gate and at the same time perform the SET operation on the RRAM device; finally, read the resistance state Y of the RRAM after the resistance change. At this time, the RRAM resistance value is in a resistance state between the high resistance state and the low resistance state, representing that the output result is the intermediate resistance state MRS, corresponding to the logic value "1", and completing the in-memory ternary AND logic calculation operation. In this example, V gate can be taken as 1.1V, V SL as 0V, and V BL as 2.5V. It should be ensured that in this example, the voltage level of V gate is the current-limiting level of V gate at which the high resistance state HRS can be partially SET to the intermediate resistance state MRS, and the voltage level of V BL is the SET voltage V SET in the normal SET process.
[0048] The specific definitions of the voltage values involved in the SET (set) operation and the RESET (reset) operation are as follows.
[0049] In the SET operation, the voltage of the V SL terminal is grounded to 0, and the SET voltage is determined by V BL . Define the voltage value V BL that completely SETs the RRAM device to the low resistance state LRS as the high voltage level (HV), and define the voltage value V BL that is not sufficient to SET the RRAM device and keeps the initial state as the low voltage level (LV), and define the voltage value V BL that can partially SET the RRAM device to the intermediate resistance state MRS as the medium voltage level (MV).
[0050] In the RESET operation, the voltage of the V BL terminal is grounded, and the RESET voltage is determined by V SL . Define the voltage value V SL that completely RESETs the RRAM device to the high resistance state HRS as the high voltage level (HV), and define the voltage value V SL that is not sufficient to RESET the RRAM device as the low voltage level (LV), and define the voltage value V SL that can partially RESET the RRAM device to the intermediate resistance state MRS as the medium voltage level (MV).
[0051] In the examples provided by this application, the given V gate 、V SL and V BL operating conditions are for reference only. The specific implemented voltage values of V gate 、V SL and V BL vary according to different process conditions, different device characteristics, and different test environments, and the specific values need to be determined through experiments.
[0052] The functions of V SL and V BL are mainly reflected in two stages. The first stage is through V SL and V BL to cause the resistance change of the RRAM device and complete the writing of the logical input variable P. The second stage is under the input of the logical input variable Q, V BL and V SL are applied to the RRAM device to implement the SET or RESET operation. Different logical inputs Q and different RRAM resistance states will cause the RRAM resistance state to change to different resistance values, representing different logical outputs. For the RRAM device, the logical values 0, 1, 2 represent different resistance states. For example, {0, 1, 2} can correspond to {the low resistance state after the RRAM is completely SET, the intermediate resistance state of the RRAM, the high resistance state after the RRAM is completely RESET} respectively. For the RRAM device used in this application, the low resistance state is generally on the order of 10 kΩ, the intermediate resistance state is generally on the order of 100 kΩ, and the high resistance state is generally on the order of 1000 kΩ. Of course, for different devices, the resistance values of the high, medium, and low resistance states are different, and these three different resistance states need to be set according to the device characteristics and corresponding to the logical values 0, 1, 2.
[0053] (2) In-memory ternary OR logic operation
[0054] As Figure 4 shown, when performing the in-memory ternary OR logic operation, the initial resistance state of the RRAM is defined as the logical input P, the source line voltage V SL of the 1T1R unit is defined as the logical input Q, and the resistance state of the RRAM after resistance change is defined as the logical output Y. The in-memory ternary OR logic operation is realized by applying the corresponding level of V SL voltage to the RRAM.
[0055] Specifically, the truth table of the in-memory ternary OR logic operation is shown in Figure 5. When implementing the in-memory ternary OR logic operation, for the logic input P, the high-resistance state (HRS) of the RRAM is defined as the logic value 2, the middle-resistance state (MRS) is defined as the logic value 1, and the low-resistance state (LRS) is defined as the logic value 0. That is, the logic input P = {0, 1, 2} is mapped to {LRS, MRS, HRS}. For the logic input Q, the high voltage level (HV) of the voltage value is defined as the logic value 2, the medium voltage level (MV) is defined as the logic value 1, and the low voltage level (LV) is defined as the logic value 0. That is, the logic input Q = {0, 1, 2} is quantified to {LV, MV, HV}. SL The high voltage level (HV) of the voltage value is defined as the logic value 2, the medium voltage level (MV) is defined as the logic value 1, and the low voltage level (LV) is defined as the logic value 0. That is, the logic input Q = {0, 1, 2} is quantified to {LV, MV, HV}.
[0056] See Figure 4 , for the in-memory ternary OR logic operation method, first initialize the resistance state of the RRAM according to the logic value of the logic input P to complete the writing of the logic input P. Secondly, apply the V SL with the corresponding voltage level according to the logic value of the logic input Q; at the same time, apply the corresponding V BL and V gate voltages to both ends of the bit line (BL) and the word line (WL) of the 1T1R to implement the RESET operation of the RRAM. Specifically, when implementing the RESET operation of the RRAM, set the voltage V BL of the bit line BL of the 1T1R unit to 0V, and apply the gate voltage V gate to the NMOS transistor of the 1T1R unit. After the RRAM completes the resistive switching operation, read the logic value corresponding to the resistive state of the RRAM after resistive switching as the logic output Y.
[0057] The following takes P = 2 and Q = 1 as an example for illustration. P = 2 means that the initial state of the RRAM is the high-resistance state (HRS), that is, the RRAM device is completely RESET to the high-resistance state. At this time, the conductive filament inside the RRAM device is completely broken, and the resistance is in the highest state. Q = 1 means that V SL is the medium voltage level (MV), that is, this voltage level is the voltage level that causes the conductive filament to break partially, making the resistance in the intermediate state. At this time, the in-memory ternary OR logic operation is as follows: first, use the RESET operation to resistively switch the RRAM to the high-resistance state (HRS); secondly, apply the V SL with the medium voltage level MV to the 1T1R unit for the SET operation; finally, read the resistive state Y of the RRAM after resistive switching. Its resistive state remains the high-resistance state (HRS), representing that the output result is the high-resistance state (HRS), corresponding to the logic value "2", and completing the in-memory ternary OR logic calculation operation. In this example, V gate can be taken as 2.5V, V SL as 1.1V, and V BL as 0V. As long as it is ensured that V SL is the voltage level that makes the RRAM resistance in the intermediate state, V gateIt is only necessary to use the voltage level during the normal RESET process.
[0058] (3) In-memory ternary NOT logic operation
[0059] Such as Figure 6 shown, when performing the in-memory ternary NOT logic operation, the gate voltage V of the NMOS transistor is defined as a single-input logic variable (which can also be called a logic input) P, and the resistance state after the RRAM resistance change is defined as the logic output Y. By applying the corresponding level of V gate voltage to the RRAM, the in-memory ternary NOT logic operation is realized. gate Specifically, the truth table of the in-memory ternary NOT logic operation is shown in
[0060] When implementing the in-memory ternary NOT logic operation, for the single-input logic variable P, the high voltage level HVG of the V Figure 7 voltage value is defined as the logic value 2, the medium voltage level MVG is defined as the logic value 1, and the low voltage level LVG is defined as the logic value 0. That is, the logic input P = {0, 1, 2} is quantized to {LVG, MVG, HVG}. gate For the in-memory ternary NOT logic operation method, first, the resistance state of the RRAM is initialized to the high resistance state HRS. Second, according to the logic value of the logic input P, the corresponding voltage level of V
[0061] See Figure 6 is applied. At the same time, the corresponding V gate and V SL and V BL voltages are applied to both ends of the source line SL and the bit line BL of the 1T1R cell. The voltage pulse condition is the pulse condition that can make the RRAM device realize the SET process to realize the SET operation of the RRAM. Specifically, when realizing the SET operation of the RRAM, the source line voltage V of the 1T1R cell is set to 0V, and a V SL voltage pulse is applied to the word line voltage V of the 1T1R cell during the logical operation. After the RRAM completes the resistance change operation, the logical value corresponding to the resistance state of the RRAM after the resistance change is read as the logical output Y. BL is applied. After the RRAM completes the resistance change operation, the logical value corresponding to the resistance state of the RRAM after the resistance change is read as the logical output Y. SET voltage pulse. After the RRAM completes the resistance change operation, the logical value corresponding to the resistance state of the RRAM after the resistance change is read as the logical output Y.
[0062] Next, an example with P = 2 is used for illustration. P = 2 represents that V gate is the high voltage level HVG, and the typical value is 2V. At this time, the in-memory ternary NOT logic operation is as follows: First, the RRAM is changed to the high resistance state HRS through the RESET operation; second, the V of the high voltage level HVG is applied to the 1T1R cell gateA voltage pulse is used for the SET operation; finally, the resistance state Y of the RRAM after the resistance change is read. At this time, the RRAM is SET to the low resistance state, representing that the output result is the low resistance state LRS, corresponding to the logic value "0", and the in-memory ternary NOT logic calculation operation is completed. In this example, V gate can be taken as 2V, V SL as 0V, and V BL as 2.5V.
[0063] (4) In-memory ternary COPY logic operation
[0064] As Figure 8 shown, when performing the in-memory ternary COPY logic operation, the source line voltage V SL of the 1T1R cell is defined as the single input logic variable P, and the resistance state of the RRAM after the resistance change is defined as the logic output Y. By applying the corresponding level of V SL voltage to the RRAM, the in-memory ternary COPY logic operation is realized.
[0065] Specifically, the truth table of the in-memory ternary COPY logic operation is shown in Figure 9 . When implementing the in-memory ternary COPY logic operation, for the logic input P, the high voltage level HV of the V SL voltage value is defined as the logic value 2, the medium voltage level MV is defined as the logic value 1, and the low voltage level LV is defined as the logic value 0. That is to say, the logic input P = {0, 1, 2} is quantized to {LV, MV, HV}.
[0066] See Figure 8 . For the in-memory ternary COPY logic operation mode, first, the resistance state of the RRAM is initialized to the low resistance state LRS. Secondly, according to the logic value of the logic input P, the corresponding voltage level of V SL is applied; at the same time, the corresponding V BL and V gate voltages are applied to both ends of the bit line BL and the word line WL of the 1T1R cell. This voltage condition is the pulse voltage condition that can enable the RRAM device to achieve the RESET process, so as to realize the RESET operation of the RRAM. Specifically, when realizing the RESET operation of the RRAM, the bit line BL voltage V BL of the 1T1R cell is set to 0V, and the gate voltage V gate is applied to the NMOS transistor of the 1T1R cell. After the RRAM completes the resistance change operation, the logic value corresponding to the resistance state of the RRAM after the resistance change is read as the logic output Y.
[0067] The following takes P = 2 as an example for illustration. P = 2 represents V SLFor the high voltage level HV, a typical value is 2.5V. At this time, the in-memory ternary COPY logic operation is as follows: First, the RRAM is resistively changed to the low resistance state LRS through the SET operation; second, a voltage pulse with a high voltage level is applied to the 1T1R cell for the RESET operation; finally, the resistive state Y of the RRAM after the resistive change is read. At this time, the RRAM device is completely RESET to the high resistance state, representing that the output result is the high resistance state HRS, corresponding to the logic value "2", and the in-memory ternary COPY logic calculation operation is completed. In this example, V SL can be taken as 2V, V gate = 2V, V SL = 2.5V, V BL = 0V.
[0068] Studies have shown that calculations based on multi-valued logic (MVL) can reduce the interconnection difficulty and minimize the chip space and power consumption by up to 50%. Therefore, multi-valued logic has great potential in replacing traditional computing. In terms of data representation ability, the number of bits required to represent the same value in ternary is about 58.5% less than that in binary, which reduces the data complexity, especially when dealing with a large number of problems such as data encryption. Therefore, in-memory ternary logic has a very broad application space. Compared with the traditional Boolean logic operation method, the in-memory ternary logic operation method based on the in-memory ternary logic circuit of the present application has at least the following beneficial effects:
[0069] 1) No additional auxiliary memory cells are required to implement in-memory ternary AND, OR, NOT, COPY logic operations; the present application utilizes the resistive change characteristics of the SET / RESET process of the RRAM, and by controlling the magnitude of the SET process V gate current limiting and the magnitude of the RESET process V SL to control the RRAM to be resistively changed into three different resistive states, thereby completing the overall logic operation process; the entire in-memory ternary logic circuit can be completed only with a 1T1R cell array, without any additional circuit area overhead;
[0070] 2) The in-memory ternary AND, OR, NOT, COPY logic operations are implemented in one-step write cycles of the memory; the overall operation time includes the time for logically writing to the memory and the time for reading the logical output, providing a V / R-R type in-memory ternary logic operation method with low logical operation steps and low logical operation time.
[0071] That is to say, the in-memory ternary logic operation method based on the in-memory ternary logic circuit of the present application utilizes the SET / RESET resistance switching characteristics of the RRAM resistive memory device to achieve ternary state conversion, and further realizes in-memory ternary logic operation. It avoids the circuit area and speed overhead caused by a large number of auxiliary memory cells and multiple cycles of memory writing in the traditional Boolean logic operation method, realizes high-integration and high-efficiency in-memory ternary logic calculation, and has broad application prospects.
[0072] It should be noted that the terms "including", "comprising" or any other variant thereof used in the present application are intended to cover non-exclusive inclusion, so that a product or system including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such product or system. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the product or system including the said element.
[0073] The above description shows and describes several preferred embodiments of the present application. However, as mentioned above, it should be understood that the present application is not limited to the forms disclosed herein, should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be changed within the scope contemplated by the present application through the above teachings or the technology or knowledge in the relevant field. And the changes and variations made by those skilled in the art without departing from the spirit and scope of the present application should all be within the protection scope of the appended claims of the present application.
[0074] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.
[0075] Specific examples are used in this article to elaborate on the principles and implementation manners of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present application.
Claims
1. A method for in-memory ternary logic operation based on an in-memory ternary logic circuit, characterized in that, The in-memory ternary logic circuit includes: 1T1R cells, word line WL, bit line BL, and source line SL; the 1T1R cell includes an NMOS transistor and an RRAM; wherein, the drain of the NMOS transistor is connected to the bottom electrode of the RRAM; the gate of the NMOS transistor is connected to the word line WL; the source of the NMOS transistor is connected to the source line SL; the top electrode of the RRAM is connected to the bit line BL; The in-memory ternary logic operation method includes: The initial resistance state of RRAM is defined as the logic input P, and the gate voltage V gate Defined as logic input Q, the resistance state of RRAM after resistance change is defined as logic output Y. By applying the corresponding level of V gate Voltage to realize the three-value AND logic operation in memory; Define the initial resistance state of the RRAM as the logical input P, define the source line voltage V of the 1T1R cell SL as the logical input Q, and define the resistance state after the RRAM resistance change as the logical output Y. By applying a corresponding level of V SL voltage to the RRAM, an in-memory ternary OR logic operation is realized; Define the gate voltage V of the NMOS transistor gate as a single-input logic variable P, and define the resistance state after the RRAM resistance change as the logic output Y. By applying the corresponding level of V gate voltage to implement the in-memory ternary NOT logic operation; Define the source line voltage V of the 1T1R cell SL as a single-input logic variable P, and define the resistive state after the RRAM resistance change as the logic output Y. By applying the corresponding level of V to the RRAM SL voltage to implement the in-memory ternary COPY logic operation.
2. The method for in-memory ternary logic operation according to claim 1, wherein When implementing the in-memory ternary AND logic operation, for the logic input P, the high resistance state (HRS) of the RRAM is defined as the logic value 2, the middle resistance state (MRS) is defined as the logic value 1, and the low resistance state (LRS) is defined as the logic value 0; for the logic input Q, the gate high voltage level (HVG) of the voltage value is defined as the logic value 0, the medium voltage level (MVG) is defined as the logic value 1, and the low voltage level (LVG) is defined as the logic value 2.
3. The method for in-memory ternary logic operation according to claim 2, wherein The specific implementation of the in-memory ternary AND logic operation includes: First, initialize the resistance state of the RRAM according to the logic value of the logic input P to complete the writing of the logic input P; secondly, apply a V with a corresponding voltage level according to the logic value of the logic input Q gate ; at the same time, apply corresponding V SL and V BL voltages to both ends of the source line SL and the bit line BL of the 1T1R to realize the SET operation of the RRAM; after the RRAM completes the resistive switching operation, read the logic value corresponding to the resistance state after the resistive switching of the RRAM as the logic output Y.
4. The in-memory ternary logic operation method according to claim 3, wherein When performing the SET operation on the RRAM, the source line voltage V of the 1T1R cell is set to 0V, and a voltage pulse of V is applied to the word line voltage V of the 1T1R cell. SL BL SET 5. The method for in-memory ternary logic operation according to claim 1, wherein When implementing the in-memory ternary OR logic operation, for the logic input P, the high-resistance state (HRS) of the RRAM is defined as the logic value 2, the middle-resistance state (MRS) is defined as the logic value 1, and the low-resistance state (LRS) is defined as the logic value 0; for the logic input Q, the SL high voltage level (HV) of the voltage value is defined as the logic value 2, the medium voltage level (MV) is defined as the logic value 1, and the low voltage level (LV) is defined as the logic value 0.
6. The method for in-memory ternary logic operation according to claim 5, wherein The specific implementation of the in-memory ternary OR logic operation includes: First, initialize the resistance state of the RRAM according to the logic value of the logic input P to complete the writing of the logic input P; second, apply a V with a corresponding voltage level according to the logic value of the logic input Q SL ; at the same time, apply corresponding V BL and V gate voltages to both ends of the bit line BL and the word line WL of the 1T1R to implement the RESET operation of the RRAM; after the RRAM completes the resistive switching operation, read the logic value corresponding to the resistance state of the RRAM after resistive switching as the logic output Y.
7. The method for in-memory ternary logic operation according to claim 1, wherein When implementing the in-memory ternary NOT logic operation, for a single-input logic variable P, V gate The high voltage level HVG of the voltage value is defined as logic value 2, the medium voltage level MVG is defined as logic value 1, and the low voltage level LVG is defined as logic value 0.
8. The method for in-memory ternary logic operation according to claim 7, wherein The specific implementation of the in-memory ternary NOT logic operation includes: First, initialize the resistance state of the RRAM to the high resistance state (HRS); second, apply a V with a corresponding voltage level according to the logic value of the single-input logic variable P gate ; at the same time, apply corresponding V SL and V BL voltages to both ends of the source line (SL) and the bit line (BL) of the 1T1R cell to perform the SET operation on the RRAM; after the RRAM completes the resistive switching operation, read the logic value corresponding to the resistance state after the resistive switching of the RRAM as the logic output Y.
9. The method for in-memory ternary logic operation according to claim 1, wherein When implementing the in-memory ternary COPY logical operation, for a single-input logical variable P, V SL The high voltage level HV of the voltage value is defined as logical value 2, the medium voltage level MV is defined as logical value 1, and the low voltage level LV is defined as logical value 0.
10. The method for in-memory ternary logic operation according to claim 9, characterized in that, The specific implementation of the in-memory ternary COPY logic operation includes: First, initialize the resistance state of the RRAM to the low resistance state (LRS); second, apply a corresponding voltage level of V according to the logical value of the single-input logical variable P SL ; at the same time, apply corresponding V BL and V gate voltages to both ends of the bit line BL and the word line WL of the 1T1R cell to implement the RESET operation of the RRAM; after the RRAM completes the resistive switching operation, read the logical value corresponding to the resistance state of the RRAM after resistive switching as the logical output Y.