Method for extracting parasitic capacitance of three-dimensional semiconductor field effect transistor

Abstract

The invention discloses a method for extracting parasitic capacitance of a three-dimensional semiconductor field effect transistor, which comprises the following steps of: establishing a model of the three-dimensional semiconductor field effect transistor in TCAD software, and classifying the parasitic capacitance based on device characteristics; solving the total capacitance value when the device works under a specific condition, wherein the capacitance value is the total parasitic capacitance of the device; according to the stray capacitance classification composition needing to be solved, the material dielectric constants of the corresponding components are modulated, the total stray capacitance value of the device after the dielectric constants are adjusted is solved, and the stray capacitance of the corresponding components of the device can be solved. And the dielectric constant of the material is re-modulated to extract the parasitic capacitance of other components, so that the extraction work of the parasitic capacitance of each part of the three-dimensional semiconductor field effect transistor is completed. The method can be used for efficiently extracting the parasitic capacitance of the three-dimensional semiconductor field effect transistor, and is suitable for extracting the parasitic capacitance of a device under the condition of process random fluctuation.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor field effect transistor simulation, and particularly relates to a method for extracting parasitic capacitance of a three-dimensional semiconductor field effect transistor based on dielectric constant modulation. Background Art

[0002] Field Effect Transistors (FETs) are widely used in integrated circuits. With the development of Moore's Law, after the feature size of semiconductor devices enters the nanoscale, new types of field effect transistors such as Fin Field Effect Transistors (FinFETs), Gate-All-Around Field Effect Transistors (GAAFETs), and Complementary Field Effect Transistors (CFETs) have been successfully applied to the manufacture of high-performance integrated circuits due to their advantages of strong gate control ability and low power consumption. However, due to the three-dimensional structural characteristics of devices such as FinFETs and GAAFETs, the complexity and importance of their parasitic capacitance are gradually increasing as the device size shrinks. Therefore, whether it is to study the compact model of the parasitic effect of three-dimensional semiconductor field effect transistors or to extract parasitic capacitance in the production and manufacture of integrated circuits to calculate the delay, an accurate and efficient method for extracting parasitic capacitance is required.

[0003] Currently, the common methods for extracting device capacitance mainly rely on computer-aided design software (Technology Computer Aided Design, TCAD), such as Sentaurus and Silvaco, or use specialized interconnect simulation software such as Raphael. However, none of these software is specifically for simulating the parasitic capacitance of semiconductor devices. Using the SDEVICE module in Sentaurus TCAD software can obtain the capacitance value between every two electrodes, but it cannot distinguish between the intrinsic capacitance and the parasitic capacitance, nor can it distinguish the composition of the parasitic capacitance part in the obtained value (such as the fringe capacitance between the gate and the source / drain). Although the Raphael tool can construct metal structures and extract the parasitic capacitance therein, its construction of the device gate and its surrounding structures is inaccurate and the calculation and simulation results are not ideal.

[0004] Based on the TCAD simulation software, the present invention proposes a method for extracting parasitic capacitance based on dielectric constant modulation to solve the problem of unsatisfactory extraction effect of parasitic capacitance of three-dimensional semiconductor field effect transistors. Summary of the Invention

[0005] Technical problem: Aiming at the deficiencies of the above-mentioned existing technologies, a method for extracting the parasitic capacitance of a three-dimensional semiconductor field-effect transistor is proposed. The original method of calculating the device capacitance by TCAD simulation cannot accurately distinguish the parasitic capacitance and the intrinsic capacitance, and cannot simulate and calculate the individual components of the parasitic capacitance. The method proposed in the present invention comprehensively considers the components of the parasitic capacitance and can accurately extract the total parasitic capacitance and the capacitance of each component in the parasitic capacitance using TCAD software.

[0006] Technical solution: To achieve the above object, a method for extracting the parasitic capacitance of a three-dimensional semiconductor field-effect transistor proposed by the present invention includes the following steps:

[0007] Step S1: Establish a model of a three-dimensional semiconductor field-effect transistor in TCAD software, classify the parasitic capacitance based on the characteristics of the three-dimensional semiconductor field-effect transistor, and set specific working conditions to extract the total parasitic capacitance of the three-dimensional semiconductor field-effect transistor;

[0008] Step S2: Measure the area of the overlapping part between the gate and the source / drain epitaxial region through the structural data of the three-dimensional semiconductor field-effect transistor, and extract the parasitic overlap capacitance C ov ;

[0009] Step S3: Modulate the dielectric constants of the gate oxide layer, channel, sidewall, buried oxide layer of the substrate, and source / drain epitaxial region materials of the three-dimensional semiconductor field-effect transistor, and extract the parasitic capacitance C gb ;

[0010] Step S4: Modulate the dielectric constants of the gate oxide layer, channel, sidewall, buried oxide layer of the substrate, and source / drain epitaxial region materials of the three-dimensional semiconductor field-effect transistor, and extract the internal edge parasitic capacitance C if ;

[0011] Step S5: Modulate the dielectric constants of the gate oxide layer, channel, sidewall, buried oxide layer of the substrate, and source / drain epitaxial region materials of the three-dimensional semiconductor field-effect transistor, and extract the external edge parasitic capacitance C of ;

[0012] Step S6: Refine the modulation of the dielectric constants of the sidewall and source / drain epitaxial region materials of the three-dimensional semiconductor field-effect transistor, further refine the external edge parasitic capacitance C of , and extract the parasitic capacitances C of1 and C of2 .

[0013] The three-dimensional semiconductor field-effect transistor has three-dimensional structural characteristics, that is, the source, drain, and gate are not in the same plane, and it has a three-dimensional gate surrounding the channel structure, including FinFET and GAAFET devices.

[0014] The classification and composition of the parasitic capacitance of the three-dimensional semiconductor field-effect transistor are shown in Formulas (1) and (2):

[0015] C total = C in + C para (1)

[0016] C para = C if + C of + C ov + C gb + C add (2)

[0017] ≈ C if + C of + C ov + C gb

[0018] Among them, C total is the total capacitance of the device, C in is the intrinsic capacitance of the device, C para is the total parasitic capacitance of the device, C ov is the parasitic capacitance of the overlapping part between the gate and the source / drain epitaxial region, C if is the internal edge parasitic capacitance generated by the edge electric field inside the gate coupling to the PN junctions on both sides of the channel, C of is the external edge parasitic capacitance generated by the edge electric field outside the gate coupling to the source / drain and the source / drain epitaxial region; among them, C of can be further divided into the parasitic capacitance C of1 of the gate coupling to the source / drain epitaxial region through the sidewall and the parallel plate parasitic capacitance C of2 of the gate coupling to the source / drain region through the sidewall; C gb is the parasitic capacitance related to the gate and the buried oxide layer of the substrate, mainly the parasitic capacitance of the bottom of the gate coupling to the bottom of the source / drain region through the buried oxide layer of the substrate; C add is the additional stray parasitic capacitance, and its value is small and can be ignored.

[0019] In step S1, the specific working conditions for extracting the total parasitic capacitance of the three-dimensional semiconductor field-effect transistor are shown in Formula (3):

[0020] V ds = 0V, 0 ≤ V gs < V T (3)

[0021] Among them, V ds is the voltage difference between the drain and source of the three-dimensional semiconductor field-effect transistor, and V gs is the voltage difference between the gate and source, in volts; V T is the threshold voltage of the three-dimensional semiconductor field-effect transistor; when the device operates under the conditions shown in formula (3), the device is in the depletion region, and the intrinsic capacitance value of the device can be ignored. It is determined that the total capacitance of the device calculated by TCAD is the total parasitic capacitance C para ; as shown in Table 1:

[0022] Table 1 Settings of the relative permittivity of the corresponding region for extracting the total parasitic capacitance of the three-dimensional semiconductor field-effect transistor

[0023]

[0024] In step S2, the parasitic capacitance C of the overlapping part between the gate and the source / drain epitaxial regions in the parasitic capacitance composition ov is calculated by formula (4):

[0025] C ov = ε ox A ov / t ox (4)

[0026] Among them, ε ox is the permittivity of the gate oxide layer dielectric of the three-dimensional semiconductor field-effect transistor, t ox is the thickness of the gate oxide layer of the three-dimensional semiconductor field-effect transistor, and A ov is the total area of the overlapping part region.

[0027] In steps S3, S4, and S5, according to the classification composition of the parasitic capacitance shown in formulas (1) and (2), select the specific region of the three-dimensional semiconductor field-effect transistor for the parasitic capacitance component to be extracted, modulate the permittivity of this part of the material, retain the permittivity value of the specific region, and set the permittivity value of the region outside the specific region to the minimum value MIN close to zero. The value of MIN ranges from 10 -12 to 10 -9 . Under the specific working conditions shown in formula (3), it is determined that the total capacitance of the device calculated by TCAD after the permittivity modulation is this part of the parasitic capacitance; as shown in Table 2:

[0028] Table 2 Settings of the relative permittivity of the corresponding region for extracting the main parasitic capacitance of the three-dimensional semiconductor field-effect transistor

[0029]

[0030] Set C gb calculated by the TCAD software according to Table 2;

[0031] Set C calculated by TCAD software according to Table 2 if +C ov , subtract the obtained C ov Extract C if Parasitic capacitance value;

[0032] Set C calculated by TCAD software according to Table 2 of +C if +C ov , subtract the obtained C if +C ov Extractable C of Parasitic capacitance value.

[0033] In step S6, refine and adjust the relative permittivity of the corresponding part of the three-dimensional semiconductor field-effect transistor, and further refine and distinguish the external edge parasitic capacitance C of It is divided into the parasitic capacitance C of1 coupled from the gate to the source / drain epitaxial region through the sidewall and the parallel plate parasitic capacitance C of2 coupled from the gate to the source / drain region through the sidewall; under the specific working conditions shown in formula (3), the total capacitance of the device calculated by TCAD after dielectric constant modulation is recognized as this part of the parasitic capacitance, and the extraction method is shown in Table 3:

[0034] Table 3 Setting of relative permittivity for refined extraction of external edge parasitic capacitance corresponding area

[0035]

[0036] C of2 Obtained by setting according to Table 3 and calculating by TCAD software, C of1 From the formula C of1 =C of -C of2 Calculated.

[0037] When extracting each main parasitic capacitance, some minor parasitic capacitances with small values are ignored, including the peripheral parasitic capacitance coupled from the gate to the source / drain region through the air medium and the parasitic capacitance generated by the PN junction formed between the substrate and the source / drain region. These small capacitances are uniformly classified into the additional capacitance C add as shown in formula (2), C add The value is so small that it can be ignored.

[0038] When specifically extracting the parasitic capacitance, the sum of the extracted partial parasitic capacitances may be slightly larger than the total parasitic capacitance value C para This may be due to the multiple accumulations of the C add value during extraction, but the error between the two is generally less than 1%.

[0039] Beneficial effects: The present invention proposes a method for extracting parasitic capacitance of a three-dimensional semiconductor field-effect transistor based on dielectric constant modulation. This method uses TCAD simulation software to extract the parasitic capacitance of each part by modulating the relative dielectric constant of the materials of each component of the device under specific voltage conditions, which can overcome the disadvantage that TCAD cannot directly calculate parasitic capacitance and realize the simulation calculation of device parasitic capacitance. This method is applicable to the extraction of parasitic capacitance of various field-effect transistors with three-dimensional structures such as novel FinFETs and GAAFETs, and is also applicable to the extraction of device parasitic capacitance under process random fluctuations. Description of the Drawings

[0040] Figure 1 It is a schematic flow chart of a method for extracting parasitic capacitance of a three-dimensional semiconductor field-effect transistor provided by the present invention.

[0041] Figure 2 It is a schematic diagram of the main parasitic capacitance composition of a method for extracting parasitic capacitance of a three-dimensional semiconductor field-effect transistor provided by the present invention;

[0042] Figure 3 It is a schematic diagram of the composition of the external edge parasitic capacitance of a method for extracting parasitic capacitance of a three-dimensional semiconductor field-effect transistor provided by the present invention;

[0043] Figure 4 It is a schematic diagram of the structure of a 14nm SOI FinFET device used in Embodiment 1 of the present invention;

[0044] Figure 5 It is a schematic diagram of the structure of a 10nm SOI GAAFET device used in Embodiment 1 of the present invention;

[0045] In the figure: source 1, source / drain epitaxial region 2, channel 3, gate oxide layer 4, sidewall 5, gate 6, drain 7, buried oxide layer of the substrate 8. Detailed Embodiments

[0046] The present invention will be further described below with reference to the drawings and embodiments.

[0047] Embodiment 1:

[0048] Refer to Figure 1 , Embodiment 1 of the present invention provides a method for extracting parasitic capacitance of a 14nm SOI FinFET device, and this method includes steps S1 to S6.

[0049] Figure 4Schematic diagram of a 14nm SOI FinFET device structure used in Embodiment 1 of the present invention. In the figure: source 1, source / drain epitaxial region 2, channel 3, gate oxide layer 4, sidewall 5, gate 6, drain 7, buried oxide layer of the substrate 8. The specific parameters of this FinFET device are shown in Table 4:

[0050] Table 4 Parameters of 14nm SOI FinFET in Embodiment 1

[0051]

[0052] S1. Establish a TCAD model of the FinFET device described in this embodiment in TCAD software. The total parasitic capacitance C of the device para can be divided into the following main components:

[0053] C total = C in + C para

[0054] C para = C if + C of + C ov + C gb + C add

[0055] ≈ C if + C of + C ov + C gb

[0056] Among them, C total is the total capacitance of the device, C in is the intrinsic capacitance of the device, C para is the total parasitic capacitance of the device, C ov is the parasitic capacitance of the overlapping part between the gate and the source / drain epitaxial region, C if is the internal edge parasitic capacitance generated by the edge electric field inside the gate coupling to the PN junctions on both sides of the channel, C of is the external edge parasitic capacitance generated by the edge electric field outside the gate coupling to the source / drain and the source / drain epitaxial region; among them, C of can be further divided into the parasitic capacitance C of1 of the gate coupling to the source / drain epitaxial region through the sidewall and the parallel plate parasitic capacitance C of2 of the gate coupling to the source / drain region through the sidewall; C gb is the parasitic capacitance related to the gate and the buried oxide layer of the substrate, mainly the parasitic capacitance of the bottom of the gate coupling to the bottom of the source / drain region through the buried oxide layer of the substrate; C addis the additional stray parasitic capacitance, which is small and can be ignored. The three-dimensional structure distribution in the SOI FinFET in Embodiment 1 of the present invention conforms to Figure 2 the main parasitic capacitance distribution of the three-dimensional semiconductor field-effect transistor shown.

[0057] Apply bias voltages to each electrode of the model so that V ds = 0V, V gs = 0.05V. Under this working condition, extract the total capacitance of the device, as shown in Table 5.

[0058] Table 5 Relative dielectric constant settings for the corresponding regions of the total parasitic capacitance of the SOI FinFET

[0059]

[0060] It is obtained that the total parasitic capacitance C para of the SOI FinFET in this embodiment is 28.60 aF.

[0061] S2. Given that the relative dielectric constant ε r_ox of the gate oxide layer is 22.0 and the thickness t ox of the gate oxide layer is 3.2 nm; use the measurement tool in the TCAD software to measure the length L ov of one side of the overlapping region between the gate and the epitaxial regions of the source / drain, and obtain L ov = 0.50 nm; in the SOI FinFET, the formula for solving the area A ov of the overlapping region between the gate and the epitaxial regions of the source / drain is as follows:

[0062] A ov = 2 × L ov × (2 × H fin + W fin )

[0063] where H fin is the height of the fin structure of the FinFET device, and W fin is the width of the fin structure of the FinFET device. It is known from Table 1 of the device parameters that H fin = 26 nm and W fin = 6.5 nm; substitute the above data into the formula:

[0064] C ov = ε ox A ov / t ox

[0065] It is obtained that the overlapping parasitic capacitance C ov of the SOI FinFET in this embodiment is 3.56 aF.

[0066] S3. Modulate the dielectric constants of some materials inside the device, and extract the parasitic capacitance C related to the gate and the buried oxide layer of the substrate gb . Retain the relative dielectric constant value of the buried oxide layer of the substrate, and modulate the relative dielectric constants of the gate oxide layer, the channel, the sidewall, and the source / drain epitaxial region to MIN = 10 -10 , as shown in Table 6.

[0067] Table 6 Settings of relative dielectric constants of corresponding regions for extracting the parasitic capacitance related to the gate and the buried oxide layer of the SOI FinFET

[0068]

[0069] It is obtained that the parasitic capacitance C related to the gate and the buried oxide layer of the SOI FinFET in this embodiment gb = 2.11 aF.

[0070] S4. Modulate the dielectric constants of some materials inside the device, and extract the internal edge parasitic capacitance C generated by the edge electric field inside the gate coupling to the PN junctions on both sides of the channel if .

[0071] Specifically, the region where the internal edge parasitic capacitance C if is generated is inside the gate, that is, it passes through the gate oxide layer and the channel region, and couples to the PN junctions on both sides of the channel. Retain the relative dielectric constant values of the gate oxide layer, the channel, and the source / drain epitaxial region, and modulate the relative dielectric constants of the sidewall and the buried oxide layer region of the substrate to MIN = 10 -10 , as shown in Table 7.

[0072] Table 7 Settings of relative dielectric constants of corresponding regions for extracting the internal edge parasitic capacitance of the SOI FinFET

[0073]

[0074] Apply bias voltages to each electrode of the model so that V ds = 0V, V gs = 0.05V. Under this working condition, extract the total capacitance of the device, that is, C if + C ov = 7.49 aF; subtract C ov obtained in step S2, and obtain C if = 3.93 aF.

[0075] S5. Modulate the dielectric constants of some materials inside the device, and extract the external edge parasitic capacitance C generated by the edge electric field outside the gate coupling to the source / drain and the source / drain epitaxial region of .

[0076] Specifically, the external edge parasitic capacitance Cof The generated region is outside the gate, that is, it passes through the spacer region and is coupled to the edge of the channel source / drain epitaxial region or the edge of the source / drain region. Keeping the relative dielectric constant values of the gate oxide layer, channel, spacer, and source / drain epitaxial region, the relative dielectric constant value of the buried oxide layer region of the substrate is modulated to MIN = 10 -10 , as shown in Table 8.

[0077] Table 8 Settings of relative dielectric constants for regions corresponding to parasitic capacitances at the outer edges of SOI FinFETs

[0078]

[0079] Biases are applied to each electrode of the model such that V ds = 0V, V gs = 0.05V. Under this working condition, the total capacitance of the device is extracted, that is, C of + C if + C ov = 26.50 aF; subtracting C if and C ov obtained in step S3, C of = 19.01 aF is obtained.

[0080] S6. Refine and modulate the dielectric constants of the corresponding parts of the device materials to further refine the parasitic capacitance C of at the outer edge, and extract the parasitic capacitances C of1 and C of2 .

[0081] C of can be further divided into the parasitic capacitance C of1 of the gate coupled to the source / drain epitaxial region through the spacer and the parallel - plate parasitic capacitance C of2 of the gate coupled to the source / drain region through the spacer. The three - dimensional structure distribution in the SOI FinFET in Embodiment 1 of the present invention conforms to the Figure 3 three - dimensional semiconductor field - effect transistor gate outer - edge parasitic capacitance distribution shown.

[0082] Specifically, the region where the outer - edge parasitic capacitance C of1 is generated passes through the spacer region and is coupled to the edge of the source / drain epitaxial region; the region where the outer - edge parasitic capacitance C of2 is generated passes through the spacer region and is coupled to the edge of the source / drain region.

[0083] Particularly, during the process of extracting the outer - edge parasitic capacitance, the capacitance value of C of2 is calculated successively, and then based on the known value of C of , through the formula C of1 = Cof -C of2 Find out C of1 's capacitance value to complete the extraction of the parasitic capacitance at the epitaxial edges of the two parts. When extracting C of2 , keep the dielectric constant value in the sidewall region, and modulate the relative dielectric constant values of the gate oxide layer, channel, source / drain epitaxial region, and buried oxide layer of the substrate to MIN = 10 -10 , as shown in Table 9.

[0084] Table 9 Refined extraction of dielectric constant settings for regions corresponding to the external edge parasitic capacitance of the SOI FinFET

[0085]

[0086] Apply bias voltages to each electrode of the model such that V ds = 0V, V gs = 0.05V. Under this operating condition, extract the total capacitance of the device, i.e., the external edge parasitic capacitance C of2 = 17.00 aF; Solve for C of1 = C of - C of2 = 2.01 aF.

[0087] In this Example 1, it is obtained that:

[0088] C para = 28.60 aF, C ov = 3.56 aF, C if = 3.93 aF, C gb = 2.11 aF,

[0089] C of = 19.01 aF, C of1 = 2.01 aF, C of2 = 17.00 aF

[0090] After calculation, C ov + C if + C of + C gb = 28.61 aF, and the relative error with the total parasitic capacitance C para is 0.03%. The method for extracting parasitic capacitance in the present invention efficiently extracts the total parasitic capacitance of the three-dimensional semiconductor field effect transistor in this example and the parasitic capacitances of its corresponding components.

[0091] Example 2:

[0092] Refer to Figure 1 , Example 2 of the present invention provides a method for extracting the parasitic capacitance of a GAAFET device, and this method includes steps S1 to S6.

[0093] Figure 5 Schematic diagram of a 10nm SOI GAAFET device structure used in Embodiment 2 of the present invention. In the figure: source 1, source / drain epitaxial region 2, channel 3, gate oxide layer 4, sidewall 5, gate 6, drain 7, buried oxide layer of the substrate 8. The specific parameters of this GAAFET device are as follows:

[0094] Table 10 Parameters of 10nm SOI GAAFET in Embodiment 1

[0095]

[0096] S1. Establish a TCAD model of the GAAFET device described in this embodiment in TCAD software. The total parasitic capacitance C of the device para can be divided into the following main components:

[0097] C total = C in + C para

[0098] C para = C if + C of + C ov + C gb + C add

[0099] ≈ C if + C of + C ov + C gb

[0100] Among them, C total is the total capacitance of the device, C in is the intrinsic capacitance of the device, C para is the total parasitic capacitance of the device, C ov is the parasitic capacitance of the overlapping part between the gate and the source / drain epitaxial region, C if is the internal edge parasitic capacitance generated by the edge electric field inside the gate coupling to the PN junctions on both sides of the channel, C of is the external edge parasitic capacitance generated by the edge electric field outside the gate coupling to the source / drain and the source / drain epitaxial region; among them, C of can be further divided into the parasitic capacitance C of1 of the gate coupling to the source / drain epitaxial region through the sidewall and the parallel plate parasitic capacitance C of2 of the gate coupling to the source / drain region through the sidewall; C gb is the parasitic capacitance related to the gate and the buried oxide layer of the substrate, mainly the parasitic capacitance of the bottom of the gate coupling to the bottom of the source / drain region through the buried oxide layer of the substrate;add is the additional stray parasitic capacitance, which is small and can be ignored. The three-dimensional structure distribution in the SOIGAAFET in Embodiment 2 of the present invention conforms to Figure 2 the main parasitic capacitance distribution of the three-dimensional semiconductor field effect transistor shown.

[0101] Apply bias voltages to each electrode of the model to make V ds = 0V, V gs = 0.05V. Under this working condition, extract the total capacitance of the device, as shown in Table 11:

[0102] Table 11 Relative dielectric constant settings for the corresponding regions of the total parasitic capacitance of the SOI GAAFET

[0103]

[0104] It is obtained that the total parasitic capacitance C para = 33.70 aF.

[0105] S2. Given that the relative dielectric constant ε r_ox of the gate oxide layer is 22.0 and the thickness t ox of the gate oxide layer is 3.2 nm; use the measurement tool in the TCAD software to measure the overlapping region length L ov on one side in the overlapping part of the gate and the source / drain epitaxial regions, and obtain L ov = 0.50 nm; in the GAAFET, the formula for solving the overlapping area of the gate and the source / drain epitaxial regions is as follows:

[0106] A ov1 = 2 × L ov × (2 × H sheet / 2 + W sheet )

[0107] A ov2 = 2 × L ov × (2 × H sheet / 2 + 2 × W sheet )

[0108] Among them, A ov1 is the overlapping area of the nanosheet channel connected to the substrate, and A ov2 is the overlapping area of the nanosheet channel; H sheet is the height of the nanosheet structure in the GAAFET device, and W sheet is the width of the fin structure of the FinFET device. It is known from Table 10 of the device parameters that H sheet = 30 nm and W sheet = 10 nm; substitute the above data into the formula:

[0109] Cov = ε ox (A ov1 + A ov2 ) / t ox

[0110] It is obtained that the overlapping parasitic capacitance C of the device ov = 5.48 aF.

[0111] S3. Modulate the dielectric constants of some materials inside the device, and extract the parasitic capacitance C related to the gate and the buried oxide layer of the substrate gb . Retain the relative dielectric constant value of the buried oxide layer of the substrate, and modulate the relative dielectric constants of the gate oxide layer, the channel, the sidewall, and the source / drain epitaxial region to MIN = 10 -10 , as shown in Table 12.

[0112] Table 12 Settings of the relative dielectric constants of the corresponding regions for extracting the parasitic capacitance related to the gate and the buried oxide layer of the SOI FinFET

[0113]

[0114] It is obtained that the parasitic capacitance C related to the gate and the buried oxide layer of the SOI GAAFET in this embodiment gb = 2.26 aF.

[0115] S4. Modulate the dielectric constants of some materials inside the device, and extract the internal edge parasitic capacitance C generated by the edge electric field inside the gate coupling to the PN junctions on both sides of the channel if .

[0116] Specifically, the region where the internal edge parasitic capacitance C if is generated is inside the gate, that is, it passes through the gate oxide layer and the channel region, and couples to the PN junctions on both sides of the channel. Retain the relative dielectric constant values of the gate oxide layer, the channel, and the source / drain epitaxial region, and modulate the relative dielectric constants of the sidewall and the buried oxide layer region of the substrate to MIN = 10 -10 , as shown in Table 13.

[0117] Table 13 Settings of the relative dielectric constants of the corresponding regions for extracting the internal edge parasitic capacitance C of the SOI GAAFET if Corresponding region relative dielectric constant setting

[0118]

[0119] Apply bias voltages to each electrode of the model so that V ds = 0 V, V gs = 0.05 V. Under this working condition, extract the total capacitance of the device, that is, C if + C ov = 7.27 aF; Subtract C obtained in step S2ov , obtain C if = 1.79 aF.

[0120] S5. Modulate the dielectric constants of some of the materials inside the device, and extract the external edge parasitic capacitance C generated by the edge electric field outside the gate coupling to the source / drain and the source / drain epitaxial regions of .

[0121] Specifically, the region where the external edge parasitic capacitance C of is generated is outside the gate, that is, it passes through the sidewall region and couples to the edge of the channel source / drain epitaxial region or the edge of the source / drain region. Retain the relative dielectric constant values of the gate oxide layer, channel, sidewall, and source / drain epitaxial regions, and modulate the relative dielectric constant value of the buried oxide layer region of the substrate to MIN = 10 -10 , as shown in Table 14.

[0122] Table 14 Settings of relative dielectric constants of corresponding regions for extracting the external edge parasitic capacitance of SOI GAAFET

[0123]

[0124] Apply bias voltages to each electrode of the model so that V ds = 0 V, V gs = 0.05 V. Under this working condition, extract the total capacitance of the device, that is, C of + C if + C ov = 31.50 aF; subtract C if and C ov obtained in step S3, and obtain C of = 24.23 aF.

[0125] S6. Refine the dielectric constants of the corresponding parts of the device, further refine the external edge parasitic capacitance C of , and extract the parasitic capacitances C of1 and C of2 .

[0126] C of can be further divided into the parasitic capacitance C of1 where the gate couples to the source / drain epitaxial region through the sidewall and the parallel plate parasitic capacitance C of2 where the gate couples to the source / drain region through the sidewall. The three-dimensional structure distribution in the SOI GAAFET in Embodiment 2 of the present invention conforms to Figure 3 the three-dimensional semiconductor field effect transistor gate external edge parasitic capacitance distribution shown.

[0127] Specifically, the external edge parasitic capacitance C of1The generated region passes through the sidewall region and is coupled to the edge of the source / drain epitaxial region; the external edge parasitic capacitance C of2 The generated region passes through the sidewall region and is coupled to the edge of the source / drain region.

[0128] Specifically, during the process of extracting the external edge parasitic capacitance, C of2 capacitance value is calculated successively, and then based on the known C of value, through the formula C of1 = C of - C of2 the capacitance value of C of1 is obtained to complete the extraction of the parasitic capacitance of the two parts of the epitaxial edge. When extracting C of2 the dielectric constant value of the sidewall region is retained, and the relative dielectric constant values of the gate oxide layer, channel, source / drain epitaxial region, and substrate buried oxide layer region are modulated to MIN = 10 -10 , as shown in Table 15.

[0129] Table 15 Refined Extraction of Relative Dielectric Constant Settings for Regions Corresponding to External Edge Parasitic Capacitance of SOI GAAFET

[0130]

[0131] A bias voltage is applied to each electrode of the model such that V ds = 0V, V gs = 0.05V. Under this working condition, the total capacitance of the device, i.e., the external edge parasitic capacitance C of2 = 22.80 aF; according to the formula, C of1 = C of - C of2 = 1.43 aF.

[0132] In this Example 2, it is obtained that:

[0133] C para = 33.70 aF, C ov = 5.48 aF, C if = 1.79 aF, C gb = 2.26 aF,

[0134] c of = 24.23 aF, C of1 = 1.43 aF, C of2 = 22.80 aF

[0135] After calculation, C ov + C if + C of + C gb = 33.76 aF, which is the same as the total parasitic capacitance Cpara The relative error is 0.18%. The method for extracting parasitic capacitance in the present invention efficiently extracts the total parasitic capacitance of the three-dimensional semiconductor field effect transistor in this embodiment and the parasitic capacitances of its corresponding components.

Claims

1. A method for extracting parasitic capacitance of a three-dimensional semiconductor field effect transistor, characterized in that, Including the following steps: Step S1: Establish a model of a three-dimensional semiconductor field-effect transistor in TCAD software, classify the parasitic capacitances based on the characteristics of the three-dimensional semiconductor field-effect transistor, and set specific working conditions to extract the total parasitic capacitance of the three-dimensional semiconductor field-effect transistor; Step S2: Measure the area of the overlapping part between the gate and the source / drain epitaxial regions through the three-dimensional semiconductor field effect transistor structure data, and extract the parasitic overlap capacitance C ov ; Step S3: Modulate the dielectric constants of the gate oxide layer, channel, sidewall, buried oxide layer of the substrate, and source / drain epitaxial region materials of the three-dimensional semiconductor field effect transistor, and extract the parasitic capacitance C related to the gate and the buried oxide layer of the substrate gb ; Step S4: Modulate the dielectric constants of the gate oxide layer, channel, sidewall, buried oxide layer of the substrate, and source / drain epitaxial region materials of the three-dimensional semiconductor field-effect transistor, and extract the internal edge parasitic capacitance C generated by the edge electric field inside the gate coupling to the PN junctions on both sides of the channel if ; Step S5: Modulate the dielectric constants of the gate oxide layer, channel, sidewall, buried oxide layer of the substrate, and source / drain epitaxial region materials of the three-dimensional semiconductor field-effect transistor, and extract the external edge parasitic capacitance C generated by the edge electric field outside the gate being coupled to the source / drain and the source / drain epitaxial region of ; Step S6: Refine the dielectric constant of the sidewall and source / drain epitaxial region materials of the modulated three-dimensional semiconductor field-effect transistor, and further refine the external edge parasitic capacitance C of , extract the parasitic capacitance C of1 and C of2 .

2. The method for extracting parasitic capacitance of a three-dimensional semiconductor field effect transistor according to claim 1, wherein The three-dimensional semiconductor field-effect transistor has three-dimensional structural characteristics, that is, the source, drain, and gate are not in the same plane, and it has a three-dimensional gate surrounding the channel structure, including FinFET and GAAFET devices.

3. A method for extracting parasitic capacitance of a three-dimensional semiconductor field effect transistor according to claim 1, characterized in that, The classification composition of the parasitic capacitances of the three-dimensional semiconductor field-effect transistor is shown in formulas (1) and (2): C total = C in + C para (1) C para = C if + C of + C ov + C gb + C add (2) ≈C if +C of +C ov +C gb Among them, C total is the total capacitance of the device, C in is the intrinsic capacitance of the device, C para is the total parasitic capacitance of the device, C ov is the parasitic capacitance of the overlapping part between the gate and the source / drain epitaxial region, C if is the internal edge parasitic capacitance generated by the edge electric field inside the gate coupling to the PN junctions on both sides of the channel, C of is the external edge parasitic capacitance generated by the edge electric field outside the gate coupling to the source / drain and the source / drain epitaxial region; among them, C of can be further divided into the parasitic capacitance C of1 of the gate coupling to the source / drain epitaxial region through the sidewall and the parallel plate parasitic capacitance C of2 of the gate coupling to the source / drain region through the sidewall; C gb is the parasitic capacitance related to the gate and the buried oxide layer of the substrate, mainly the parasitic capacitance of the bottom of the gate coupling to the bottom of the source / drain region through the buried oxide layer of the substrate; C add is the additional stray parasitic capacitance, the value of which is small and can be ignored.

4. A method for extracting parasitic capacitance of a three-dimensional semiconductor field effect transistor according to claim 1, characterized in that, In step S1, the specific working conditions for extracting the total parasitic capacitance of the three-dimensional semiconductor field-effect transistor are shown in formula (3): V ds = 0V, 0 ≤ V gs < V T (3) Among them, V ds is the voltage difference between the drain and source of the three-dimensional semiconductor field-effect transistor, and V gs is the voltage difference between the gate and source, in volts; V T is the threshold voltage of the three-dimensional semiconductor field-effect transistor; when the device operates under the conditions shown in Equation (3), the device is in the depletion region, and the intrinsic capacitance value of the device can be ignored. It is considered that the total capacitance of the device calculated by TCAD is the total parasitic capacitance C para ; as shown in Table 1: Table 1 Relative permittivity settings for the regions corresponding to the extraction of the total parasitic capacitance of the three-dimensional semiconductor field-effect transistor 5. A method for extracting parasitic capacitance of a three-dimensional semiconductor field effect transistor according to claim 1, characterized in that, In step S2, the parasitic capacitance C of the overlapping portion between the gate and the source / drain epitaxial regions in the parasitic capacitance composition ov is calculated by formula (4): C ov = ε ox A ov / t ox (4) Among them, ε ox is the dielectric constant of the gate oxide layer dielectric of the three-dimensional semiconductor field effect transistor, and t ox is the thickness of the gate oxide layer of the three-dimensional semiconductor field effect transistor, and A ov is the total area of the overlapping part region.

6. A method for extracting parasitic capacitance of a three-dimensional semiconductor field effect transistor according to claim 1, characterized in that In steps S3, S4, and S5, according to the classification composition of the parasitic capacitance shown in formulas (1) and (2), select a specific region of the three-dimensional semiconductor field-effect transistor of the parasitic capacitance component to be extracted, modulate the dielectric constant of this part of the material, retain the dielectric constant value of the specific region, and set the dielectric constant value of the region outside the specific region to the minimum value MIN close to zero, where the value of MIN is between 10 -12 ~10 -9 . Under the specific working conditions shown in formula (3), the total capacitance of the device calculated by TCAD after dielectric constant modulation is recognized as the parasitic capacitance of this part; as shown in Table 2: Table 2 Relative permittivity settings for the regions corresponding to the extraction of the main parasitic capacitances of the three-dimensional semiconductor field-effect transistor Set C obtained by TCAD software calculation according to Table 2 gb ; Set C obtained by TCAD software calculation according to Table 2 if +C ov , subtract the obtained C ov Extract C if Parasitic capacitance value; Set C obtained by TCAD software calculation according to Table 2 of +C if +C ov , subtract the obtained C if +C ov The parasitic capacitance value can be extracted of ​ 7. A method for extracting parasitic capacitance of a three-dimensional semiconductor field effect transistor according to claim 1, characterized in that, In step S6, the dielectric constant of the corresponding part of the three-dimensional semiconductor field effect transistor is refined and adjusted, and the external edge parasitic capacitance C of is further refined and distinguished into the parasitic capacitance C of1 where the gate is coupled to the source / drain epitaxial region through the sidewall, and the parallel plate parasitic capacitance C of2 ; Under the specific working conditions shown in formula (3), it is determined that the total capacitance of the device calculated by TCAD after dielectric constant modulation is this part of the parasitic capacitance, and the extraction method is shown in Table 3: Table 3 Refined relative permittivity settings for the regions corresponding to the extraction of the external edge parasitic capacitance C of2 Set according to Table 3, obtained by TCAD software calculation, C of1 From the formula C of1 = C of - C of2 Calculated as follows.

8. A method for extracting parasitic capacitance of a three-dimensional semiconductor field effect transistor according to claim 1, characterized in that, When extracting each main parasitic capacitance, some minor parasitic capacitances with small values are ignored, including the peripheral parasitic capacitance of the gate coupled to the source / drain region through the air medium, and the parasitic capacitance generated by the PN junction formed between the substrate and the source / drain region. These small capacitances are uniformly grouped into the additional capacitance C add in, as shown in formula (2), C add The value is so small that it can be ignored.

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