Display driving chip and display device

Abstract

According to the display driving chip and the display device provided by the embodiment of the invention, the first IO interface is short-circuited with the output end of the first voltage signal generation module, so that even if the first voltage signal is not generated on the mainboard of the display equipment where the display driving chip is located, the display driving chip can comprise the IO interface for outputting the first voltage signal; and user requirements are met.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display driving chip and a display device. Background Art

[0002] For LTPO (Low Temperature Polycrystalline Oxide) OLED (Organic Light Emitting Display) products, the AP (Application Processor) is now paying increasing attention to the power consumption of the display driving chip. Currently, the voltage of the IO (Input / Output Interface) is basically 1.8V. To consider the power consumption of the entire machine, the requirement for a 1.2V IO voltage has gradually been mentioned. However, for power consumption considerations, the motherboard of the subsequent display device will not provide a 1.2V voltage source. This requires designing a solution that is compatible with a 1.2V IO without the motherboard of the mobile phone providing a 1.2V voltage source. Summary of the Invention

[0003] The purpose of the embodiments of this application is to provide a display driving chip and a display device. The specific technical solutions are as follows:

[0004] The embodiments of this application provide a display driving chip, including:

[0005] A first voltage signal generation module and a first IO interface;

[0006] The first voltage signal generation module is used to generate a first voltage signal, and the first IO interface is short-circuited with the output end of the first voltage signal generation module. Among them, the first voltage signal is a voltage signal that is not generated by the motherboard of the display device where the display driving chip is located.

[0007] In a possible implementation manner, the first voltage signal generation module is used to generate a 1.2V voltage signal.

[0008] In a possible implementation manner, it further includes an electrostatic protection module;

[0009] The electrostatic protection module is disposed between the first IO interface and the receiving circuit, and the receiving circuit is used to receive the first voltage signal output by the first IO interface.

[0010] In a possible implementation manner, the display driving chip further includes a first resistor;

[0011] The first resistor is connected in series between the electrostatic protection module and the receiving circuit.

[0012] In a possible implementation, the electrostatic protection module includes a first digital ground, and the receiving circuit includes a second digital ground;

[0013] The first digital ground is shorted to the second digital ground.

[0014] In a possible implementation, the electrostatic protection module includes a first transistor, a second transistor, a second resistor, a third transistor, and a fourth transistor;

[0015] The first end of the first transistor, the first end of the second transistor, and the first end of the second resistor are all connected to the first IO interface;

[0016] The second end of the first transistor is connected to the first digital ground; the second end of the second transistor is connected to a first high-level signal;

[0017] The second end of the second resistor is connected to the first end of the third transistor and the first end of the fourth transistor;

[0018] The second end of the third transistor and the second end of the fourth transistor are both connected to the receiving signal terminal of the receiving circuit;

[0019] The first power receiving terminal of the receiving circuit is connected to a second high-level signal;

[0020] The second power receiving terminal of the receiving circuit is connected to the second digital ground.

[0021] In a possible implementation, the electrostatic protection module further includes a third resistor, and the receiving circuit includes a fourth resistor;

[0022] The first end of the third resistor is connected to the second end of the second transistor, and the second end of the third resistor is connected to the first digital ground;

[0023] The first end of the fourth resistor is connected to the second power receiving terminal of the receiving circuit, and the second end of the fourth resistor is connected to the second digital ground.

[0024] In a possible implementation, the electrostatic protection module further includes a first diode and a second diode;

[0025] The anode of the first diode and the cathode of the second diode are connected to the first end of the third resistor;

[0026] The cathode of the first diode and the anode of the second diode are connected to the first end of the fourth resistor;

[0027] The second end of the first transistor, the second end of the second transistor are connected to the first end of the third transistor and the first end of the fourth transistor.

[0028] In a possible implementation manner, the electrostatic protection module further includes a third diode and a fourth diode;

[0029] The anode of the third diode and the cathode of the third diode are connected to the second end of the third resistor;

[0030] The cathode of the fourth diode and the anode of the fourth diode are connected to the second end of the fourth resistor.

[0031] The embodiment of the present application further provides a display device, including the display driving chip described in any one of the above.

[0032] Beneficial effects of the embodiment of the present application:

[0033] For the display driving chip and the display device provided by the embodiment of the present application, by short - circuiting the first IO interface and the output end of the first voltage signal generation module, even when the main board of the display device where the display driving chip is located does not generate the first voltage signal, it can be realized that the display driving chip includes an IO port for outputting the first voltage signal, and the first voltage signal is provided for the user through the first IO interface, meeting the user's needs.

[0034] Of course, when implementing any product or method of the present application, it is not necessarily required to achieve all the above - mentioned advantages simultaneously. Brief Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following - described drawings are only some embodiments of the present application, and those of ordinary skill in the art can also obtain other embodiments according to these drawings.

[0036] Figure 1-1 It is a first structural schematic diagram of a display driving chip provided by an embodiment of the present application;

[0037] Figure 1-2 It is a structural schematic diagram of a connection between a display driving chip and a PMIC provided by an embodiment of the present application;

[0038] Figure 2 It is a second structural schematic diagram of a display driving chip provided by an embodiment of the present application;

[0039] Figure 3-1 It is a schematic diagram of a scenario of ESD of a typical charging device model CDM;

[0040] Figure 3-2 For Figure 3-1 equivalent circuit diagram;

[0041] Figure 4 This is a schematic diagram of the third structure of a display driver chip provided by an embodiment of the present application;

[0042] Figure 5 This is a schematic diagram of the fourth structure of a display driver chip provided by an embodiment of the present application;

[0043] Figure 6 This is a schematic diagram of the fifth structure of a display driver chip provided by an embodiment of the present application;

[0044] Figure 7 This is a schematic diagram of the sixth structure of a display driver chip provided by an embodiment of the present application;

[0045] Figure 8 This is a schematic diagram of the seventh structure of a display driver chip provided by an embodiment of the present application;

[0046] Figure 9 This is a design diagram of a display driver chip provided by an embodiment of the present application. Detailed implementation manners

[0047] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art based on the present application belong to the scope of protection of the present application.

[0048] Currently, the voltage of the IO (input / output interface) is basically 1.8V. To consider the power consumption of the entire machine, the host of the display device including the display driver chip generally only provides a voltage source of 1.8V. However, with the development of technology, the demand for an IO voltage of 1.2V has gradually been mentioned. For example, both the Flash interface and the I 2 C interface (Inter-Integrated Circuit interface) require a voltage source of 1.2V. However, for the sake of power consumption, the motherboard of the subsequent display device will not provide a voltage source of 1.2V. Therefore, as Figure 1-1 shown, an embodiment of the present application provides a display driver chip. The display driver chip 00 includes:

[0049] A first voltage signal generation module 110 and a first IO interface 210;

[0050] The first voltage signal generation module 110 is used to generate a first voltage signal, and the first IO interface 210 is short-circuited with the output end of the first voltage signal generation module 110.

[0051] A DDIC (Display Driver Integrated Circuit) is the core chip used to control display devices such as LCD (Liquid Crystal Display), OLED, Micro-LED (Micro Light Emitting Diode Display), etc., for the pixel to emit light or change color. It is responsible for converting image data into the electrical signals required by the panel and driving the pixels to display regularly. It is the bridge between the display panel of the display device and the main processor of the display device, such as a mobile phone SoC (System on Chip) or a graphics card, and directly affects the display effect (such as resolution, refresh rate, color accuracy, power consumption, etc.).

[0052] Inside the DDIC, there is a first voltage signal generation module 110. The first voltage signal generation module 110 can generate a first voltage signal and output the first voltage signal through the output terminal of the first voltage signal generation module 110. The first voltage signal can be a voltage signal that is not generated by the main board of the display device where the display driver chip is located.

[0053] Exemplarily, when the main board of the display device where the display driver chip is located mainly provides a voltage signal of 1.8V, the first voltage signal can be a voltage signal of 1.2V. Or, when the main board of the display device where the display driver chip is located mainly provides a voltage signal of 2.3V, the first voltage signal can be a voltage signal of 1.8V. The specific magnitude of the first voltage signal generated by the first voltage signal generation module 110 can be determined based on the actual situation and is not limited here.

[0054] The first IO interface 210 can be a physical interface for the DDIC to interact with other devices (such as a display, a button, etc.). The first IO interface 210 is the "bridge" for the DDIC to communicate with other devices, and the other devices can be any device that requires the first voltage signal.

[0055] Short-circuit the first IO interface 210 with the output terminal of the first voltage signal generation module 110. Since the output terminal of the first voltage signal generation module 110 outputs the first voltage information, after short-circuiting the first IO interface 210 with the output terminal of the first voltage signal generation module 110, the first IO interface 210 is connected to the first voltage signal, and then the first voltage signal can be output through the first IO interface 210.

[0056] For example, when the first voltage signal is 1.2V, the first IO interface 210 can be connected to a flash memory to provide a voltage signal for the flash memory, so as to realize operations such as reading, writing, and erasing data in the flash memory.

[0057] Alternatively, when the first voltage signal is 1.2V, the first IO interface 210 can be connected to the I 2 C bus to provide a working voltage for the I 2 C bus and realize the communication of the I 2 C. For example, the display device further includes a PMIC (Power Management Integrated Circuit), and the PMIC communicates with the DDIC through the I 2 C bus. Then, the first IO interface 210 of the DDIC can provide a working voltage for the I 2 C bus to realize the communication between the PMIC and the DDIC. As Figure 1-2 shown.

[0058] By short - circuiting the first IO interface 210 with the output terminal of the first voltage signal generation module 110, even when the main board of the display device where the display driver chip is located does not generate the first voltage signal, it is possible to implement that the display driver chip includes an IO port for outputting the first voltage signal, and provide the first voltage signal for the user through the first IO interface to meet the user's needs.

[0059] In a possible implementation manner, the first voltage signal generation module 110 is used to generate a voltage signal of 1.2V.

[0060] For the display driver chip, the voltage required by the load connected to the display driver chip is between 1.2V and 1.95V, and the typical value is 1.8V. However, there is also a circuit design in the display driver chip that provides a voltage of 1.2V. Thus, when an input - output interface requiring a voltage of 1.2V is needed, the first voltage signal generation module 110 that generates 1.2V inside the display driver chip can be used to meet the requirements of the input - output interface with a voltage of 1.2V, without the main board of the display device where the display driver chip is located generating a 1.2V power supply voltage, and the requirement of 1.2V IO compatibility can also be realized.

[0061] As Figure 2 shown, in a possible implementation manner, an electrostatic protection module 310 is further included;

[0062] The electrostatic protection module 310 is arranged between the first IO interface 210 and the receiving circuit 410, and the receiving circuit 410 is used to receive the first voltage signal output by the first IO interface 210.

[0063] ESD (Electrostatic Discharge) refers to the phenomenon in which the static electric charges accumulated on the surface of an object are suddenly released through contact, electric field coupling, induction, or other means. In the electronic field, ESD is one of the important hidden dangers that can cause component damage and circuit failures. Therefore, the display driver chip further includes an electrostatic protection module 310. The electrostatic protection module 310 is arranged between the first IO interface 210 and the receiving circuit 410. The static electric charges are released through the electrostatic protection module 310, and the discharge current is released through the electrostatic protection module, protecting the devices of the receiving circuit 410 from being damaged.

[0064] In a possible implementation manner, the display driver chip further includes a first resistor;

[0065] The first resistor is connected in series between the electrostatic protection module and the receiving circuit.

[0066] Both the electrostatic protection module and the receiving circuit include a ground signal. The electrostatic protection module and the receiving circuit adopt different ground signals. The ground of the electrostatic protection module is the first digital ground, and the ground of the receiving circuit is the second digital ground. That is to say, the grounds of the front and rear stages are inconsistent. A first resistor can be set between the electrostatic protection module and the receiving circuit. The first resistor can play a role in current limiting, preventing the current in the circuit from being too large, and further protecting the devices of the receiving circuit 410 from being damaged.

[0067] As Figure 3-1 shown, Figure 3-1 is a schematic diagram of a scenario of ESD of a typical Charged Device Model (CDM).

[0068] A Charged Device undergoes Electrostatic Discharge (ESD). Figure 3-1 In the figure, a plastic tube is dropping towards the charged device, and charges are accumulated on the charged device (as Figure 3-1 shown). When the charged device approaches a grounded metal device (such as a table, Metallic equipment, Ex.Table), the charges will be released in the form of discharge. That is, after the electronic device itself is charged, discharging to the ground through the pins may cause damage to the electronic device.

[0069] As Figure 3-2 shown, Figure 3-2 is Figure 3-1 the equivalent circuit diagram:

[0070] V is the power supply, which provides electrical energy for the entire circuit.

[0071] R is a resistor: connected in series with the power supply, it can limit the magnitude of the current and prevent excessive current in the circuit from damaging other components.

[0072] The switch includes two contacts A and B. When the switch is connected to contact A, the current flows out from the positive pole of the power supply, passes through the resistor R and the device under test (DUT) in sequence, and then returns to the negative pole of the power supply. At this time, the device is connected to the circuit for testing.

[0073] When the switch is connected to contact B, it will cause a short circuit. The current does not pass through the device and directly returns from the positive pole of the power supply through the resistor R and contact B to the negative pole of the power supply. This is a dangerous state and may damage the power supply.

[0074] The device under test (DUT) is the object to be tested in this circuit. By connecting it to the circuit, its electrical performance (such as parameters like voltage, current, resistance, etc.) can be tested and analyzed.

[0075] Both the electrostatic protection module and the receiving circuit include ground signals. The electrostatic protection module and the receiving circuit use different ground signals. During the CDM test, a voltage difference will gradually occur between the two ground signals, which will cause the voltage at the receiving end of the receiving circuit to increase. Once the voltage difference is too large, it may cause the components in the receiving circuit to burn out.

[0076] Therefore, in a possible implementation, the electrostatic protection module includes a first digital ground, and the receiving circuit includes a second digital ground;

[0077] The first digital ground is short-circuited with the second digital ground.

[0078] Both the electrostatic protection module and the receiving circuit include ground signals. The electrostatic protection module and the receiving circuit use different ground signals. The ground of the electrostatic protection module is the first digital ground, and the ground of the receiving circuit is the second digital ground. By short-circuiting the first digital ground and the second digital ground, when a voltage difference occurs between the first digital ground and the second digital ground, a conduction path can be provided to consume the static electricity through the path between the first digital ground and the second digital ground, avoiding the components of the receiving module from burning out.

[0079] In a possible implementation, the electrostatic protection module includes a first digital ground, and the receiving circuit includes a second digital ground;

[0080] A bidirectional transient diode is provided between the first digital ground and the second digital ground.

[0081] Both the electrostatic protection module and the receiving circuit include a ground signal. The electrostatic protection module and the receiving circuit use different ground signals. The ground of the electrostatic protection module is the first digital ground, and the ground of the receiving circuit is the second digital ground. A board-to-board diode is connected in series between the first digital ground and the second digital ground. When a voltage difference occurs between the first digital ground and the second digital ground, the bidirectional transient can conduct, providing a conduction path between the first digital ground and the second digital ground, and dissipating the static electricity through the path between the first digital ground and the second digital ground, avoiding the burnout of the components in the receiving module.

[0082] As Figure 4 shown, in a possible implementation, the electrostatic protection module 310 includes a first transistor T1, a second transistor T2, a second resistor R2, a third transistor T3, and a fourth transistor T4;

[0083] The first end of the first transistor T1, the first end of the second transistor T2, and the first end of the second resistor are all connected to the first IO interface 210;

[0084] The second end of the first transistor T1 is connected to the first digital ground; the second end of the second transistor T2 is connected to the first high-level signal;

[0085] The second end of the second resistor R2 is connected to the first end of the third transistor T3 and the first end of the fourth transistor T4;

[0086] The second ends of the third transistor T3 and the fourth transistor T4 are both connected to the receiving signal end of the receiving circuit 410; the control end of the third transistor T3 is connected to the first digital ground; the control end of the fourth transistor T4 is connected to the first high-level signal;

[0087] The first power receiving end of the receiving circuit is connected to the second high-level signal;

[0088] The second power receiving end of the receiving circuit is connected to the second digital ground.

[0089] The polarities of the first transistor T1 and the second transistor T2 are opposite. That is to say, when the first transistor T1 is a P-type transistor, the second transistor T2 is an N-type transistor. When the first transistor T1 is an N-type transistor, the second transistor T2 is a P-type transistor.

[0090] The polarities of the third transistor T3 and the fourth transistor T4 are opposite. That is to say, when the third transistor T3 is a P-type transistor, the fourth transistor T4 is an N-type transistor. When the third transistor T3 is an N-type transistor, the fourth transistor T4 is a P-type transistor.

[0091] The control terminals of the first transistor T1 and the second transistor T2 are both connected to an enable signal. The enable signal can be provided by the DDIC. In one example, when the DDIC is in the working state, the DDIC provides the enable signal, and the control terminals of the first transistor T1 and the second transistor T2 are both connected to this enable signal.

[0092] Since the electrostatic protection module 310 includes the first transistor T1, the second transistor T2, the second resistor R2, the third transistor T3, and the fourth transistor T4, when there is static electricity, the energy can be discharged to the ground through the T2 transistor to protect the devices of the receiving circuit 410 from being damaged.

[0093] As Figure 5 shown, in a possible implementation, the electrostatic protection module 310 further includes a third resistor R3, and the receiving circuit 410 includes a fourth resistor R4;

[0094] The first end of the third resistor R3 is connected to the second end of the second transistor T2, and the second end of the third resistor R3 is connected to the first digital ground;

[0095] The first end of the fourth resistor R4 is connected to the second power receiving end of the receiving circuit, and the second end of the fourth resistor R4 is connected to the second digital ground.

[0096] A third resistor R3 is connected in series between the second end of the second transistor T2 and the first digital ground. The third resistor can play a role in current limiting to protect the devices of the electrostatic protection module 310 from being damaged.

[0097] Similarly, a fourth resistor R4 is connected in series between the second power receiving end of the receiving circuit and the second digital ground. The fourth resistor can play a role in current limiting to further protect the devices of the receiving circuit 410 from being damaged.

[0098] Based on Figure 5 the embodiment shown, as Figure 6 shown, in a possible implementation, the electrostatic protection module 310 further includes a first diode D1 and a second diode D2;

[0099] The anode of the first diode D1 and the cathode of the second diode D2 are connected to the first end of the third resistor R3;

[0100] The cathode of the first diode D1 and the anode of the second diode D2 are connected to the first end of the fourth resistor R4;

[0101] The second end of the first transistor T1, the second end of the second transistor T2, the first end of the third transistor T3, and the first end of the fourth transistor T4 are connected.

[0102] Both the electrostatic protection module and the receiving circuit include ground signals. The electrostatic protection module and the receiving circuit adopt different ground signals. The ground of the electrostatic protection module is the first digital ground, and the ground of the receiving circuit is the second digital ground. When a voltage difference occurs between the first digital ground and the second digital ground, the first diode D1 or the second diode D2 can conduct, providing a conduction path between the first digital ground and the second digital ground, and consuming the static electricity through the path between the first digital ground and the second digital ground, thus preventing the components of the receiving module from being burned out.

[0103] Based on Figure 5 the embodiment shown, as Figure 7 shown, in a possible implementation manner, the electrostatic protection module 310 further includes a third diode D3 and a fourth diode D4;

[0104] The anode of the third diode D3 and the cathode of the third diode D3 are connected to the second end of the third resistor R3;

[0105] The cathode of the fourth diode D4 and the anode of the fourth diode D4 are connected to the second end of the fourth resistor R4.

[0106] Both the electrostatic protection module and the receiving circuit include ground signals. The electrostatic protection module and the receiving circuit adopt different ground signals. The ground of the electrostatic protection module is the first digital ground, and the ground of the receiving circuit is the second digital ground. When a voltage difference occurs between the first digital ground and the second digital ground, the third diode D3 or the fourth diode D4 can conduct, providing a conduction path between the first digital ground and the second digital ground, and consuming the static electricity through the path between the first digital ground and the second digital ground, thus preventing the components of the receiving module from being burned out.

[0107] Based on the above embodiment, as Figure 8 , Figure 8 This is the seventh structural schematic diagram of a display driving chip provided by an embodiment of the present application. Figure 8 Among them, the receiving circuit includes a fifth diode D5, a sixth diode D6, a transistor M1, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and R1 is the first resistor.

[0108] The first end of the sixth transistor T6 of the receiving circuit is connected to a second high-level signal, and the first end of the seventh transistor T7 of the receiving circuit is connected to a third high-level signal. The second high-level signal and the third high-level signal can be provided by a voltage signal generated inside the DDIC or by an external voltage signal, which is not limited herein.

[0109] Exemplarily, if the first IO interface is connected to a 1.2V voltage signal generated inside the DDIC, then the first IO interface can provide a 1.2V voltage signal. When the first end of the seventh transistor T7 needs to be 1.2V when connected to the third high-level signal, the first end of the seventh transistor T7 can be connected to the first IO interface.

[0110] The first high-level signal can be provided by a voltage signal generated inside the DDIC or by an external voltage signal, which is not limited here.

[0111] When a voltage difference is generated between the first digital ground and the second digital ground, the third diode D3 or the fourth diode D4 can conduct, providing a conduction path between the first digital ground and the second digital ground, and dissipating the static electricity through the path between the first digital ground and the second digital ground to avoid burning out the devices of the receiving module.

[0112] Based on the above embodiment, when the electrostatic protection module 310 further includes a first diode D1 and a second diode D2, the first diode D1 and the second diode D2 can be arranged at a position close to the first IO interface, such as Figure 9 at A2 in Figure 9 is the modified DDIC layout. Figure 9 In Figure 9 IP is the junction circuit position of the first digital ground and the second digital ground,

[0113] When the electrostatic protection module 310 further includes a third diode D3 and a fourth diode D4, the third diode D3 and the fourth diode D4 can be arranged at a position close to between the first digital ground and the second digital ground, such as Figure 9 at A1 in

[0114] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0115] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for the relevant parts, reference can be made to the partial description of the method embodiment.

[0116] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are all included in the protection scope of the present application.

Claims

1. A display driving chip, characterized in that, Comprising: A first voltage signal generation module, a first IO interface; The first voltage signal generation module is used to generate a first voltage signal, and the first IO interface is short-circuited with the output end of the first voltage signal generation module, wherein the first voltage signal is a voltage signal not generated by the main board of the display device where the display driving chip is located.

2. The display driving chip according to claim 1, wherein The first voltage signal generation module is used to generate a voltage signal of 1.2V.

3. The display driving chip according to claim 1, wherein It further comprises an electrostatic protection module; The electrostatic protection module is arranged between the first IO interface and the receiving circuit, and the receiving circuit is used to receive the first voltage signal output by the first IO interface.

4. The display driving chip according to claim 3, wherein The display driving chip further comprises a first resistor; The first resistor is connected in series between the electrostatic protection module and the receiving circuit.

5. The display driving chip according to claim 3, wherein The electrostatic protection module comprises a first digital ground, and the receiving circuit comprises a second digital ground; The first digital ground is short-circuited with the second digital ground.

6. The display driving chip according to claim 3, wherein The electrostatic protection module comprises a first transistor, a second transistor, a second resistor, a third transistor, and a fourth transistor; The first end of the first transistor, the first end of the second transistor, and the first end of the second resistor are all connected to the first IO interface; The second end of the first transistor is connected to the first digital ground; the second end of the second transistor is connected to a first high-level signal; The second end of the second resistor is connected to the first end of the third transistor and the first end of the fourth transistor; The second ends of the third transistor and the fourth transistor are both connected to the receiving signal end of the receiving circuit; The first power supply receiving end of the receiving circuit is connected to a second high-level signal; The second power supply receiving end of the receiving circuit is connected to the second digital ground.

7. The display driving chip according to claim 6, wherein The electrostatic protection module further comprises a third resistor, and the receiving circuit comprises a fourth resistor; The first end of the third resistor is connected to the second end of the second transistor, and the second end of the third resistor is connected to the first digital ground; The first end of the fourth resistor is connected to the second power supply receiving end of the receiving circuit, and the second end of the fourth resistor is connected to the second digital ground.

8. The display driving chip according to claim 7, wherein The electrostatic protection module further comprises a first diode and a second diode; The anode of the first diode and the cathode of the second diode are connected to the first end of the third resistor; The cathode of the first diode and the anode of the second diode are connected to the first end of the fourth resistor; The second end of the first transistor, the second end of the second transistor, the first end of the third transistor, and the first end of the fourth transistor are connected.

9. The display driving chip according to claim 7, wherein, The electrostatic protection module further comprises a third diode and a fourth diode; The anode and the cathode of the third diode are connected to the second end of the third resistor; The cathode and the anode of the fourth diode are connected to the second end of the fourth resistor.

10. A display device, characterized in that, Comprising the display driving chip according to any one of claims 1-9.

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