Pixel circuit and driving method thereof

Abstract

The invention provides a pixel circuit and a driving circuit of the pixel circuit. The pixel circuit includes the following elements. The driving circuit comprises a first transistor, the first transistor generates a driving current according to the voltage of a node during the enabling period of the driving signal, and the brightness of the light emitting diode is changed along with the driving current. The first control circuit is used for resetting the voltage of the capacitor in a first period and applying a plurality of reference voltages to the two ends of the first transistor respectively. The second control circuit is coupled to the capacitor and is used for writing the gray scale voltage into the capacitor in a second period. The interval between the first period and the second period is larger than the time length of the first period or the time length of the second period by two times.

Description

Technical Field

[0001] The present disclosure relates to a pixel circuit and a driving method thereof, which can solve the image retention problem. Background Art

[0002] The image retention problem of a display panel usually occurs in devices using liquid crystal display or organic light-emitting diode technology. The image retention phenomenon refers to the situation where, after a specific image has been on the display screen for a long time, even if the image has been switched or removed, the residual trace of the image still temporarily exists on the screen. This problem is usually related to the unstable performance of the thin film transistor (TFT) substrate, especially the TFT hysteresis phenomenon. The TFT hysteresis phenomenon can cause the driving voltage to shift after being applied for a long time, and then the pixel driving voltage recovers slowly, resulting in the failure to clear the image information in time, thus generating the image retention effect.

[0003] In addition, the on-dot problem in a display panel refers to the situation where some pixels remain in a high-brightness state for a long time and cannot adjust the brightness or turn off normally. This problem may also be related to the physical property changes of the TFT structure. Especially during long-term operation or in a high-temperature environment, the electron migration inside the TFT will be affected, resulting in a continuous conduction state. In addition, material degradation, an increase in gate leakage current, or the accumulation of charge trapping effects may also cause the on-dot problem. The accumulation of these problems will have a negative impact on the display quality. Summary of the Invention

[0004] The present invention provides a pixel circuit and a driving method thereof. By increasing the interval between two signals, the image retention problem can be solved, and by setting multiple enabling periods for the control signal, the on-dot problem can be solved.

[0005] The present invention provides a pixel circuit, including the following components. A capacitor is coupled to a node. A driving circuit is coupled to the capacitor and includes a first transistor. During the enabling period of the driving signal, the first transistor generates a driving current according to the voltage of the node. A light-emitting diode is coupled to the driving circuit, and the brightness of the light-emitting diode changes with the driving current. A first control circuit is coupled to the capacitor and is used to reset the voltage of the capacitor during a first period and apply multiple reference voltages to both ends of the first transistor respectively. A second control circuit is coupled to the capacitor and is used to write a grayscale voltage into the capacitor during a second period. The interval between the above-mentioned first period and the second period is greater than the time length of the first period or twice the time length of the second period.

[0006] In an embodiment of the present invention, the above-mentioned capacitor includes: a first capacitor, whose first end is coupled to the control end of a first transistor; and a second capacitor, whose first end is coupled to the second end of the first capacitor, and whose second end is coupled to the first end of the first transistor.

[0007] In an embodiment of the present invention, the above-mentioned driving circuit further includes: a second transistor, whose first end is coupled to the first end of a light-emitting diode, whose second end is coupled to the second end of the first transistor, and whose control end receives a driving signal; and a third transistor, whose first end is coupled to the first end of the first transistor, whose second end is coupled to a system voltage, and whose control end receives a driving signal.

[0008] In an embodiment of the present invention, the above-mentioned reference voltage includes a first reference voltage and a second reference voltage. The first control circuit includes: a fourth transistor, whose first end is coupled to the first reference voltage, whose second end is coupled to the second end of the second capacitor and the first end of the first transistor, and whose control end receives a control signal; a fifth transistor, whose first end is coupled to the second reference voltage, whose second end is coupled to the control end of the first transistor, and whose control end receives a reset signal; and a sixth transistor, whose first end is coupled to the second reference voltage, whose second end is coupled to the second end of the first capacitor, and whose control end receives a reset signal.

[0009] In an embodiment of the present invention, the above-mentioned second control circuit includes: a seventh transistor, whose first end is coupled to the second end of the second transistor, whose second end is coupled to the second end of the fifth transistor, and whose control end receives a compensation signal; an eighth transistor, whose first end is coupled to a grayscale voltage, whose second end is coupled to the second end of the first capacitor, and whose control end receives a write signal; and a ninth transistor, whose first end is coupled to the second reference voltage, whose second end is coupled to the second end of the first capacitor, and whose control end receives a compensation signal.

[0010] In an embodiment of the present invention, the enabling period of the above-mentioned control signal partially overlaps with the enabling period of the reset signal, the enabling period of the compensation signal, and the enabling period of the write signal. Wherein the first period is the same as the enabling period of the reset signal, and the second period is included in the enabling period of the compensation signal and the enabling period of the write signal.

[0011] In an embodiment of the present invention, the above-mentioned control signal includes a first enabling period and a second enabling period, and the first enabling period and the second enabling period are not continuous. The first enabling period partially overlaps with the enabling period of the reset signal, and the second enabling period partially overlaps with the enabling period of the compensation signal and the enabling period of the write signal. The above-mentioned first period is the same as the enabling period of the reset signal, and the second period is the same as the enabling period of the compensation signal.

[0012] In an embodiment of the present invention, the first end of the capacitor is coupled to the control end of the first transistor. The driving circuit further includes: a second transistor, whose first end is coupled to the first end of the light-emitting diode, whose second end is coupled to the first end of the first transistor, and whose control end receives a driving signal; and a third transistor, whose first end is coupled to a system voltage, whose second end is coupled to the second end of the first transistor and the second end of the capacitor, and whose control end receives a driving signal.

[0013] In an embodiment of the present invention, the above-mentioned reference voltage includes a first reference voltage and a second reference voltage. The first control circuit includes: a fourth transistor, whose first end is coupled to the first reference voltage, whose second end is coupled to the second end of the capacitor and the second end of the first transistor, and whose control end receives a control signal; a fifth transistor, whose first end is coupled to the second reference voltage, whose second end is coupled to the control end of the first transistor, and whose control end receives a reset signal.

[0014] In an embodiment of the present invention, the above-mentioned second control circuit includes: a sixth transistor, whose first end is coupled to the first end of the first transistor, whose second end is coupled to the control end of the first transistor, and whose control end receives a write signal; and a seventh transistor, whose first end is coupled to a grayscale voltage, whose second end is coupled to the second end of the capacitor, and whose control end receives a write signal.

[0015] In an embodiment of the present invention, the above-mentioned control signal includes a first enabling period and a second enabling period. The first enabling period partially overlaps with the enabling period of the reset signal, and the second enabling period partially overlaps with the enabling period of the write signal. The first period is the same as the enabling period of the reset signal, and the second period is the same as the enabling period of the write signal.

[0016] In an embodiment of the present invention, the above-mentioned reference voltage includes a first reference voltage and a second reference voltage. The first control circuit includes: a fourth transistor, whose first end is coupled to the first reference voltage, whose second end is coupled to the second end of the capacitor and the second end of the first transistor, and whose control end receives a reset signal; a fifth transistor, whose first end is coupled to the second reference voltage, whose second end is coupled to the control end of the first transistor, and whose control end receives a reset signal.

[0017] In an embodiment of the present invention, the above-mentioned second control circuit includes: a sixth transistor, whose first end is coupled to the first end of the first transistor, whose second end is coupled to the control end of the first transistor, and whose control end receives a write signal; a seventh transistor, whose first end is coupled to a grayscale voltage, whose second end is coupled to the second end of the capacitor, and whose control end receives a write signal; and an eighth transistor, whose first end is coupled to the first reference voltage, whose second end is coupled to the second end of the capacitor, and whose control end receives a write signal.

[0018] In an embodiment of the present invention, the above-mentioned first period is the same as the enabling period of the reset signal, and the second period is the same as the enabling period of the write signal.

[0019] In another aspect, an embodiment of the present invention provides a driving method for a pixel circuit. The pixel circuit includes at least one capacitor, a first transistor, and a light-emitting diode. The driving method includes: resetting the voltage of the capacitor by a first control circuit during a first period and applying a plurality of reference voltages to both ends of the first transistor; writing a grayscale voltage to the capacitor by a second control circuit during a second period, wherein the interval between the first period and the second period is greater than the time length of the first period or twice the time length of the second period; and generating a driving current by the first transistor during the enabling period of the driving signal to drive the light-emitting diode, and the brightness of the light-emitting diode changes with the driving current.

[0020] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are given below and described in detail in conjunction with the accompanying drawings of the specification as follows. Description of the Drawings

[0021] Figure 1 is a circuit diagram showing a pixel circuit according to a first embodiment.

[0022] Figure 2 is a timing diagram showing various signals according to a first embodiment.

[0023] Figure 3 is a schematic diagram showing the bias voltage on transistor T1 according to an embodiment.

[0024] Figure 4 is a schematic diagram showing scanning and intervals according to a first embodiment.

[0025] Figure 5 is a timing diagram showing various signals according to another embodiment.

[0026] Figure 6 is a schematic diagram showing leakage current according to an embodiment.

[0027] Figure 7 is a circuit diagram showing a pixel circuit according to a second embodiment.

[0028] Figure 8 is a timing diagram showing various signals according to a second embodiment.

[0029] Figure 9 is a circuit diagram showing a pixel circuit according to a third embodiment.

[0030] Figure 10 is a timing diagram showing various signals according to a third embodiment.

[0031] Figure 11 It is a flowchart showing a driving method of a pixel circuit according to an embodiment.

[0032] Description of reference numerals:

[0033] 100, 700, 900: Pixel circuit

[0034] 110, 710, 910: Driving circuit

[0035] 120, 130, 720, 730, 920, 930: Control circuit

[0036] 140: Test circuit

[0037] EM: Driving signal

[0038] VC: Control signal

[0039] CS: Compensation signal

[0040] WS: Write signal

[0041] RS: Reset signal

[0042] Vsig: Gray-scale voltage

[0043] Vref, Vini: Reference voltage

[0044] VDD, VSS: System voltage

[0045] Id, Ik: Current

[0046] 201, 801, 1001: First period

[0047] 202, 802, 1002: Second period

[0048] 210, 220, 230, 240, 420, 501, 502, 811, 812, 820, 830, 840, 1010, 1020, 1030: Enable period

[0049] 250, 850, 1050: Interval

[0050] 410: Region

[0051] 421, 422: Blank period

[0052] 1101~1103: Steps

[0053] C1~C3: Capacitors

[0054] LED1, LED2: Light-emitting diodes

[0055] N1, N2: Nodes

[0056] T1 to T10: Transistors

[0057] Test1: Test Signal Detailed Embodiment

[0058] Some embodiments of the present invention will be described in detail with reference to the accompanying drawings hereinafter. For the component symbols cited in the following description, when the same component symbols appear in different drawings, they will be regarded as the same or similar components. These embodiments are only a part of the present invention and do not disclose all the implementable ways of the present invention. More precisely, these embodiments are only examples of the systems and methods within the scope of the patent application of the present invention.

[0059] Regarding the use of "first", "second", etc. in this article, it does not particularly refer to the meaning of order or sequence. It is only used to distinguish components or operations described with the same technical terms.

[0060] The term "coupled (or connected)" used throughout this specification (including the claims) may refer to any direct or indirect connection means. For example, if it is described in the text that the first device is coupled (or connected) to the second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connection means.

[0061] [First Embodiment]

[0062] Figure 1 is a circuit diagram showing a pixel circuit according to the first embodiment. Please refer to Figure 1, the pixel circuit 100 includes capacitors C1, C2, light-emitting diode LED1, driving circuit 110, control circuit 120, control circuit 130, and test circuit 140. Capacitor C1 is coupled to node N1. The driving circuit 110 is coupled to node N1 and the light-emitting diode LED1. The driving circuit 110 includes at least one driving transistor (such as transistor T1), which is used to generate a driving current Id according to the voltage on node N1 during the enabling period of the driving signal EM. This driving current Id is used to drive the light-emitting diode LED1 to provide a light source, and the brightness of the light-emitting diode LED1 changes with the driving current Id. The control circuit 120 is coupled to capacitors C1, C2, and is used to reset the voltages of capacitors C1, C2 during the first period and apply a plurality of reference voltages Vref, Vini to both ends (including the control end and one of the source and drain) of transistor T1 respectively. The control circuit 130 is also coupled to capacitors C1, C2, and is used to write the grayscale voltage Vsig into capacitors C1, C2 during the second period. In a frame, the above-mentioned first period is performed first, then the second period, and then the enabling period of the driving signal EM. Specifically, the interval between the first period and the second period is greater than the time length of the first period or the second period. That is to say, after the reference voltages Vref, Vini are applied to both ends of transistor T1 respectively, after a period of time, the grayscale voltage Vsig will be written into capacitors C1, C2. The purpose of doing this is to keep both ends of transistor T1 at a bias voltage for a period of time. During this period, the charges on the interface between the channel layer and the gate insulating layer in transistor T1 will be cleared, which can solve the afterimage problem of the pixel circuit 100.

[0063] Specifically, the first end of capacitor C1 is coupled to the control end of the first transistor, and the second end is coupled to the first end of capacitor C2. The second end of capacitor C2 is coupled to the first end of transistor T1.

[0064] The driving circuit 110 further includes transistors T2, T3. The first end of transistor T2 is coupled to the first end (anode) of the light-emitting diode LED1, the second end is coupled to the second end of transistor T1, and the control end receives the driving signal EM. The second end (cathode) of the light-emitting diode LED1 is coupled to the system voltage VSS. The first end of transistor T3 is coupled to the first end of transistor T1, the second end is coupled to the system voltage VDD, and the control end receives the driving signal EM.

[0065] The control circuit 120 includes transistors T4 to T6. The first end of transistor T4 is coupled to the reference voltage Vref, the second end is coupled to the second end of capacitor C2 and the first end of transistor T1, and the control end receives the control signal VC. The first end of transistor T5 is coupled to the reference voltage Vini, the second end is coupled to the control end of transistor T1, and the control end receives the reset signal RS. The first end of transistor T6 is coupled to the reference voltage Vini, the second end is coupled to the second end of capacitor C1, and the control end receives the reset signal RS.

[0066] The control circuit 130 includes transistors T7 to T9. The first end of transistor T7 is coupled to the second end of transistor T2 and the second end of transistor T1, the second end is coupled to the second end of transistor T5 and the control end of transistor T1, and the control end receives the compensation signal CS. The first end of transistor T8 is coupled to the grayscale voltage Vsig, the second end is coupled to the second end of capacitor C1 and the first end of capacitor C2, and the control end receives the write signal WS. The first end of transistor T9 is coupled to the reference voltage Vini, the second end is coupled to the second end of capacitor C1 and the first end of capacitor C2, and the control end receives the compensation signal CS.

[0067] The test circuit 140 includes transistor T10. The first end of transistor T10 is coupled to the grayscale voltage Vsig, the second end is coupled to the anode of the light-emitting diode LED1, and the control end receives the test signal Test1. Transistor T10 is turned on during the test, otherwise transistor T10 is turned off.

[0068] Figure 2 FIG. is a timing diagram showing each signal according to the first embodiment. In this embodiment, transistors T1 to T9 are P-type transistors, and the control signal VC, the reset signal RS, the compensation signal CS, and the write signal WS are all at logic low level during their respective enabling periods. The enabling period 210 of the control signal VC partially overlaps with the enabling period 220 of the reset signal RS, the enabling period 230 of the compensation signal CS, and the enabling period 240 of the write signal WS.

[0069] During the enabling period 210 of the control signal VC, the transistor T4 is turned on, and the reference voltage Vref is applied to the first end of the transistor T1. During the enabling period 220 of the reset signal RS, the transistors T5 and T6 are turned on, and the reference voltage Vini is applied to both ends of the capacitor C1 and the first end of the capacitor C2. In addition, the reference voltage Vini is also applied to the control end of the transistor T1. Therefore, the voltages of the capacitors C1 and C2 are reset. The enabling period 220 of the reset signal RS is also referred to as the first period 201. During the enabling period 230 of the compensation signal CS, the transistors T7 and T9 are turned on, and the voltage on the node N1 reflects the threshold voltage of the transistor T1. During the enabling period 240 of the write signal WS, the transistor T8 is turned on, and the grayscale voltage Vsig is written to the capacitors C1 and C2. The second period 202 includes the enabling period 230 of the compensation signal CS and the enabling period 240 of the write signal WS. In particular, the interval 250 between the first period 201 and the second period 202 is greater than the time length of the first period 201 or twice the time length of the second period 202. In this embodiment, the second period 202 includes two discontinuous periods 230 and 240. The above-mentioned "interval between the first period and the second period" refers to the interval 250 between the first period 201 and the nearer enabling period 230, rather than the interval between the first period 201 and the farther enabling period 240. For example, the lengths of the enabling periods of the reset signal RS, the compensation signal CS, and the write signal WS are all 1H, where H is a variable. The time length of the interval 250 is greater than 2H. In some embodiments, the interval 250 can also be greater than 4H, 6H, 8H, 12H, 20H, etc. For example, the interval 250 can be set to 12H, 60H, 84H, etc., and the present invention is not limited thereto.

[0070] Figure 3 is a schematic diagram showing the bias voltage on the transistor T1 according to an embodiment. Please refer to Figure 2 and Figure 3, in interval 250, the voltage on the gate G of transistor T1 is the reference voltage Vini, and the voltage on the source S is the reference voltage Vref. In this example, the reference voltage Vini is 11V, the reference voltage Vref is 14V, and the threshold voltage of transistor T1 is -1.5V. Therefore, transistor T1 is conducting, and the voltage on the drain D is also 14V. The bias voltage Vgd between the gate G and the drain D of transistor T1 must be less than or equal to the threshold voltage of transistor T1. In this example, the bias voltage Vgd = 11V - 14V = -3V, and this less than or equal to relationship is expressed as -3V ≤ -1.5V. If the bias voltage Vgd is too close to the threshold voltage, transistor T1 is not fully conducting, and it is not easy to solve the problem of image sticking; if the absolute value of the bias voltage Vgd is too large, it may exceed the breakdown voltage of transistor T1. In some embodiments, the absolute value of the difference between the reference voltage Vref and the reference voltage Vini (forming the bias voltage Vgd) is twice the absolute value of the threshold voltage of transistor T1, but the present invention is not limited thereto.

[0071] In interval 250, since transistor T1 is conducting and the bias voltage Vgd is negative, this can clear the charges in the gate insulating layer of transistor T1 and solve the problem of image sticking. The longer the time length of interval 250, the shorter the image sticking time. In an experiment, when the time length of interval 250 is 1H, the image sticking time is 5 seconds; when the time length of interval 250 is 12H, the image sticking time is 4 seconds; when the time length of interval 250 is 60H, the image sticking time is 2 seconds; when the time length of interval 250 is 84H, the image sticking time is 1.2 seconds.

[0072] Figure 4 is a schematic diagram showing scanning and intervals according to the first embodiment. Please refer to Figure 4 the upper half of. The horizontal axis is time, and a blanking period is set every once in a while, such as blanking periods 421 and 422. The vertical axis is the columns in the pixel array (the scanning order is from top to bottom). The numbers 1 to 30 on the horizontal axis represent the frames, and the scanning of each frame can be represented as a diagonal line from the upper left to the lower right. The second frame starts scanning before the first frame is scanned completely. The enlarged area 410 in the upper half is shown in Figure 4The lower half describes the signals on a certain scan line. There is an interval 250 between the enabling period 220 of the reset signal RS and the enabling period 230 of the compensation signal CS. During this period, the screen is not updated. Therefore, there will be a horizontal stripe in the image displayed on the pixel array, and the human eye will not perceive this stripe after integrating these image changes. The pixel array displays multiple images per second, and only one or a few of these images will have a relatively long interval 250 (such as 60H), while the interval between the enabling period 220 of the reset signal RS and the enabling period 230 of the compensation signal CS in other images is, for example, 1H.

[0073] Please refer to Figure 1 and Figure 4 , during the enabling period 420 of the driving signal EM, transistors T1 - T3 are turned on, and transistor T1 generates a driving current Id based on the voltage at node N1 to drive the light emitting diode LED1.

[0074] Figure 5 is a timing diagram showing each signal according to another embodiment. Please refer to Figure 1 and Figure 5 , Figure 5 The timing diagram of Figure 1 can be applied to the circuit of Figure 5 and Figure 2 The difference between Figure 5 is that in

[0075] Figure 6 is a schematic diagram showing the leakage current according to an embodiment. Please refer to Figure 5 and Figure 6 , if transistor T4 is turned on and electrostatic discharge or other phenomena occur to turn on transistor T2, a leakage current Ik may be generated, which will cause the light emitting diode LED1 to emit light and form a bright spot on the pixel array. However, after adopting the embodiment of Figure 5 , as shown in Figure 6As shown, when the control signal VC is not enabled, the transistor T4 is cut off, which can avoid the generation of leakage current Ik, thus solving the problem of bright spots.

[0076] [Second Embodiment]

[0077] Figure 7 is a circuit diagram showing a pixel circuit according to the second embodiment. Please refer to Figure 7 , the pixel circuit 700 includes a capacitor C3, a light-emitting diode LED2, a driving circuit 710, a control circuit 720, and a control circuit 730. The capacitor C3 is coupled to the node N2. The driving circuit 710 includes at least one transistor T1, which generates a driving current Id according to the voltage on the node N2 to drive the light-emitting diode LED2. The control circuit 720 is used to apply two reference voltages Vref and Vini across the transistor T1 during a first period. The control circuit 730 is used to write a grayscale voltage Vsig into the capacitor C3 during a second period and make the node N2 reflect the threshold voltage of the transistor T1. The interval between the first period and the second period is greater than the time length of the first period or twice the time length of the second period.

[0078] Specifically, the first end of the capacitor C3 is coupled to the control end of the transistor T1, and the second end is coupled to the second end of the transistor T1. The driving circuit 710 further includes transistors T2 and T3. The first end of the transistor T2 is coupled to the first end (anode) of the light-emitting diode LED2, the second end is coupled to the first end of the transistor T1, and the control end receives a driving signal EM. The second end (cathode) of the light-emitting diode LED2 is coupled to the system voltage VSS. The first end of the transistor T3 is coupled to the system voltage VDD, the second end is coupled to the second end of the transistor T1 and the second end of the capacitor C3, and the control end receives the driving signal EM.

[0079] The control circuit 720 includes transistors T4 and T5. The first end of the transistor T4 is coupled to the reference voltage Vref, the second end is coupled to the second end of the capacitor C3 and the second end of the transistor T1, and the control end receives a control signal VC. The first end of the transistor T5 is coupled to the reference voltage Vini, the second end is coupled to the control end of the transistor T1 and the first end of the capacitor C3, and the control end receives a reset signal RS.

[0080] The control circuit 730 includes transistors T6 and T7. The first end of the transistor T6 is coupled to the first end of the transistor T1 and the second end of the transistor T2, the second end is coupled to the control end of the transistor T1, and the control end receives a write signal WS. The first end of the transistor T7 is coupled to the grayscale voltage Vsig, the second end is coupled to the second end of the capacitor C3 and the second end of the transistor T1, and the control end receives the write signal WS.

[0081] Figure 8 It is a timing diagram showing each signal according to the second embodiment. The control signal VC has enabling periods 811 and 812, and these two enabling periods 811 and 812 are not continuous. The enabling period 811 partially overlaps with the enabling period 820 of the reset signal RS, and the enabling period 812 partially overlaps with the enabling period 830 of the write signal WS. In this embodiment, the first period 801 is the same as the enabling period 820 of the reset signal RS, and the second period 802 is the same as the enabling period 830 of the write signal WS. The interval 850 between the first period 801 and the second period 802 is greater than the time length of the first period 801 or twice the time length of the second period 802. For example, the time lengths of the first period 801 and the second period 802 are 1H, and the length of the interval 850 is 60H, but the present invention is not limited thereto.

[0082] During the first period 801, the transistors T4 and T5 are turned on, the reference voltage Vref is applied to the second ends of the transistor T1 and the capacitor C3, and the reference voltage Vini is applied to the control end of the transistor T1 and the first end of the capacitor C3. In this way, the voltage of the capacitor C3 is reset. During the second period 802, the transistors T4, T6, and T7 are turned on, the grayscale voltage Vsig is written into the capacitor C3, and the voltage on the node N2 reflects the threshold voltage of the transistor T1. During the enabling period 840 of the driving signal EM, the transistors T1 to T3 are turned on, and the transistor T1 generates a driving current Id according to the voltage on the node N2 to drive the light-emitting diode LED2.

[0083] Similar to the first embodiment, the interval 850 can solve the problem of image sticking, and the two enabling periods 811 and 812 of the control signal VC can solve the problem of bright dots. In some embodiments, the control signal VC may also have only one continuous enabling period, which partially overlaps with the enabling period 820 and the enabling period 830.

[0084] [Third Embodiment]

[0085] Figure 9 It is a circuit diagram showing a pixel circuit according to the third embodiment. Please refer to Figure 9 , the pixel circuit 900 includes a capacitor C3, a light-emitting diode LED2, a driving circuit 910, a control circuit 920, and a control circuit 930. The driving circuit 910 is similar to Figure 7 the driving circuit 710, so the coupling relationships of the transistors T1 to T3 will not be repeated here.

[0086] The control circuit 920 includes transistors T4 and T5. A first end of the transistor T4 is coupled to a reference voltage Vref, a second end is coupled to a second end of the capacitor C3 and a second end of the transistor T1, and a control end receives a reset signal RS. A first end of the transistor T5 is coupled to a reference voltage Vini, a second end is coupled to a control end of the transistor T1 and a first end of the capacitor C3, and a control end receives the reset signal RS.

[0087] The control circuit 930 includes transistors T6 to T8. A first end of the transistor T6 is coupled to a first end of the transistor T1, a second end is coupled to a control end of the transistor T1, and a control end receives a write signal WS. A first end of the transistor T7 is coupled to a grayscale voltage Vsig, a second end is coupled to a second end of the capacitor C3 and a second end of the transistor T1, and a control end receives the write signal WS. A first end of the transistor T8 is coupled to the reference voltage Vref, a second end is coupled to a second end of the capacitor C3, and a control end receives the write signal WS.

[0088] Figure 10 is a timing diagram showing each signal according to the third embodiment. Please refer to Figure 9 and Figure 10 , the enabling period 1010 of the reset signal RS is the same as the first period 1001, and the enabling period 1020 of the write signal WS is the same as the second period 1002. During the first period 1001, the transistors T4 and T5 are turned on, the reference voltage Vref is applied to the second end of the transistor T1, and the reference voltage Vini is applied to the control end of the transistor T1. In addition, the reference voltage Vref and the reference voltage Vini are also applied to both ends of the capacitor C3 to reset the voltage of the capacitor C3. During the second period 1002, the transistors T6 to T8 are turned on, and the grayscale voltage Vsig is written into the capacitor C3. During the enabling period 1030 of the driving signal EM, the transistors T1 to T3 are turned on, and the transistor T1 generates a driving current Id according to the voltage on the node N2 to drive the light-emitting diode LED2.

[0089] The interval 1050 between the first period 1001 and the second period 1002 is greater than the time length of the first period 1001 or twice the time length of the second period 1002. For example, the time lengths of the first period 1001 and the second period 1002 are 1H, and the time length of the interval 1050 is 60H, but the present invention is not limited thereto.

[0090] Figure 11 is a flowchart showing a driving method of a pixel circuit according to an embodiment. Please refer to Figure 11 , Figure 11The method can be applied to the above first to third embodiments. In step 1101, the voltage of at least one capacitor is reset by a first control circuit during a first period, and a plurality of reference voltages are respectively applied to both ends of a first transistor, which is also called a driving transistor. In step 1102, a grayscale voltage is written into the capacitor by a second control circuit during a second period, wherein the interval between the first period and the second period is greater than the time length of the first period or twice the time length of the second period. In step 1103, a driving current is generated by the first transistor during the enabling period of the driving signal to drive the light-emitting diode, and the brightness of the light-emitting diode changes with the driving current. Figure 11 Each step has been described in detail above and will not be elaborated here.

[0091] In the above proposed pixel circuit and driving method, by lengthening the interval between the first period and the second period, the problem of image sticking can be solved. In addition, when the control signal has two discontinuous enabling periods, leakage current can be avoided and the problem of bright spots can be solved.

[0092] Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention. Any person skilled in the art, without departing from the concept and scope of the present invention, may make some changes and modifications. Therefore, the protection scope of the present invention shall be subject to that defined by the claims.

Claims

1. A pixel circuit, comprising: At least one capacitor coupled to a node; A driving circuit coupled to the at least one capacitor, the driving circuit including a first transistor that generates a driving current according to the voltage of the node during the enabling period of a driving signal; A light-emitting diode coupled to the driving circuit, wherein the brightness of the light-emitting diode changes with the driving current; A first control circuit coupled to the at least one capacitor for resetting the voltage of the at least one capacitor and applying a plurality of reference voltages to both ends of the first transistor respectively during a first period; A second control circuit coupled to the at least one capacitor for writing a grayscale voltage to the at least one capacitor during a second period; Wherein the interval between the first period and the second period is greater than the time length of the first period or twice the time length of the second period.

2. The pixel circuit according to claim 1, wherein the at least one capacitor includes: A first capacitor, the first end of which is coupled to the control end of the first transistor; and A second capacitor, the first end of which is coupled to the second end of the first capacitor, and the second end of which is coupled to the first end of the first transistor.

3. The pixel circuit according to claim 2, wherein the driving circuit further includes: A second transistor, the first end of which is coupled to the first end of the light-emitting diode, the second end of which is coupled to a second end of the first transistor, and the control end of which receives the driving signal; and A third transistor, the first end of which is coupled to the first end of the first transistor, the second end of which is coupled to a system voltage, and the control end of which receives the driving signal.

4. The pixel circuit according to claim 3, wherein the reference voltages include a first reference voltage and a second reference voltage, and the first control circuit includes: A fourth transistor, the first end of which is coupled to the first reference voltage, the second end of which is coupled to the second end of the second capacitor and the first end of the first transistor, and the control end of which receives a control signal; A fifth transistor, the first end of which is coupled to the second reference voltage, the second end of which is coupled to the control end of the first transistor, and the control end of which receives a reset signal; and A sixth transistor, the first end of which is coupled to the second reference voltage, the second end of which is coupled to the second end of the first capacitor, and the control end of which receives the reset signal.

5. The pixel circuit according to claim 4, wherein the second control circuit includes: A seventh transistor, the first end of which is coupled to the second end of the second transistor, the second end of which is coupled to the second end of the fifth transistor, and the control end of which receives a compensation signal; An eighth transistor, the first end of which is coupled to the grayscale voltage, the second end of which is coupled to the second end of the first capacitor, and the control end of which receives a write signal; and A ninth transistor, the first end of which is coupled to the second reference voltage, the second end of which is coupled to the second end of the first capacitor, and the control end of which receives the compensation signal.

6. The pixel circuit as claimed in claim 5, wherein a coincidence period of the control signal partially overlaps a coincidence period of the reset signal, a coincidence period of the compensation signal, and a coincidence period of the write signal. Wherein the first period is the same as the enable period of the reset signal, and the second period is included in the enable period of the compensation signal and the enable period of the write signal.

7. The pixel circuit as claimed in claim 5, wherein the control signal includes a first enable period and a second enable period, the first enable period and the second enable period are discontinuous, the first enable period overlaps a coincidence period of the reset signal, and the second enable period partially overlaps a coincidence period of the compensation signal and a coincidence period of the write signal. Wherein the first period is the same as the enable period of the reset signal, and the second period is the same as the enable period of the compensation signal.

8. The pixel circuit as claimed in claim 1, wherein a first end of the at least one capacitor is coupled to a control end of the first transistor, and the driving circuit further includes: a second transistor, a first end of which is coupled to a first end of the light emitting diode, a second end of which is coupled to the first end of the first transistor, and a control end of which receives the driving signal; and a third transistor, a first end of which is coupled to a system voltage, a second end of which is coupled to a second end of the first transistor and a second end of the at least one capacitor, and a control end of which receives the driving signal.

9. The pixel circuit as claimed in claim 8, wherein the reference voltages include a first reference voltage and a second reference voltage, and the first control circuit includes: a fourth transistor, a first end of which is coupled to the first reference voltage, a second end of which is coupled to the second end of the at least one capacitor and the second end of the first transistor, and a control end of which receives a control signal; a fifth transistor, a first end of which is coupled to the second reference voltage, a second end of which is coupled to the control end of the first transistor, and a control end of which receives a reset signal.

10. The pixel circuit as claimed in claim 9, wherein the second control circuit includes: a sixth transistor, a first end of which is coupled to the first end of the first transistor, a second end of which is coupled to the control end of the first transistor, and a control end of which receives a write signal; and a seventh transistor, a first end of which is coupled to the grayscale voltage, a second end of which is coupled to the second end of the at least one capacitor, and a control end of which receives the write signal.

11. The pixel circuit as claimed in claim 10, wherein the control signal includes a first enable period and a second enable period, the first enable period partially overlaps a coincidence period of the reset signal, and the second enable period partially overlaps a coincidence period of the write signal. Wherein the first period is the same as the enable period of the reset signal, and the second period is the same as the enable period of the write signal.

12. The pixel circuit as claimed in claim 8, wherein the reference voltages include a first reference voltage and a second reference voltage, and the first control circuit includes: A fourth transistor, having a first end coupled to the first reference voltage, a second end coupled to the second end of the at least one capacitor and the second end of the first transistor, and a control end receiving a reset signal; A fifth transistor, having a first end coupled to the second reference voltage, a second end coupled to the control end of the first transistor, and a control end receiving the reset signal.

13. The pixel circuit according to claim 12, wherein the second control circuit includes: A sixth transistor, having a first end coupled to the first end of the first transistor, a second end coupled to the control end of the first transistor, and a control end receiving a write signal; and A seventh transistor, having a first end coupled to the grayscale voltage, a second end coupled to the second end of the at least one capacitor, and a control end receiving the write signal; and An eighth transistor, having a first end coupled to the first reference voltage, a second end coupled to the second end of the at least one capacitor, and a control end receiving the write signal.

14. The pixel circuit according to claim 13, wherein the first period is the same as the enabling period of the reset signal, and the second period is the same as the enabling period of the write signal.

15. A driving method for a pixel circuit, wherein the pixel circuit includes at least one capacitor, a first transistor, and a light-emitting diode, and the driving method includes: Resetting the voltage of the at least one capacitor during a first period by a first control circuit and applying multiple reference voltages to both ends of the first transistor respectively; Writing a grayscale voltage to the at least one capacitor during a second period by a second control circuit, wherein the interval between the first period and the second period is greater than the time length of the first period or twice the time length of the second period; and Generating a driving current by the first transistor during the enabling period of a driving signal to drive the light-emitting diode, wherein the brightness of the light-emitting diode changes with the driving current.

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