Pixel circuit, driving method and display device

Abstract

The invention provides a pixel circuit, a driving method and display equipment, and relates to the technical field of pixel circuits. Comprising an eighth transistor and a ninth transistor, and the eighth transistor and the ninth transistor form a first phase inverter based on a low-temperature polycrystalline oxide structure; or, the quasi-inverter comprises a nineteenth transistor and a twentieth transistor, the source electrode of the nineteenth transistor is connected with the source electrode of the twentieth transistor, and the nineteenth transistor and the twentieth transistor form the quasi-inverter based on the oxide structure. According to the pixel circuit, the defects in the prior art are overcome, the level conversion speed is increased, then the driving capacity of the pixel circuit is improved, high-resolution and high-refresh-rate display panel driving is achieved, the utilization rate of all assemblies is increased, space occupation caused by various devices is reduced, and microminiaturization is facilitated.

Description

Technical Field

[0001] The present invention relates to the technical field of pixel circuits, and in particular, to a pixel circuit, a driving method, and a display device. Background Art

[0002] Currently, LED pixel circuits based on the PWM driving method are divided into two categories, including digital driving circuits and analog driving circuits. Digital driving circuits are simple but have complex driving timings. To achieve high-gray-scale display, additional circuits need to be introduced; with the research and optimization by researchers, analog driving circuits can currently meet the requirements of high refresh rates and high stability, promoting the low-power and high-stability display applications of AM-Micro / Mini LEDs and driving the rapid popularization and application of future displays such as in-vehicle displays, e-sports displays, and AR / VR technologies.

[0003] Existing analog driving circuits are generally composed of low-temperature polycrystalline silicon (LTPS) or metal-oxide TFTs (MOTFTs) alone. Although they can drive Micro LED displays, when the light-emitting device is turned off, the voltage and current decay times are often in the order of several microseconds or even dozens of microseconds, which is not conducive to high-resolution and high-refresh-rate displays, limiting the application of active-driven Micro LED display panels. At the same time, additional transistors need to be added to implement PWM (pulse-width modulation) and voltage-stabilizing output circuits, resulting in complex circuits and being not conducive to miniaturization.

[0004] In view of the above problems, there is currently no effective technical solution. Summary of the Invention

[0005] The purpose of the present invention is to provide a pixel circuit, a driving method, and a display device, which solve the deficiencies of the prior art, improve the level conversion speed, thereby enhancing the driving ability of the pixel circuit, achieving the driving of high-resolution and high-refresh-rate display panels, and improving the utilization rate among components, reducing the space occupied by numerous devices, and being conducive to miniaturization.

[0006] In a first aspect, the present invention provides a pixel circuit, including an eighth transistor and a ninth transistor. The eighth transistor is a thin-film transistor based on low-temperature polycrystalline silicon, and the ninth transistor is a thin-film transistor based on an oxide. The eighth transistor and the ninth transistor form a first inverter based on a low-temperature polycrystalline oxide structure. Alternatively, it includes a nineteenth transistor and a twentieth transistor. The source of the nineteenth transistor is connected to the source of the twentieth transistor, and both the nineteenth transistor and the twentieth transistor are thin-film transistors based on an oxide. The nineteenth transistor and the twentieth transistor form a quasi-inverter based on an oxide structure.

[0007] The pixel circuit provided by the present invention is mainly composed of high-mobility oxide transistors, and LTPS TFTs are added to construct an inverter circuit. While maintaining the low-power consumption characteristics of the original oxide pixel circuit, the current stability in the light-emitting stage is improved, and a fast level conversion function is achieved. Moreover, it can be used as both a level holding and a level conversion to turn on or off the light-emitting module, which is beneficial to high-resolution, high-refresh-rate displays and miniaturization.

[0008] Further, when the pixel circuit includes a first inverter composed of the eighth transistor and the ninth transistor, the pixel circuit further includes a third transistor and a sixth transistor. The third transistor is an oxide-based thin-film transistor, and the sixth transistor is a low-temperature polysilicon-based thin-film transistor; the third transistor and the sixth transistor form a second inverter based on a low-temperature polycrystalline oxide structure; the first inverter and the second inverter are cascaded to form a two-stage inverter structure.

[0009] Further, the pixel circuit further includes a first transistor, a second transistor, a fourth transistor, a fifth transistor, a seventh transistor, a tenth transistor, an eleventh transistor, a first electrolytic capacitor, a second electrolytic capacitor, and a first diode; Wherein, the drain of the first transistor is simultaneously connected to the drain of the second transistor, the source of the third transistor, and the first end of the second electrolytic capacitor, and the gate of the first transistor is connected to the gate of the fourth transistor; the second end of the second electrolytic capacitor is simultaneously connected to the source of the eighth transistor and the negative electrode of the first diode and grounded; the drain of the eleventh transistor is connected to the first end of the first electrolytic capacitor, the second end of the first electrolytic capacitor is connected to the source of the fourth transistor, the drain of the fourth transistor is simultaneously connected to the drain of the third transistor and the source of the tenth transistor, the gate of the tenth transistor is simultaneously connected to the gate of the eleventh transistor and the drain of the ninth transistor, the drain of the tenth transistor is simultaneously connected to the drain of the sixth transistor, the gate of the eighth transistor, and the gate of the ninth transistor, and the gate of the sixth transistor is simultaneously connected to the gate of the third transistor, the source of the seventh transistor, the second end of the first electrolytic capacitor, and the source of the fourth transistor; the drain of the eighth transistor is simultaneously connected to the source of the ninth transistor and the gate of the fifth transistor; the source of the fifth transistor is connected to the positive electrode of the first diode.

[0010] Further, when the pixel circuit includes a pseudo-inverter formed by a nineteenth transistor and a twentieth transistor, the pixel circuit further includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a third electrolytic capacitor, a fourth electrolytic capacitor, a fifth electrolytic capacitor, and a second diode; Wherein, the gate of the twelfth transistor is connected to the gate of the fifteenth transistor, the drain of the twelfth transistor is simultaneously connected to the drains of the fourteenth transistor and the thirteenth transistor, the gate of the thirteenth transistor is connected to the first end of the fifth electrolytic capacitor, and the second end of the fifth electrolytic capacitor is simultaneously connected to the source of the fourteenth transistor, the drain of the fifteenth transistor, the drain of the seventeenth transistor, the gate of the nineteenth transistor, and the drain of the twentieth transistor; the gate of the fourteenth transistor is connected to the second end of the third electrolytic capacitor, the drain of the eighteenth transistor, and the source of the fifteenth transistor; the source of the nineteenth transistor is simultaneously connected to the source of the twentieth transistor, the first end of the fourth electrolytic capacitor, and the gate of the sixteenth transistor, the gate of the twentieth transistor is simultaneously connected to the second end of the fourth electrolytic capacitor and the negative electrode of the second diode and grounded, and the positive electrode of the second diode is connected to the source of the sixteenth transistor.

[0011] In a second aspect, the present invention provides a driving method applied to a pixel circuit. The pixel circuit includes an eighth transistor and a ninth transistor. The eighth transistor is a thin film transistor based on low temperature polysilicon, and the ninth transistor is a thin film transistor based on oxide; the eighth transistor and the ninth transistor form a first inverter based on a low temperature polycrystalline oxide structure; the pixel circuit further includes a third transistor and a sixth transistor. The third transistor is a thin film transistor based on oxide, and the sixth transistor is a thin film transistor based on low temperature polysilicon; the third transistor and the sixth transistor form a second inverter based on a low temperature polycrystalline oxide structure; the first inverter and the second inverter are cascaded to form a two-stage inverter structure; the pixel circuit further includes a first transistor, a second transistor, a fourth transistor, a fifth transistor, a seventh transistor, a tenth transistor, an eleventh transistor, a first electrolytic capacitor, a second electrolytic capacitor, and a first diode; A first test point is provided between the second end of the first electrolytic capacitor and the source of the fourth transistor; a second test point is provided between the drain of the eighth transistor and the source of the ninth transistor; The driving method includes the following steps: S1. In the initialization stage, turn on the seventh transistor to initialize the first electrolytic capacitor and reach a first target voltage; S2. In the data input stage, turn off the seventh transistor and turn on the first transistor, the third transistor, and the fourth transistor to make the first test point reach the second target voltage; S3. In the light-emitting voltage initialization stage, turn off the first transistor, the third transistor, and the fourth transistor, and turn on the second transistor to make the second electrolytic capacitor reach the third target voltage; S4. In the light-emitting stage, turn off the second transistor, and turn on the tenth transistor and the eleventh transistor to input a comparison voltage to the first end of the first electrolytic capacitor and gradually raise the voltage of the first test point. Then turn on the fourth transistor and the eighth transistor, and ensure that the fifth transistor is turned off to keep the voltage of the second test point at the fourth target voltage.

[0012] Furthermore, it also includes controlling the power consumption of the first inverter and the second inverter based on the following formula: ; where is the power consumption of the corresponding inverter, is the voltage across the corresponding inverter, is the leakage current of the corresponding inverter, is the load capacitance at the output end of the corresponding inverter, is the operating frequency of the corresponding inverter.

[0013] Furthermore, the eighth transistor is an n-type thin-film transistor, and the ninth transistor is a p-type thin-film transistor; The driving method also includes controlling the level conversion time of the first inverter based on the following formula: ; ; where is the time required for the first inverter to convert from a low level to a high level, is the capacitance of the gate oxide layer in the ninth transistor, is the device mobility of the ninth transistor, is the device width of the ninth transistor, is the device length of the ninth transistor, is the high-level voltage across the first inverter, is the low-level voltage across the first inverter, is the preset threshold voltage of the ninth transistor, is the output voltage of the first inverter; The time required for the first inverter to transition from a high level to a low level The capacitance of the gate oxide layer in the eighth transistor The device mobility of the eighth transistor The device width of the eighth transistor The device length of the eighth transistor The preset threshold voltage of the eighth transistor

[0014] Further, the third transistor is an n-type thin film transistor, and the sixth transistor is a p-type thin film transistor The driving method further includes controlling the level conversion time of the second inverter based on the following formula ; ; Wherein The time required for the second inverter to transition from a low level to a high level The capacitance of the gate oxide layer in the sixth transistor The device mobility of the sixth transistor The device width of the sixth transistor The device length of the sixth transistor The high-level voltage across the second inverter The low-level voltage across the second inverter The preset threshold voltage of the sixth transistor The output voltage of the second inverter The time required for the second inverter to transition from a high level to a low level The capacitance of the gate oxide layer in the third transistor The device mobility of the third transistor The device width of the third transistor The device length of the third transistor The preset threshold voltage of the third transistor

[0015] Further, it further includes controlling the capacitance of the gate oxide layers in the ninth transistor, the eighth transistor, the sixth transistor, and the third transistor through the following formula ; ; ; ; Wherein is the capacitance of the gate oxide layer in the ninth transistor, is the relative permittivity of silicon dioxide, is the permittivity of vacuum, is the unit area of the gate oxide layer in the ninth transistor, is the accumulated thickness of the gate oxide layer in the ninth transistor, is the capacitance of the gate oxide layer in the eighth transistor, is the unit area of the gate oxide layer in the eighth transistor, is the accumulated thickness of the gate oxide layer in the eighth transistor, is the capacitance of the gate oxide layer in the sixth transistor, is the unit area of the gate oxide layer in the sixth transistor, is the accumulated thickness of the gate oxide layer in the sixth transistor, is the capacitance of the gate oxide layer in the third transistor, is the unit area of the gate oxide layer in the third transistor, is the accumulated thickness of the gate oxide layer in the third transistor.

[0016] In a third aspect, the present invention provides a display device including the above-mentioned pixel circuit.

[0017] As can be seen from the above, the inverter in the pixel circuit provided by the present invention can be used as both a level holder and a level converter to turn on or off the light-emitting module, improving the utilization rate between components, reducing the space occupation caused by a large number of devices in the multi-functional pixel circuit, and thus being beneficial to miniaturization; in addition, the inverter as a level holding and conversion module can reduce the circuit power consumption, improve the level conversion speed, and further enhance the driving ability of the pixel circuit, realizing the driving of a high-resolution and high-refresh-rate display panel, and being able to reduce the voltage and current rise and fall times to within microseconds.

[0018] Other features and advantages of the present invention will be described in the subsequent specification, and some of them will become obvious from the specification or be understood by implementing the embodiments of the present invention. The objectives and other advantages of the present invention can be achieved and obtained by the structures specifically pointed out in the written specification and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is the circuit diagram of the first pixel circuit provided by the embodiment of the present invention.

[0020] Figure 2 is the circuit diagram of the second pixel circuit provided by the embodiment of the present invention.

[0021] Figure 3 is a flowchart of a driving method provided by the embodiment of the present invention.

[0022] Description of reference numerals: 100. First inverter; 200. Second inverter; 300. Quasi-inverter; T1. First transistor; T2. Second transistor; T3. Third transistor; T4. Fourth transistor; T5. Fifth transistor; T6. Sixth transistor; T7. Seventh transistor; T8. Eighth transistor; T9. Ninth transistor; T10. Tenth transistor; T11. Eleventh transistor; T12. Twelfth transistor; T13. Thirteenth transistor; T14. Fourteenth transistor; T15. Fifteenth transistor; T16. Sixteenth transistor; T17. Seventeenth transistor; T18. Eighteenth transistor; T19. Nineteenth transistor; T20. Twentieth transistor; C1. First electrolytic capacitor; C2. Second electrolytic capacitor; C3. Third electrolytic capacitor; C4. Fourth electrolytic capacitor; C5. Fifth electrolytic capacitor; D1. First diode; D2. Second diode. Detailed implementation manners

[0023] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. The components of the embodiments of the present invention described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the present invention to be protected, but only represents the selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0024] It should be noted that similar reference numerals and letters indicate similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used for differential description and cannot be understood as indicating or implying relative importance.

[0025] Referring to Figure 1 and Figure 2 , the present invention provides a pixel circuit, including an eighth transistor T8 and a ninth transistor T9. The eighth transistor T8 is a thin film transistor based on low-temperature polysilicon, and the ninth transistor T9 is a thin film transistor based on oxide. The eighth transistor T8 and the ninth transistor T9 form a first inverter 100 based on a low-temperature polycrystalline oxide structure; Alternatively, it includes a nineteenth transistor T19 and a twentieth transistor T20. The source of the nineteenth transistor T19 is connected to the source of the twentieth transistor T20, and both the nineteenth transistor T19 and the twentieth transistor T20 are oxide-based thin film transistors. The nineteenth transistor T19 and the twentieth transistor T20 form a pseudo-inverter 300 based on an oxide structure (realizing a function similar to an inverter by using a source follower structure and the device characteristics of thin film transistors).

[0026] This embodiment provides two pixel circuit solutions. In the first solution, the eighth transistor adopts low-temperature polysilicon technology, and the ninth transistor adopts oxide technology. The eighth transistor and the ninth transistor are connected to form a first inverter, forming a low-temperature polycrystalline oxide structure. Low-temperature polysilicon thin film transistors have high carrier mobility, and oxide thin film transistors have low leakage current and good uniformity. Thus, combining high-mobility low-temperature polysilicon transistors and low-leakage-current oxide transistors to form an inverter takes advantage of the merits of both technologies, improving the switching speed of the inverter and reducing the static power consumption. In the second solution, both the nineteenth transistor and the twentieth transistor adopt oxide technology. The source of the nineteenth transistor is connected to the source of the twentieth transistor, and the nineteenth transistor and the twentieth transistor form a pseudo-inverter based on oxide technology. Adopting a single oxide technology simplifies the manufacturing process and reduces the production complexity.

[0027] Specifically, to solve the technical problems of long voltage and current fall times and complex circuit structures in existing pixel circuits, this pixel circuit is solved by introducing a first inverter based on a low-temperature polycrystalline oxide structure or a pseudo-inverter based on an oxide structure. The first solution is based on a low-temperature polycrystalline oxide circuit structure. Among them, the eighth transistor (low-temperature polysilicon) and the ninth transistor (oxide) form a first inverter. The high carrier mobility characteristic of the low-temperature polysilicon transistor enables the inverter to achieve fast level conversion, reducing the rise and fall times of voltage and current. The low leakage current characteristic of the oxide transistor helps reduce the static power consumption of the inverter. Thus, this first inverter serves as a level holding or level conversion module in the pixel circuit, improving the level conversion speed, thereby enhancing the driving ability of the pixel circuit and contributing to realizing high-resolution and high-refresh-rate displays. The second solution is based on a pure oxide circuit structure. Among them, both the nineteenth transistor and the twentieth transistor are oxide transistors, and their sources are connected to form a pseudo-inverter. This structure realizes an inversion function on an all-oxide process platform, simplifying the manufacturing process. This pseudo-inverter also plays a role in fast level conversion, capable of reducing the rise and fall times of voltage and current to within microseconds. Inverters of both structures can serve as level holding and conversion modules, improving the utilization rate among components and reducing the space occupation caused by a large number of devices.

[0028] In some specific embodiments, the pixel circuit includes an eighth transistor and a ninth transistor to form a first inverter. For example, the eighth transistor is an n-type thin film transistor based on low-temperature polysilicon, and the ninth transistor is a p-type thin film transistor based on oxide. The gates of the eighth transistor and the ninth transistor are connected as the input terminal of the first inverter. The drain of the eighth transistor is connected to the source of the ninth transistor as the output terminal of the first inverter. The source of the eighth transistor is connected to a low potential (such as ground), and the source of the ninth transistor is connected to a high potential (such as the power supply voltage). Thus, when the input terminal is at a high level, the eighth transistor is turned on, the ninth transistor is turned off, and the output terminal is pulled down to the low potential; when the input terminal is at a low level, the eighth transistor is turned off, the ninth transistor is turned on, and the output terminal is pulled up to the high potential, realizing the inverter function. This structure utilizes the high mobility of low-temperature polysilicon transistors to achieve fast switching and the low leakage current of oxide transistors to reduce power consumption, thereby improving the performance of the inverter.

[0029] In certain embodiments, referring to Figure 1 and Figure 2 , when the pixel circuit includes a first inverter 100 formed by an eighth transistor T8 and a ninth transistor T9, the pixel circuit further includes a third transistor T3 and a sixth transistor T6. The third transistor T3 is a thin film transistor based on oxide, and the sixth transistor T6 is a thin film transistor based on low-temperature polysilicon. The third transistor T3 and the sixth transistor T6 form a second inverter 200 based on a low-temperature polycrystalline oxide structure. The first inverter 100 and the second inverter 200 are cascaded to form a two-stage inverter structure for significantly reducing the switching time.

[0030] The pixel circuit includes a first inverter formed by an eighth transistor and a ninth transistor. Further, the pixel circuit adds a third transistor and a sixth transistor. The third transistor is a thin film transistor based on oxide, and the sixth transistor is a thin film transistor based on low-temperature polysilicon. Thus, the third transistor and the sixth transistor form a second inverter based on a low-temperature polycrystalline oxide structure. The output terminal of the first inverter is connected to the input terminal of the second inverter to form a two-stage inverter structure. This cascaded configuration improves the conversion rate of the signal.

[0031] Specifically, when the pixel circuit includes a first inverter composed of an eighth transistor and a ninth transistor, the switching time of the first inverter may be relatively long, affecting high-resolution and high-refresh-rate displays. By adding a second inverter composed of a third transistor and a sixth transistor and cascading the first inverter and the second inverter, a two-stage inverter structure is constructed. The first inverter receives an input signal and generates an intermediate output signal, which serves as the input of the second inverter. The second inverter further inverts and amplifies the intermediate signal to generate a final output signal. The eighth transistor and the sixth transistor adopt low-temperature polysilicon technology, which has a high carrier mobility, facilitating the improvement of circuit speed. The ninth transistor and the third transistor adopt oxide technology, providing good uniformity and low leakage current. Combining transistors of these two different technologies to form an inverter and cascading them optimizes the performance of the inverter, making the transition of the signal from high level to low level or from low level to high level faster and significantly reducing the switching time of the entire inverter structure. Thereby, the rise and fall times of voltage and current are shortened, meeting the requirements of high-resolution and high-refresh-rate displays.

[0032] In some specific embodiments, the second inverter is composed of a third transistor and a sixth transistor. The third transistor is an oxide-based n-type thin-film transistor, and the sixth transistor is a low-temperature polysilicon-based p-type thin-film transistor. The gate of the third transistor is connected to the gate of the sixth transistor as the input terminal of the second inverter. The drain of the third transistor is connected to the drain of the sixth transistor (indirectly connected through a tenth transistor) as the output terminal of the second inverter. The output terminal of the first inverter is connected to the input terminal of the second inverter. When the input signal undergoes a level conversion at the first inverter, its output signal drives the second inverter, and the second inverter further accelerates the level conversion process, thereby achieving a reduction in switching time and reducing the rise and fall times of voltage and current to within microseconds.

[0033] In certain embodiments, referring to FIGS. Figure 1 and FIGS. Figure 2 , the pixel circuit further includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a seventh transistor T7, a tenth transistor T10, an eleventh transistor T11, a first electrolytic capacitor C1, a second electrolytic capacitor C2, and a first diode D1; Among them, the drain of the first transistor T1 is simultaneously connected to the drain of the second transistor T2, the source of the third transistor T3, and the first end of the second electrolytic capacitor C2. The gate of the first transistor T1 is connected to the gate of the fourth transistor T4; the second end of the second electrolytic capacitor C2 is simultaneously connected to the source of the eighth transistor T8 and the cathode of the first diode D1 and grounded; the drain of the eleventh transistor T11 is connected to the first end of the first electrolytic capacitor C1. The second end of the first electrolytic capacitor C1 is connected to the source of the fourth transistor T4. The drain of the fourth transistor T4 is simultaneously connected to the drain of the third transistor T3 and the source of the tenth transistor T10. The gate of the tenth transistor T10 is simultaneously connected to the gate of the eleventh transistor T11 and the drain of the ninth transistor T9. The drain of the tenth transistor T10 is simultaneously connected to the drain of the sixth transistor T6, the gate of the eighth transistor T8, and the gate of the ninth transistor T9. The gate of the sixth transistor T6 is simultaneously connected to the gate of the third transistor T3, the source of the seventh transistor T7, the second end of the first electrolytic capacitor C1, and the source of the fourth transistor T4; the drain of the eighth transistor T8 is simultaneously connected to the source of the ninth transistor T9 and the gate of the fifth transistor T5; the source of the fifth transistor T5 is connected to the anode of the first diode D1.

[0034] This solution proposes a circuit structure for a low-temperature polycrystalline oxide pixel circuit. Based on a two-stage inverter, this pixel circuit structure adds multiple transistors, capacitors, and diodes to construct a complete pixel driving unit. The gate of the fifth transistor T5 is connected to the output terminal of the first inverter (the drain of the eighth transistor T8 and the source of the ninth transistor T9). The fifth transistor T5 serves as the driving transistor of the pixel, and its conduction state and current are controlled by the output voltage of the first inverter, thereby realizing the regulation of the current of the light-emitting device. The first electrolytic capacitor C1 and the second electrolytic capacitor C2 serve as storage elements for storing data voltage or control voltage, thus realizing the voltage holding function. One end of the first electrolytic capacitor C1 is connected to the drain of the eleventh transistor T11, and the other end is connected to the source of the fourth transistor T4, the gate of the sixth transistor T6, and the source of the seventh transistor T7, indicating that the voltage stored in the first electrolytic capacitor C1 is related to data input, control signals, and the gate voltage of the driving fifth transistor T5, and is used to store driving voltage or compensation voltage. One end of the second electrolytic capacitor C2 is connected to the drain of the first transistor T1, the drain of the second transistor T2, and the source of the third transistor T3, and the other end is grounded, indicating that the voltage stored in the second electrolytic capacitor C2 is related to data input, light-emitting initialization, and the source voltage of the driving transistor T5, and is used to store the light-emitting initialization voltage. The first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the tenth transistor T10, and the eleventh transistor T11 serve as switching transistors. By controlling their gate signals, the connection and disconnection between different nodes in the circuit are controlled, thereby realizing the functions of different stages such as data input, voltage storage, threshold voltage compensation, light-emitting initialization, and light emission. For example, the gates of the first transistor T1 and the fourth transistor T4 are connected to control the data input path simultaneously. The gates of the tenth transistor T10 and the eleventh transistor T11 are connected to the drain of the ninth transistor T9 (the input terminal of the first inverter), indicating that their switching states are controlled by the input signal of the first inverter and are used to control the transmission of signals. The first diode D1 is connected between the source of the fifth transistor T5 and the ground, and is used to provide a reference voltage or a protection function. Through the specific connection of these transistors and capacitors, combined with the two-stage inverter, the entire circuit structure can accurately control the gate voltage or source voltage of the driving transistor T5, thereby stabilizing the driving current, realizing accurate light emission of the pixel, and including a threshold voltage compensation mechanism to solve the problems of unstable driving or the need for additional complex circuits in the prior art, thereby improving the current stability in the light-emitting stage.

[0035] In some specific embodiments, the pixel circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a seventh transistor T7, a tenth transistor T10, and an eleventh transistor T11. These transistors can be oxide-based thin film transistors. The first electrolytic capacitor C1 and the second electrolytic capacitor C2 can be electrolytic capacitors with a capacitance value ranging from 1 picofarad to 10 picofarads. The first diode D1 can be a Schottky diode. The drain of the first transistor T1 is connected to a first node, and the first node is simultaneously connected to the drain of the second transistor T2, the source of the third transistor T3, and the first end of the second electrolytic capacitor C2. The gate of the first transistor T1 is connected to a second node, and the second node is simultaneously connected to the gate of the fourth transistor T4. The second end of the second electrolytic capacitor C2 is connected to a third node, and the third node is simultaneously connected to the source of the eighth transistor T8 and the negative electrode of the first diode D1, and the third node is grounded. The drain of the eleventh transistor T11 is connected to the first end of the first electrolytic capacitor C1. The second end of the first electrolytic capacitor C1 is connected to a fourth node, and the fourth node is simultaneously connected to the source of the fourth transistor T4, the gate of the sixth transistor T6, and the source of the seventh transistor T7. The drain of the fourth transistor T4 is connected to a fifth node, and the fifth node is simultaneously connected to the drain of the third transistor T3 and the source of the tenth transistor T10. The gate of the tenth transistor T10 is connected to a sixth node, and the sixth node is simultaneously connected to the gate of the eleventh transistor T11 and the drain of the ninth transistor T9. The drain of the tenth transistor T10 is connected to a seventh node, and the seventh node is simultaneously connected to the drain of the sixth transistor T6, the gate of the eighth transistor T8, and the gate of the ninth transistor T9. The drain of the eighth transistor T8 is connected to an eighth node, and the eighth node is simultaneously connected to the source of the ninth transistor T9 and the gate of the fifth transistor T5. The source of the fifth transistor T5 is connected to the positive electrode of the first diode D1. The drain of the seventh transistor T7 is connected to an initialization voltage source. The source of the second transistor T2 is connected to a light-emitting initialization voltage source. The source of the first transistor T1 is connected to a data input line. The source of the eleventh transistor T11 is connected to a comparison voltage source. The drain of the fifth transistor T5 is connected to the anode of the light-emitting device. The source of the sixth transistor T6 is connected to a high-level power supply. The gate of the third transistor T3 is connected to the fourth node. Thus, by controlling the voltage signals of the second node, the fourth node, the gate of the second transistor T2, the gate of the seventh transistor T7, and the sixth node, functions such as data input, voltage storage, threshold voltage compensation, light-emitting initialization, and light emission of the pixel circuit can be realized, ensuring the stability of the driving current.

[0036] In practical applications, the circuit structure is divided into two parts, including a PWM input module and an output module (although it exists in the figure but is not clearly divided. It can be simply demarcated by the first inverter. The input side belongs to the PWM input module, the output side belongs to the output module, the first inverter belongs to the PWM input module, and the first inverter and the output module form a cascaded circuit to improve the level conversion time). The PWM input module is used to store the input signal and convert the input signal into a PWM signal, while the output module is a control output circuit responsible for the stable output of the current signal and the opening or closing of the circuit to ensure stable grayscale display. The first inverter can both hold the level and turn on or off the light-emitting module as a level converter, improving the utilization rate between components, reducing the space occupied by the multi-functional pixel circuit due to numerous devices, and being beneficial for miniaturization. As a level-holding and conversion module, the first inverter can reduce the circuit power consumption, improve the level conversion speed, thereby enhancing the driving ability of the pixel circuit and realizing the driving of a high-resolution and high-refresh-rate display panel. The digital PWM pixel circuit proposed by the present invention has the advantages of high output current stability, low power consumption, and high refresh rate. This circuit not only has the threshold voltage compensation and luminous duration-grayscale matching functions of the traditional PWM pixel circuit but also has a constant current driving and fast level conversion function. In terms of the ability to drive Micro LED, the proposed pixel circuit can also achieve the function of frame-by-frame display, which can not only reduce the screen flicker but also be beneficial for the synchronization of the tiled display screen.

[0037] In some embodiments, referring to the attached Figure 1 and the attached Figure 2 , when the pixel circuit includes an inverter-like structure composed of the nineteenth transistor T19 and the twentieth transistor T20, the pixel circuit further includes the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, the third electrolytic capacitor C3, the fourth electrolytic capacitor C4, the fifth electrolytic capacitor C5, and the second diode D2; Among them, the gate of the twelfth transistor T12 is connected to the gate of the fifteenth transistor T15. The drain of the twelfth transistor T12 is simultaneously connected to the drains of the fourteenth transistor T14 and the thirteenth transistor T13. The gate of the thirteenth transistor T13 is connected to the first end of the fifth electrolytic capacitor C5. The second end of the fifth electrolytic capacitor C5 is simultaneously connected to the source of the fourteenth transistor T14, the drain of the fifteenth transistor T15, the drain of the seventeenth transistor T17, the gate of the nineteenth transistor T19, and the drain of the twentieth transistor T20. The gate of the fourteenth transistor T14 is connected to the second end of the third electrolytic capacitor C3, the drain of the eighteenth transistor T18, and the source of the fifteenth transistor T15. The source of the nineteenth transistor T19 is simultaneously connected to the source of the twentieth transistor T20, the first end of the fourth electrolytic capacitor C4, and the gate of the sixteenth transistor T16. The gate of the twentieth transistor T20 is simultaneously connected to the second end of the fourth electrolytic capacitor C4 and the negative electrode of the second diode D2 and is grounded. The positive electrode of the second diode D2 is connected to the source of the sixteenth transistor T16.

[0038] The pixel circuit includes a pseudo-inverter formed by the nineteenth transistor and the twentieth transistor, and a plurality of additional transistors, capacitors, and diodes are added to jointly form a complete pixel driving unit. The sources of the nineteenth transistor and the twentieth transistor are connected together. The gate of the twentieth transistor is grounded. The fourth electrolytic capacitor is connected between the source node of the nineteenth transistor and the twentieth transistor and the ground. The drain of the twentieth transistor is connected to the gate of the nineteenth transistor, forming a feedback structure. This node is also connected to the second end of the fifth electrolytic capacitor, as well as the source of the fourteenth transistor, the drain of the fifteenth transistor, and the drain of the seventeenth transistor. The fifth electrolytic capacitor is connected between the gate of the thirteenth transistor and this node for signal coupling or voltage storage. Transistors T12 - T18, capacitors C3, C4, C5, and diode D2 jointly implement the various functions of the pixel circuit through specific connection methods. Capacitors are used to store voltage to control or compensate the emission brightness of the pixel. Transistors act as switches, conducting or cutting off according to control signals, and are used for data input, voltage holding, and driving signal transmission. The gates of the twelfth transistor and the fifteenth transistor are connected and controlled by the same signal. The drains of the twelfth transistor, the thirteenth transistor, and the fourteenth transistor are connected together. The gate of the fourteenth transistor is connected to the third electrolytic capacitor, the drain of the eighteenth transistor, and the source of the fifteenth transistor. The gate of the sixteenth transistor is connected to the source node of the nineteenth transistor and the twentieth transistor, and its source is connected to the positive electrode of the second diode, and the negative electrode of the second diode is grounded. These connection relationships construct the control logic and signal paths, enabling the pixel circuit to receive external signals, process and store voltage, and ultimately drive the pixel to emit light.

[0039] Specifically, aiming at the problems in the prior art that the voltage and current decay times are long when the light-emitting device is turned off in the analog driving circuit, which is not conducive to high-resolution and high-refresh-rate displays, and that implementing the PWM and regulated voltage output circuits requires adding extra transistors, resulting in a complex circuit, this solution proposes a circuit structure for a pure-oxide pixel circuit. Based on the pseudo-inverter formed by the nineteenth transistor and the twentieth transistor, this structure adds the twelfth transistor to the eighteenth transistor, the third electrolytic capacitor to the fifth electrolytic capacitor, and the second diode. The nineteenth transistor and the twentieth transistor form a pseudo-inverter. Their sources are connected, and both are oxide-based thin-film transistors, forming a pseudo-inverter based on an oxide structure. This pseudo-inverter structure can serve as a level-holding and conversion module, reducing circuit power consumption and increasing the level-conversion speed. By adding other transistors, capacitors, and diodes and connecting them in a specific way, this pixel circuit can achieve a complete pixel driving function. For example, capacitors C3, C4, and C5 are used to store voltages or couple signals to control or compensate the luminous brightness of the pixel. Transistors T12 - T18 act as switches, conducting or cutting off according to external control signals, and are used to manage operation stages such as data input, voltage holding, and driving signal transmission. The gates of the twelfth transistor and the fifteenth transistor are connected, and their switching states can be controlled by the same control signal. The gate of the fourteenth transistor is connected to the third electrolytic capacitor, the drain of the eighteenth transistor, and the source of the fifteenth transistor, indicating signal interaction or control relationships between these components. The gate of the sixteenth transistor is connected to the source nodes of the nineteenth transistor and the twentieth transistor, and its source is connected to ground through the second diode, which may be used to control or stabilize the voltage of this node. Through the collaborative work of these components, the pixel circuit can receive external data signals, convert them into current or voltage signals for driving the pixel to emit light, and achieve voltage storage, signal coupling, and manage different operation stages by controlling the switching states of the transistors. This structure can achieve more complex and complete driving functions than a single pseudo-inverter, such as voltage storage, signal coupling, and managing different operation stages by controlling the switching states of the transistors, thus solving the problem that a single pseudo-inverter is insufficient to form a complete high-performance pixel circuit. Different from the first circuit, the second circuit uses a pure-oxide circuit structure but is also divided into two parts, including a PWM input module and an output module (although present in the figure but not clearly divided. It can be simply demarcated by the pseudo-inverter. The input side belongs to the PWM input module, the output side belongs to the output module, and the pseudo-inverter belongs to the PWM input module. The pseudo-inverter and the output module form a cascaded circuit to improve the level-conversion time). The PWM input module is used to store the input signal and convert the input signal into a PWM signal, while the output module is a control output circuit responsible for stable output of the current signal and turning the circuit on or off to ensure stable grayscale display.The class inverter can be used as both a level holding and a level conversion to turn on or off the light-emitting module, improving the utilization rate between components, reducing the space occupied by the multi-functional pixel circuit due to a large number of devices, and facilitating miniaturization. As a level holding and conversion module, the class inverter can reduce circuit power consumption and improve the level conversion speed, thereby enhancing the driving ability of the pixel circuit and realizing the driving of a high-resolution and high-refresh-rate display panel. The digital PWM pixel circuit proposed in the present invention has advantages such as high output current stability, low power consumption, and high refresh rate. This circuit not only includes the threshold voltage compensation and luminous duration-gray scale matching functions of the traditional PWM pixel circuit but also has a constant current driving and fast level conversion function. In terms of the ability to drive Micro LEDs, the proposed pixel circuit can also achieve the function of frame-by-frame display, which can not only reduce screen flicker but also facilitate the synchronization of the tiled display screen.

[0040] In some specific embodiments, the pixel circuit can be integrated on the substrate of the display panel. All transistors T12 - T20 are fabricated using oxide-based thin-film transistor technology. For example, IGZO (indium gallium zinc oxide) can be used as the channel material. Capacitors C3, C4, C5 can be metal-insulator-metal MIM structures or MOS structures based on the gate oxide layer of thin-film transistors. The second diode D2 can be a Schottky diode or a PN junction diode. In a pixel unit, these components are arranged according to the connection relationships described in this embodiment. For example, the sources of the nineteenth transistor T19 and the twentieth transistor T20 are connected to a common node, and one end of the fourth electrolytic capacitor C4 is also connected to this node, with the other end grounded. The drain of the twentieth transistor T20 is connected to the gate of the nineteenth transistor T19 to form a feedback. This node is simultaneously connected to the second end of the fifth electrolytic capacitor C5, the source of the fourteenth transistor, the drain of the fifteenth transistor, and the drain of the seventeenth transistor. The gate of the thirteenth transistor T13 is connected to the first end of the fifth electrolytic capacitor C5. The gates of the twelfth transistor T12 and the fifteenth transistor T15 are connected together and are driven by a control line. The gate of the fourteenth transistor T14 is connected to the third electrolytic capacitor C3, the drain of the eighteenth transistor T18, and the source of the fifteenth transistor T15. The gate of the sixteenth transistor T16 is connected to the source node of the nineteenth and twentieth transistors, and its source is connected to the positive electrode of the second diode D2, with the negative electrode of the second diode D2 grounded. These components are connected on the substrate through metal interconnects. For example, complex connections can be achieved through multi-layer metal wiring. The pixel circuit can receive signals from data lines, scan lines, and control lines, and through the switching of transistors and the charging and discharging of capacitors, it can achieve the storage of data voltage, the conversion of signals, and the output of driving current, thereby controlling the emission brightness of the Micro LED or other light-emitting devices connected to the pixel circuit. This pure oxide TFT structure is beneficial for manufacturing on large-sized substrates, reducing costs. At the same time, the oxide TFT has a low leakage current, which is beneficial for voltage retention and power consumption reduction.

[0041] Reference attached Figure 3, the present invention provides a driving method, which is applied to a pixel circuit. The pixel circuit includes an eighth transistor T8 and a ninth transistor T9. The eighth transistor T8 is a thin film transistor based on low-temperature polysilicon, and the ninth transistor T9 is a thin film transistor based on oxide; the eighth transistor T8 and the ninth transistor T9 form a first inverter 100 based on a low-temperature polycrystalline oxide structure; the pixel circuit further includes a third transistor T3 and a sixth transistor T6. The third transistor T3 is a thin film transistor based on oxide, and the sixth transistor T6 is a thin film transistor based on low-temperature polysilicon; the third transistor T3 and the sixth transistor T6 form a second inverter 200 based on a low-temperature polycrystalline oxide structure; the first inverter 100 and the second inverter 200 are cascaded to form a two-stage inverter structure; the pixel circuit further includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a seventh transistor T7, a tenth transistor T10, an eleventh transistor T11, a first electrolytic capacitor C1, a second electrolytic capacitor C2, and a first diode D1; A first test point A is provided between the second terminal of the first electrolytic capacitor C1 and the source of the fourth transistor T4; a second test point B is provided between the drain of the eighth transistor T8 and the source of the ninth transistor T9; The driving method includes the following steps: S1. In the initialization stage, turn on the seventh transistor to initialize the first electrolytic capacitor and make it reach a first target voltage; S2. In the data input stage, turn off the seventh transistor, and turn on the first transistor, the third transistor, and the fourth transistor to make the first test point reach a second target voltage, for compensating the threshold voltage of the third transistor and inputting a data voltage at the same time; S3. In the light-emitting voltage initialization stage, turn off the first transistor, the third transistor, and the fourth transistor, and turn on the second transistor to make the second electrolytic capacitor reach a third target voltage, for turning off the fifth transistor at the end of light emission; S4. In the light-emitting stage, turn off the second transistor, and turn on the tenth transistor and the eleventh transistor to input a comparison voltage to the first terminal of the first electrolytic capacitor and gradually raise the voltage of the first test point, then turn on the fourth transistor and the eighth transistor, and ensure that the fifth transistor is turned off to keep the voltage of the second test point at a fourth target voltage, for ensuring the current stability of the driving transistor in the light-emitting stage and preventing screen flicker.

[0042] In the initialization stage S1, by turning on the seventh transistor, a preset initialization voltage is applied to the first electrolytic capacitor C1 to charge or discharge it to the first target voltage, establishing a reference state for subsequent operations. In the data input stage S2, the seventh transistor is turned off, and at the same time, the first transistor, the third transistor, and the fourth transistor are turned on. The first transistor receives the input data voltage. The source of the third transistor is connected to the drain of the first transistor, and the drain is connected to the drain of the fourth transistor and the source of the tenth transistor. The source of the fourth transistor is connected to the first test point A and the second terminal of the first electrolytic capacitor C1, and the gate is connected to the gate of the first transistor. This connection method makes the voltage formed at the first test point A include the input data voltage and the compensation for the threshold voltage of the third transistor, ensuring the accurate transmission of the data voltage. In the light-emitting voltage initialization stage S3, the transistors related to data input (the first, third, and fourth transistors) are turned off, and the second transistor is turned on. The drain of the second transistor is connected to the drain of the first transistor, the source of the third transistor, and the first terminal of the second electrolytic capacitor C2. The second terminal of the second electrolytic capacitor C2 is grounded. Turning on the second transistor charges the second electrolytic capacitor C2 to the third target voltage, and this voltage state is used to control the turn-off of the fifth transistor at the end of light emission. In the light-emitting stage S4, first, the second transistor is turned off. The tenth transistor and the eleventh transistor are turned on, and a comparison voltage is input to the first terminal of the first electrolytic capacitor C1. The voltage change of the first electrolytic capacitor C1 affects the voltage at the first test point A. Subsequently, the fourth transistor and the eighth transistor are turned on, and it is ensured that the fifth transistor is turned off. The source of the eighth transistor is connected to the second terminal of the second electrolytic capacitor C2 (grounded), and the drain is connected to the source of the ninth transistor and the gate of the fifth transistor (the second test point B). By controlling the states of the fourth transistor and the eighth transistor, the voltage at the second test point B is stabilized at the fourth target voltage. The voltage at the second test point B directly controls the gate of the fifth transistor, thereby stabilizing the conduction current of the fifth transistor.

[0043] Specifically, the driving method realizes the initialization, data input, light-emitting voltage initialization and light-emitting process of the pixel by time-sharing control of the switching state of each transistor in the pixel circuit. In the initialization stage, the seventh transistor is turned on, and the first electrolytic capacitor C1 is initialized by a preset voltage. In the data input stage, the first, third, and fourth transistors are turned on, and the data voltage is input. At the same time, the circuit structure is used to compensate the threshold voltage of the third transistor at the first test point A to ensure the accuracy of the input voltage. In the light-emitting voltage initialization stage, the second transistor is turned on, and the second electrolytic capacitor C2 is charged to a specific voltage, which is used to subsequently turn off the fifth transistor. In the light-emitting stage, the comparison voltage is input by turning on the tenth and eleventh transistors, and then turning on the fourth and eighth transistors, while ensuring that the fifth transistor is turned off, and the voltage of the second test point B is stabilized at the fourth target voltage. The second test point B is connected to the gate of the fifth transistor, and the voltage at this point is stabilized to directly control the on-current of the fifth transistor, thereby ensuring the brightness of the light-emitting device (first diode D1) is stable and preventing the screen from flickering. Although the first inverter and the second inverter are not directly mentioned in the switching control in these steps, as part of the pixel circuit, their fast response characteristics help to quickly establish and transmit the signal, indirectly supporting the timing requirements of the driving method.

[0044] In some specific embodiments, in the initialization stage S1, the seventh transistor can be turned on by applying a high-level pulse to its gate, and a preset initialization voltage is connected to the source or drain of the seventh transistor, and this voltage is transmitted to the first electrolytic capacitor C1 through the seventh transistor. The data input stage S2 can be achieved by applying data input signals and corresponding control signals to the gates of the first, third, and fourth transistors. For example, during the data input period, the gate of the first transistor receives a row strobe signal, and at the same time, the data line is connected to the source of the first transistor to input a data voltage. The gates of the third and fourth transistors also receive corresponding control signals to turn them on. In the light-emitting voltage initialization stage S3, the second transistor can be turned on by applying a control signal to its gate, and a preset voltage source is connected to the source or drain of the second transistor, and this voltage is transmitted to the second electrolytic capacitor C2 through the second transistor. In the light-emitting stage S4, the tenth and eleventh transistors can be turned on by applying control signals to their gates, and a comparison voltage is applied to the first end of the first electrolytic capacitor C1. Subsequently, control signals are applied to the gates of the fourth and eighth transistors to turn them on, and at the same time, a control signal is applied to the gate of the fifth transistor to turn it off. By precisely controlling the timing and voltage levels of these control signals, stable control of the voltage at the second test point B can be achieved, and thus the current output of the fifth transistor can be stabilized. For example, in the light-emitting stage, by adjusting the comparison voltage applied to the tenth and eleventh transistors and the conduction states of the fourth and eighth transistors, the voltage at the second test point B can be dynamically adjusted to maintain it near a predetermined fourth target voltage, thereby compensating for factors that may affect the current of the fifth transistor, such as voltage fluctuations or device characteristic changes.

[0045] In some embodiments, it further includes controlling the power consumption of the first inverter and the second inverter based on the following formula: ; Wherein, is the power consumption of the corresponding inverter, is the voltage across the corresponding inverter, is the leakage current of the corresponding inverter, is the load capacitance at the output end of the corresponding inverter, is the operating frequency of the corresponding inverter.

[0046] In some embodiments, the eighth transistor is an n-type thin-film transistor, and the ninth transistor is a p-type thin-film transistor; The driving method further includes controlling the level conversion time of the first inverter based on the following formula: ; ; Wherein, The time required for the first inverter to transition from a low level to a high level, is the capacitance of the gate oxide layer in the ninth transistor, is the device mobility of the ninth transistor, is the device width of the ninth transistor, is the device length of the ninth transistor, is the high-level voltage across the first inverter, is the low-level voltage across the first inverter, is the preset threshold voltage of the ninth transistor, is the output voltage of the first inverter; is the time required for the first inverter to transition from a high level to a low level, is the capacitance of the gate oxide layer in the eighth transistor, is the device mobility of the eighth transistor, is the device width of the eighth transistor, is the device length of the eighth transistor, is the preset threshold voltage of the eighth transistor.

[0047] In some embodiments, the third transistor is an n-type thin-film transistor and the sixth transistor is a p-type thin-film transistor; The driving method further includes controlling the level transition time of the second inverter based on the following formula: ; ; where, is the time required for the second inverter to transition from a low level to a high level, is the capacitance of the gate oxide layer in the sixth transistor, is the device mobility of the sixth transistor, is the device width of the sixth transistor, is the device length of the sixth transistor, is the high-level voltage across the second inverter, is the low-level voltage across the second inverter, is the preset threshold voltage of the sixth transistor, is the output voltage of the second inverter; is the time required for the second inverter to transition from a high level to a low level, is the capacitance of the gate oxide layer in the third transistor, is the device mobility of the third transistor, is the device width of the third transistor, is the device length of the third transistor, is the preset threshold voltage of the third transistor.

[0048] In some embodiments, it further includes controlling the capacitances of the gate oxides of the ninth transistor T9, the eighth transistor T8, the sixth transistor T6, and the third transistor T3 through the following formula: ; ; ; ; wherein, is the capacitance of the gate oxide in the ninth transistor, is the relative permittivity of silicon dioxide, is the permittivity of vacuum, is the unit area of the gate oxide in the ninth transistor, is the accumulated thickness of the gate oxide in the ninth transistor, is the capacitance of the gate oxide in the eighth transistor, is the unit area of the gate oxide in the eighth transistor, is the accumulated thickness of the gate oxide in the eighth transistor, is the capacitance of the gate oxide in the sixth transistor, is the unit area of the gate oxide in the sixth transistor, is the accumulated thickness of the gate oxide in the sixth transistor, is the capacitance of the gate oxide in the third transistor, is the unit area of the gate oxide in the third transistor, is the accumulated thickness of the gate oxide in the third transistor.

[0049] The present invention provides a display device, including the pixel circuit in the above embodiments.

[0050] In this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0051] The above description is only for the embodiments of the present invention and is not used to limit the protection scope of the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A pixel circuit, characterized in that, It includes an eighth transistor T8 and a ninth transistor T9. The eighth transistor T8 is a thin-film transistor based on low-temperature polycrystalline silicon, and the ninth transistor T9 is a thin-film transistor based on oxide. The eighth transistor T8 and the ninth transistor T9 form a first inverter (100) based on a low-temperature polycrystalline oxide structure. Alternatively, it includes a nineteenth transistor T19 and a twentieth transistor T20. The source of the nineteenth transistor T19 is connected to the source of the twentieth transistor T20, and both the nineteenth transistor T19 and the twentieth transistor T20 are thin-film transistors based on oxide. The nineteenth transistor T19 and the twentieth transistor T20 form a pseudo-inverter (300) based on an oxide structure.

2. The pixel circuit according to claim 1, wherein When the pixel circuit includes the first inverter (100) formed by the eighth transistor T8 and the ninth transistor T9, the pixel circuit further includes a third transistor T3 and a sixth transistor T6. The third transistor T3 is a thin-film transistor based on oxide, and the sixth transistor T6 is a thin-film transistor based on low-temperature polycrystalline silicon. The third transistor T3 and the sixth transistor T6 form a second inverter (200) based on a low-temperature polycrystalline oxide structure. The first inverter (100) and the second inverter (200) are cascaded to form a two-stage inverter structure.

3. The pixel circuit according to claim 2, wherein The pixel circuit further includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a seventh transistor T7, a tenth transistor T10, an eleventh transistor T11, a first electrolytic capacitor C1, a second electrolytic capacitor C2, and a first diode D1. Among them, the drain of the first transistor T1 is simultaneously connected to the drain of the second transistor T2, the source of the third transistor T3, and the first end of the second electrolytic capacitor C2. The gate of the first transistor T1 is connected to the gate of the fourth transistor T4. The second end of the second electrolytic capacitor C2 is simultaneously connected to the source of the eighth transistor T8 and the negative electrode of the first diode D1 and grounded. The drain of the eleventh transistor T11 is connected to the first end of the first electrolytic capacitor C1. The second end of the first electrolytic capacitor C1 is connected to the source of the fourth transistor T4. The drain of the fourth transistor T4 is simultaneously connected to the drain of the third transistor T3 and the source of the tenth transistor T10. The gate of the tenth transistor T10 is simultaneously connected to the gate of the eleventh transistor T11 and the drain of the ninth transistor T9. The drain of the tenth transistor T10 is simultaneously connected to the drain of the sixth transistor T6, the gate of the eighth transistor T8, and the gate of the ninth transistor T9. The gate of the sixth transistor T6 is simultaneously connected to the gate of the third transistor T3, the source of the seventh transistor T7, the second end of the first electrolytic capacitor C1, and the source of the fourth transistor T4. The drain of the eighth transistor T8 is simultaneously connected to the source of the ninth transistor T9 and the gate of the fifth transistor T5. The source of the fifth transistor T5 is connected to the positive electrode of the first diode D1.

4. The pixel circuit according to claim 1, wherein When the pixel circuit includes a pseudo-inverter composed of a nineteenth transistor T19 and a twentieth transistor T20, the pixel circuit further includes a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, a twentieth transistor T20, a third electrolytic capacitor C3, a fourth electrolytic capacitor C4, a fifth electrolytic capacitor C5, and a second diode D2. Among them, the gate of the twelfth transistor T12 is connected to the gate of the fifteenth transistor T15, the drain of the twelfth transistor T12 is simultaneously connected to the drain of the fourteenth transistor T14 and the drain of the thirteenth transistor T13, the gate of the thirteenth transistor T13 is connected to the first end of the fifth electrolytic capacitor C5, and the second end of the fifth electrolytic capacitor C5 is simultaneously connected to the source of the fourteenth transistor T14, the drain of the fifteenth transistor T15, the drain of the seventeenth transistor T17, the gate of the nineteenth transistor T19, and the drain of the twentieth transistor T20; the gate of the fourteenth transistor T14 is connected to the second end of the third electrolytic capacitor C3, the drain of the eighteenth transistor T18, and the source of the fifteenth transistor T15; the source of the nineteenth transistor T19 is simultaneously connected to the source of the twentieth transistor T20, the first end of the fourth electrolytic capacitor C4, and the gate of the sixteenth transistor T16, the gate of the twentieth transistor T20 is simultaneously connected to the second end of the fourth electrolytic capacitor C4 and the negative electrode of the second diode D2 and grounded, and the positive electrode of the second diode D2 is connected to the source of the sixteenth transistor T16.

5. A driving method, applied to a pixel circuit, characterized in that The pixel circuit includes an eighth transistor T8 and a ninth transistor T9. The eighth transistor T8 is a thin film transistor based on low temperature polysilicon, and the ninth transistor T9 is a thin film transistor based on an oxide; the eighth transistor T8 and the ninth transistor T9 form a first inverter (100) based on a low temperature polycrystalline oxide structure; the pixel circuit further includes a third transistor T3 and a sixth transistor T6. The third transistor T3 is a thin film transistor based on an oxide, and the sixth transistor T6 is a thin film transistor based on low temperature polysilicon; the third transistor T3 and the sixth transistor T6 form a second inverter (200) based on a low temperature polycrystalline oxide structure; the first inverter (100) and the second inverter (200) are cascaded to form a two-stage inverter structure; the pixel circuit further includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a seventh transistor T7, a tenth transistor T10, an eleventh transistor T11, a first electrolytic capacitor C1, a second electrolytic capacitor C2, and a first diode D1; A first test point A is provided between the second end of the first electrolytic capacitor C1 and the source of the fourth transistor T4; A second test point B is provided between the drain of the eighth transistor T8 and the source of the ninth transistor T9; The driving method includes the following steps: S1. In the initialization stage, turn on the seventh transistor T7 to initialize the first electrolytic capacitor C1 and make it reach a first target voltage; S2. In the data input stage, turn off the seventh transistor T7, and turn on the first transistor T1, the third transistor T3, and the fourth transistor T4 to make the first test point reach a second target voltage; S3. In the light-emitting voltage initialization stage, turn off the first transistor T1, the third transistor T3, and the fourth transistor T4, and turn on the second transistor T2 to make the second electrolytic capacitor C2 reach the third target voltage; S4. In the light-emitting stage, turn off the second transistor T2, and turn on the tenth transistor T10 and the eleventh transistor T11 to input a comparison voltage to the first end of the first electrolytic capacitor C1 and gradually raise the voltage of the first test point. Then turn on the fourth transistor T4 and the eighth transistor T8, and ensure that the fifth transistor T5 is turned off to keep the voltage of the second test point at the fourth target voltage.

6. The driving method according to claim 5, wherein It further includes controlling the power consumption of the first inverter and the second inverter based on the following formula: ； Among them, is the power consumption of the corresponding inverter, is the voltage across the corresponding inverter, is the leakage current of the corresponding inverter, is the load capacitance at the output of the corresponding inverter, is the operating frequency of the corresponding inverter.

7. The driving method according to claim 6, wherein The eighth transistor T8 is an n-type thin-film transistor, and the ninth transistor T9 is a p-type thin-film transistor; The driving method further includes controlling the level conversion time of the first inverter based on the following formula: ； ； Wherein, is the time required for the first inverter to transition from a low level to a high level, is the capacitance of the gate oxide layer in the ninth transistor T9, is the device mobility of the ninth transistor T9, is the device width of the ninth transistor T9, is the device length of the ninth transistor T9, is the high-level voltage across the first inverter, is the low-level voltage across the first inverter, is the preset threshold voltage of the ninth transistor T9, is the output voltage of the first inverter; is the time required for the first inverter to transition from a high level to a low level, is the capacitance of the gate oxide layer in the eighth transistor T8, is the device mobility of the eighth transistor T8, is the device width of the eighth transistor T8, is the device length of the eighth transistor T8, is the preset threshold voltage of the eighth transistor T8.

8. The driving method according to claim 6, characterized in that, The third transistor T3 is an n-type thin-film transistor, and the sixth transistor T6 is a p-type thin-film transistor; The driving method further includes controlling the level conversion time of the second inverter based on the following formula: ； ； Wherein, is the time required for the second inverter to transition from a low level to a high level, is the capacitance of the gate oxide layer in the sixth transistor T6, is the device mobility of the sixth transistor T6, is the device width of the sixth transistor T6, is the device length of the sixth transistor T6, is the high-level voltage across the second inverter, is the low-level voltage across the second inverter, is the preset threshold voltage of the sixth transistor T6, is the output voltage of the second inverter; is the time required for the second inverter to transition from a high level to a low level, is the capacitance of the gate oxide layer in the third transistor T3, is the device mobility of the third transistor T3, is the device width of the third transistor T3, is the device length of the third transistor T3, is the preset threshold voltage of the third transistor T3.

9. The driving method according to claim 7 or 8, characterized in that, It further includes controlling the capacitance of the gate oxide layers of the ninth transistor T9, the eighth transistor T8, the sixth transistor T6, and the third transistor T3 through the following formula: ； ； ； ； Among them, is the capacitance of the gate oxide layer in the ninth transistor T9, is the relative permittivity of silicon dioxide, is the permittivity of vacuum, is the area per unit of the gate oxide layer in the ninth transistor T9, is the accumulated thickness of the gate oxide layer in the ninth transistor T9, is the capacitance of the gate oxide layer in the eighth transistor T8, is the area per unit of the gate oxide layer in the eighth transistor T8, is the accumulated thickness of the gate oxide layer in the eighth transistor T8, is the capacitance of the gate oxide layer in the sixth transistor T6, is the area per unit of the gate oxide layer in the sixth transistor T6, is the accumulated thickness of the gate oxide layer in the sixth transistor T6, is the capacitance of the gate oxide layer in the third transistor T3, is the area per unit of the gate oxide layer in the third transistor T3, is the accumulated thickness of the gate oxide layer in the third transistor T3.

10. A display device, characterized in that, It includes the pixel circuit according to any one of claims 1-4.

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